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Commit | Line | Data |
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ef509b90 | 1 | /* |
e595107e | 2 | * Keystone : Board initialization |
ef509b90 | 3 | * |
e595107e | 4 | * (C) Copyright 2014 |
ef509b90 VA |
5 | * Texas Instruments Incorporated, <www.ti.com> |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
e595107e | 10 | #include "board.h" |
ef509b90 | 11 | #include <common.h> |
5ec66b14 | 12 | #include <spl.h> |
ef509b90 VA |
13 | #include <exports.h> |
14 | #include <fdt_support.h> | |
0b868589 | 15 | #include <asm/arch/ddr3.h> |
497e9e03 | 16 | #include <asm/arch/psc_defs.h> |
909ea9aa | 17 | #include <asm/ti-common/ti-aemif.h> |
0935cac6 | 18 | #include <asm/ti-common/keystone_net.h> |
ef509b90 VA |
19 | |
20 | DECLARE_GLOBAL_DATA_PTR; | |
21 | ||
909ea9aa | 22 | static struct aemif_config aemif_configs[] = { |
ef509b90 | 23 | { /* CS0 */ |
909ea9aa | 24 | .mode = AEMIF_MODE_NAND, |
ef509b90 VA |
25 | .wr_setup = 0xf, |
26 | .wr_strobe = 0x3f, | |
27 | .wr_hold = 7, | |
28 | .rd_setup = 0xf, | |
29 | .rd_strobe = 0x3f, | |
30 | .rd_hold = 7, | |
31 | .turn_around = 3, | |
909ea9aa | 32 | .width = AEMIF_WIDTH_8, |
ef509b90 | 33 | }, |
ef509b90 VA |
34 | }; |
35 | ||
36 | int dram_init(void) | |
37 | { | |
66c98a0c VA |
38 | u32 ddr3_size; |
39 | ||
40 | ddr3_size = ddr3_init(); | |
ef509b90 VA |
41 | |
42 | gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, | |
43 | CONFIG_MAX_RAM_BANK_SIZE); | |
909ea9aa | 44 | aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); |
66c98a0c | 45 | ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); |
ef509b90 VA |
46 | return 0; |
47 | } | |
48 | ||
e595107e HZ |
49 | int board_init(void) |
50 | { | |
59d4cd22 | 51 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
e595107e HZ |
52 | |
53 | return 0; | |
54 | } | |
fc9a8e8d | 55 | |
e595107e | 56 | #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET |
fc9a8e8d KM |
57 | int get_eth_env_param(char *env_name) |
58 | { | |
59 | char *env; | |
e595107e | 60 | int res = -1; |
fc9a8e8d KM |
61 | |
62 | env = getenv(env_name); | |
63 | if (env) | |
64 | res = simple_strtol(env, NULL, 0); | |
65 | ||
66 | return res; | |
67 | } | |
68 | ||
69 | int board_eth_init(bd_t *bis) | |
70 | { | |
e595107e HZ |
71 | int j; |
72 | int res; | |
73 | int port_num; | |
74 | char link_type_name[32]; | |
75 | ||
497e9e03 KI |
76 | /* By default, select PA PLL clock as PA clock source */ |
77 | if (psc_enable_module(KS2_LPSC_PA)) | |
78 | return -1; | |
79 | if (psc_enable_module(KS2_LPSC_CPGMAC)) | |
80 | return -1; | |
81 | if (psc_enable_module(KS2_LPSC_CRYPTO)) | |
82 | return -1; | |
69a3b811 | 83 | pass_pll_pa_clk_enable(); |
497e9e03 | 84 | |
e595107e | 85 | port_num = get_num_eth_ports(); |
fc9a8e8d | 86 | |
e595107e | 87 | for (j = 0; j < port_num; j++) { |
fc9a8e8d KM |
88 | sprintf(link_type_name, "sgmii%d_link_type", j); |
89 | res = get_eth_env_param(link_type_name); | |
90 | if (res >= 0) | |
91 | eth_priv_cfg[j].sgmii_link_type = res; | |
92 | ||
93 | keystone2_emac_initialize(ð_priv_cfg[j]); | |
94 | } | |
95 | ||
96 | return 0; | |
97 | } | |
98 | #endif | |
99 | ||
5ec66b14 HZ |
100 | #ifdef CONFIG_SPL_BUILD |
101 | void spl_board_init(void) | |
102 | { | |
103 | spl_init_keystone_plls(); | |
104 | preloader_console_init(); | |
105 | } | |
106 | ||
107 | u32 spl_boot_device(void) | |
108 | { | |
109 | #if defined(CONFIG_SPL_SPI_LOAD) | |
110 | return BOOT_DEVICE_SPI; | |
111 | #else | |
112 | puts("Unknown boot device\n"); | |
113 | hang(); | |
114 | #endif | |
115 | } | |
116 | #endif | |
117 | ||
ef509b90 | 118 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
e895a4b0 | 119 | int ft_board_setup(void *blob, bd_t *bd) |
ef509b90 | 120 | { |
e595107e HZ |
121 | int lpae; |
122 | char *env; | |
123 | char *endp; | |
124 | int nbanks; | |
ef509b90 | 125 | u64 size[2]; |
e595107e | 126 | u64 start[2]; |
e595107e | 127 | int nodeoffset; |
ef509b90 | 128 | u32 ddr3a_size; |
e595107e | 129 | int unitrd_fixup = 0; |
ef509b90 VA |
130 | |
131 | env = getenv("mem_lpae"); | |
132 | lpae = env && simple_strtol(env, NULL, 0); | |
0bedbb81 MK |
133 | env = getenv("uinitrd_fixup"); |
134 | unitrd_fixup = env && simple_strtol(env, NULL, 0); | |
ef509b90 VA |
135 | |
136 | ddr3a_size = 0; | |
137 | if (lpae) { | |
138 | env = getenv("ddr3a_size"); | |
139 | if (env) | |
140 | ddr3a_size = simple_strtol(env, NULL, 10); | |
141 | if ((ddr3a_size != 8) && (ddr3a_size != 4)) | |
142 | ddr3a_size = 0; | |
143 | } | |
144 | ||
145 | nbanks = 1; | |
146 | start[0] = bd->bi_dram[0].start; | |
147 | size[0] = bd->bi_dram[0].size; | |
148 | ||
149 | /* adjust memory start address for LPAE */ | |
150 | if (lpae) { | |
e595107e | 151 | start[0] -= CONFIG_SYS_SDRAM_BASE; |
ef509b90 VA |
152 | start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; |
153 | } | |
154 | ||
155 | if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { | |
156 | size[1] = ((u64)ddr3a_size - 2) << 30; | |
157 | start[1] = 0x880000000; | |
158 | nbanks++; | |
159 | } | |
160 | ||
161 | /* reserve memory at start of bank */ | |
30491fc8 | 162 | env = getenv("mem_reserve_head"); |
ef509b90 VA |
163 | if (env) { |
164 | start[0] += ustrtoul(env, &endp, 0); | |
165 | size[0] -= ustrtoul(env, &endp, 0); | |
166 | } | |
167 | ||
30491fc8 | 168 | env = getenv("mem_reserve"); |
ef509b90 VA |
169 | if (env) |
170 | size[0] -= ustrtoul(env, &endp, 0); | |
171 | ||
172 | fdt_fixup_memory_banks(blob, start, size, nbanks); | |
173 | ||
174 | /* Fix up the initrd */ | |
0bedbb81 | 175 | if (lpae && unitrd_fixup) { |
ef509b90 | 176 | int err; |
e595107e HZ |
177 | u32 *prop1, *prop2; |
178 | u64 initrd_start, initrd_end; | |
0bedbb81 | 179 | |
ef509b90 VA |
180 | nodeoffset = fdt_path_offset(blob, "/chosen"); |
181 | if (nodeoffset >= 0) { | |
182 | prop1 = (u32 *)fdt_getprop(blob, nodeoffset, | |
183 | "linux,initrd-start", NULL); | |
184 | prop2 = (u32 *)fdt_getprop(blob, nodeoffset, | |
185 | "linux,initrd-end", NULL); | |
186 | if (prop1 && prop2) { | |
187 | initrd_start = __be32_to_cpu(*prop1); | |
e595107e | 188 | initrd_start -= CONFIG_SYS_SDRAM_BASE; |
ef509b90 VA |
189 | initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; |
190 | initrd_start = __cpu_to_be64(initrd_start); | |
191 | initrd_end = __be32_to_cpu(*prop2); | |
e595107e | 192 | initrd_end -= CONFIG_SYS_SDRAM_BASE; |
ef509b90 VA |
193 | initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; |
194 | initrd_end = __cpu_to_be64(initrd_end); | |
195 | ||
196 | err = fdt_delprop(blob, nodeoffset, | |
197 | "linux,initrd-start"); | |
198 | if (err < 0) | |
199 | puts("error deleting initrd-start\n"); | |
200 | ||
201 | err = fdt_delprop(blob, nodeoffset, | |
202 | "linux,initrd-end"); | |
203 | if (err < 0) | |
204 | puts("error deleting initrd-end\n"); | |
205 | ||
206 | err = fdt_setprop(blob, nodeoffset, | |
207 | "linux,initrd-start", | |
208 | &initrd_start, | |
209 | sizeof(initrd_start)); | |
210 | if (err < 0) | |
211 | puts("error adding initrd-start\n"); | |
212 | ||
213 | err = fdt_setprop(blob, nodeoffset, | |
214 | "linux,initrd-end", | |
215 | &initrd_end, | |
216 | sizeof(initrd_end)); | |
217 | if (err < 0) | |
218 | puts("error adding linux,initrd-end\n"); | |
219 | } | |
220 | } | |
221 | } | |
e895a4b0 SG |
222 | |
223 | return 0; | |
ef509b90 VA |
224 | } |
225 | ||
226 | void ft_board_setup_ex(void *blob, bd_t *bd) | |
227 | { | |
e595107e HZ |
228 | int lpae; |
229 | u64 size; | |
230 | char *env; | |
231 | u64 *reserve_start; | |
ef509b90 VA |
232 | |
233 | env = getenv("mem_lpae"); | |
234 | lpae = env && simple_strtol(env, NULL, 0); | |
235 | ||
236 | if (lpae) { | |
237 | /* | |
238 | * the initrd and other reserved memory areas are | |
239 | * embedded in in the DTB itslef. fix up these addresses | |
240 | * to 36 bit format | |
241 | */ | |
242 | reserve_start = (u64 *)((char *)blob + | |
243 | fdt_off_mem_rsvmap(blob)); | |
244 | while (1) { | |
245 | *reserve_start = __cpu_to_be64(*reserve_start); | |
246 | size = __cpu_to_be64(*(reserve_start + 1)); | |
247 | if (size) { | |
e595107e | 248 | *reserve_start -= CONFIG_SYS_SDRAM_BASE; |
ef509b90 VA |
249 | *reserve_start += |
250 | CONFIG_SYS_LPAE_SDRAM_BASE; | |
251 | *reserve_start = | |
252 | __cpu_to_be64(*reserve_start); | |
253 | } else { | |
254 | break; | |
255 | } | |
256 | reserve_start += 2; | |
257 | } | |
258 | } | |
89f44bb0 VA |
259 | |
260 | ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); | |
ef509b90 VA |
261 | } |
262 | #endif |