[thirdparty/u-boot.git] / board / ti / ks2_evm / board_k2e.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * K2E EVM : Board initialization
 *
 * (C) Copyright 2014
 *     Texas Instruments Incorporated, <www.ti.com>
 */

#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>

unsigned int get_external_clk(u32 clk)
{
	unsigned int clk_freq;

	switch (clk) {
	case sys_clk:
		clk_freq = 100000000;
		break;
	case alt_core_clk:
		clk_freq = 100000000;
		break;
	case pa_clk:
		clk_freq = 100000000;
		break;
	case ddr3a_clk:
		clk_freq = 100000000;
		break;
	default:
		clk_freq = 0;
		break;
	}

	return clk_freq;
}

static struct pll_init_data core_pll_config[NUM_SPDS] = {
	[SPD800]	= CORE_PLL_800,
	[SPD850]	= CORE_PLL_850,
	[SPD1000]	= CORE_PLL_1000,
	[SPD1250]	= CORE_PLL_1250,
	[SPD1350]	= CORE_PLL_1350,
	[SPD1400]	= CORE_PLL_1400,
	[SPD1500]	= CORE_PLL_1500,
};

/* DEV and ARM speed definitions as specified in DEVSPEED register */
int speeds[DEVSPEED_NUMSPDS] = {
	SPD850,
	SPD1000,
	SPD1250,
	SPD1350,
	SPD1400,
	SPD1500,
	SPD1400,
	SPD1350,
	SPD1250,
	SPD1000,
	SPD850,
	SPD800,
};

s16 divn_val[16] = {
	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

static struct pll_init_data pa_pll_config =
	PASS_PLL_1000;

struct pll_init_data *get_pll_init_data(int pll)
{
	int speed;
	struct pll_init_data *data;

	switch (pll) {
	case MAIN_PLL:
		speed = get_max_dev_speed(speeds);
		data = &core_pll_config[speed];
		break;
	case PASS_PLL:
		data = &pa_pll_config;
		break;
	default:
		data = NULL;
	}

	return data;
}

#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
	{
		.int_name        = "K2E_EMAC0",
		.rx_flow         = 0,
		.phy_addr        = 0,
		.slave_port      = 1,
		.sgmii_link_type = SGMII_LINK_MAC_PHY,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC1",
		.rx_flow         = 8,
		.phy_addr        = 1,
		.slave_port      = 2,
		.sgmii_link_type = SGMII_LINK_MAC_PHY,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC2",
		.rx_flow         = 16,
		.phy_addr        = 2,
		.slave_port      = 3,
		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC3",
		.rx_flow         = 24,
		.phy_addr        = 3,
		.slave_port      = 4,
		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC4",
		.rx_flow         = 32,
		.phy_addr        = 4,
		.slave_port      = 5,
		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC5",
		.rx_flow         = 40,
		.phy_addr        = 5,
		.slave_port      = 6,
		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC6",
		.rx_flow         = 48,
		.phy_addr        = 6,
		.slave_port      = 7,
		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
	{
		.int_name        = "K2E_EMAC7",
		.rx_flow         = 56,
		.phy_addr        = 7,
		.slave_port      = 8,
		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
		.phy_if          = PHY_INTERFACE_MODE_SGMII,
	},
};

int get_num_eth_ports(void)
{
	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif

#if defined(CONFIG_MULTI_DTB_FIT)
int board_fit_config_name_match(const char *name)
{
	if (!strcmp(name, "keystone-k2e-evm"))
		return 0;

	return -1;
}
#endif

#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
	init_plls();

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a9068479 HZ	2	/*
	3	* K2E EVM : Board initialization
	4	*
	5	* (C) Copyright 2014
	6	* Texas Instruments Incorporated, <www.ti.com>
a9068479 HZ	7	*/
	8
	9	#include <common.h>
	10	#include <asm/arch/ddr3.h>
	11	#include <asm/arch/hardware.h>
00b821f1	12	#include <asm/ti-common/keystone_net.h>
a9068479	13
ee3c6532 LV	14	unsigned int get_external_clk(u32 clk)
	15	{
	16	unsigned int clk_freq;
	17
	18	switch (clk) {
	19	case sys_clk:
	20	clk_freq = 100000000;
	21	break;
	22	case alt_core_clk:
	23	clk_freq = 100000000;
	24	break;
	25	case pa_clk:
	26	clk_freq = 100000000;
	27	break;
	28	case ddr3a_clk:
	29	clk_freq = 100000000;
	30	break;
	31	default:
	32	clk_freq = 0;
	33	break;
	34	}
	35
	36	return clk_freq;
	37	}
a9068479	38
7b50e159 LV	39	static struct pll_init_data core_pll_config[NUM_SPDS] = {
	40	[SPD800] = CORE_PLL_800,
	41	[SPD850] = CORE_PLL_850,
	42	[SPD1000] = CORE_PLL_1000,
	43	[SPD1250] = CORE_PLL_1250,
	44	[SPD1350] = CORE_PLL_1350,
	45	[SPD1400] = CORE_PLL_1400,
	46	[SPD1500] = CORE_PLL_1500,
	47	};
	48
	49	/* DEV and ARM speed definitions as specified in DEVSPEED register */
	50	int speeds[DEVSPEED_NUMSPDS] = {
	51	SPD850,
	52	SPD1000,
	53	SPD1250,
	54	SPD1350,
	55	SPD1400,
	56	SPD1500,
	57	SPD1400,
	58	SPD1350,
	59	SPD1250,
	60	SPD1000,
	61	SPD850,
	62	SPD800,
a9068479 HZ	63	};
a9068479 HZ	64
c321a236 LV	65	s16 divn_val[16] = {
	66	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	67	};
	68
61f66fd5 VA	69	static struct pll_init_data pa_pll_config =
	70	PASS_PLL_1000;
	71
94069301 LV	72	struct pll_init_data *get_pll_init_data(int pll)
	73	{
	74	int speed;
	75	struct pll_init_data *data;
	76
	77	switch (pll) {
	78	case MAIN_PLL:
5cd1f6bd	79	speed = get_max_dev_speed(speeds);
94069301 LV	80	data = &core_pll_config[speed];
	81	break;
	82	case PASS_PLL:
	83	data = &pa_pll_config;
	84	break;
	85	default:
	86	data = NULL;
	87	}
	88
	89	return data;
	90	}
	91
00b821f1 HZ	92	#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
	93	struct eth_priv_t eth_priv_cfg[] = {
	94	{
	95	.int_name = "K2E_EMAC0",
	96	.rx_flow = 0,
	97	.phy_addr = 0,
	98	.slave_port = 1,
	99	.sgmii_link_type = SGMII_LINK_MAC_PHY,
bf7bd4e7	100	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	101	},
	102	{
	103	.int_name = "K2E_EMAC1",
	104	.rx_flow = 8,
	105	.phy_addr = 1,
	106	.slave_port = 2,
	107	.sgmii_link_type = SGMII_LINK_MAC_PHY,
bf7bd4e7	108	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	109	},
	110	{
	111	.int_name = "K2E_EMAC2",
	112	.rx_flow = 16,
	113	.phy_addr = 2,
	114	.slave_port = 3,
	115	.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
bf7bd4e7	116	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	117	},
	118	{
	119	.int_name = "K2E_EMAC3",
	120	.rx_flow = 24,
	121	.phy_addr = 3,
	122	.slave_port = 4,
	123	.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
bf7bd4e7	124	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	125	},
	126	{
	127	.int_name = "K2E_EMAC4",
	128	.rx_flow = 32,
	129	.phy_addr = 4,
	130	.slave_port = 5,
	131	.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
bf7bd4e7	132	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	133	},
	134	{
	135	.int_name = "K2E_EMAC5",
	136	.rx_flow = 40,
	137	.phy_addr = 5,
	138	.slave_port = 6,
	139	.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
bf7bd4e7	140	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	141	},
	142	{
	143	.int_name = "K2E_EMAC6",
	144	.rx_flow = 48,
	145	.phy_addr = 6,
	146	.slave_port = 7,
	147	.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
bf7bd4e7	148	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	149	},
	150	{
	151	.int_name = "K2E_EMAC7",
	152	.rx_flow = 56,
	153	.phy_addr = 7,
	154	.slave_port = 8,
	155	.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
bf7bd4e7	156	.phy_if = PHY_INTERFACE_MODE_SGMII,
00b821f1 HZ	157	},
	158	};
	159
	160	int get_num_eth_ports(void)
	161	{
	162	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
	163	}
	164	#endif
	165
11955590	166	#if defined(CONFIG_MULTI_DTB_FIT)
7234f215 CJF	167	int board_fit_config_name_match(const char *name)
	168	{
	169	if (!strcmp(name, "keystone-k2e-evm"))
	170	return 0;
	171
	172	return -1;
	173	}
	174	#endif
	175
a9068479 HZ	176	#if defined(CONFIG_BOARD_EARLY_INIT_F)
	177	int board_early_init_f(void)
	178	{
94069301	179	init_plls();
61f66fd5	180
a9068479 HZ	181	return 0;
	182	}
	183	#endif
5ec66b14 HZ	184
5ec66b14 HZ	185	#ifdef CONFIG_SPL_BUILD
5ec66b14 HZ	186	void spl_init_keystone_plls(void)
5ec66b14 HZ	187	{
94069301	188	init_plls();
5ec66b14 HZ	189	}
5ec66b14 HZ	190	#endif