[thirdparty/u-boot.git] / board / ti / ks2_evm / board_k2hk.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * K2HK EVM : Board initialization
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 */

#include <common.h>
#include <image.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>

unsigned int external_clk[ext_clk_count] = {
	[sys_clk]	=	122880000,
	[alt_core_clk]	=	125000000,
	[pa_clk]	=	122880000,
	[tetris_clk]	=	125000000,
	[ddr3a_clk]	=	100000000,
	[ddr3b_clk]	=	100000000,
};

unsigned int get_external_clk(u32 clk)
{
	unsigned int clk_freq;

	switch (clk) {
	case sys_clk:
		clk_freq = 122880000;
		break;
	case alt_core_clk:
		clk_freq = 125000000;
		break;
	case pa_clk:
		clk_freq = 122880000;
		break;
	case tetris_clk:
		clk_freq = 125000000;
		break;
	case ddr3a_clk:
		clk_freq = 100000000;
		break;
	case ddr3b_clk:
		clk_freq = 100000000;
		break;
	default:
		clk_freq = 0;
		break;
	}

	return clk_freq;
}

static struct pll_init_data core_pll_config[NUM_SPDS] = {
	[SPD800]	= CORE_PLL_799,
	[SPD1000]	= CORE_PLL_999,
	[SPD1200]	= CORE_PLL_1200,
};

s16 divn_val[16] = {
	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

static struct pll_init_data tetris_pll_config[] = {
	[SPD800]	= TETRIS_PLL_800,
	[SPD1000]	= TETRIS_PLL_1000,
	[SPD1200]	= TETRIS_PLL_1200,
	[SPD1350]	= TETRIS_PLL_1350,
	[SPD1400]	= TETRIS_PLL_1400,
};

static struct pll_init_data pa_pll_config =
	PASS_PLL_983;

struct pll_init_data *get_pll_init_data(int pll)
{
	int speed;
	struct pll_init_data *data;

	switch (pll) {
	case MAIN_PLL:
		speed = get_max_dev_speed(speeds);
		data = &core_pll_config[speed];
		break;
	case TETRIS_PLL:
		speed = get_max_arm_speed(speeds);
		data = &tetris_pll_config[speed];
		break;
	case PASS_PLL:
		data = &pa_pll_config;
		break;
	default:
		data = NULL;
	}

	return data;
}

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	init_plls();

	return 0;
}
#endif

#if defined(CONFIG_MULTI_DTB_FIT)
int board_fit_config_name_match(const char *name)
{
	if (!strcmp(name, "keystone-k2hk-evm"))
		return 0;

	return -1;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e595107e HZ	2	/*
	3	* K2HK EVM : Board initialization
	4	*
	5	* (C) Copyright 2012-2014
	6	* Texas Instruments Incorporated, <www.ti.com>
e595107e HZ	7	*/
	8
	9	#include <common.h>
4d72caa5	10	#include <image.h>
61f66fd5	11	#include <asm/arch/clock.h>
e595107e	12	#include <asm/arch/hardware.h>
0935cac6	13	#include <asm/ti-common/keystone_net.h>
e595107e	14
e595107e HZ	15	unsigned int external_clk[ext_clk_count] = {
	16	[sys_clk] = 122880000,
	17	[alt_core_clk] = 125000000,
	18	[pa_clk] = 122880000,
	19	[tetris_clk] = 125000000,
	20	[ddr3a_clk] = 100000000,
	21	[ddr3b_clk] = 100000000,
e595107e HZ	22	};
e595107e HZ	23
ee3c6532 LV	24	unsigned int get_external_clk(u32 clk)
	25	{
	26	unsigned int clk_freq;
	27
	28	switch (clk) {
	29	case sys_clk:
	30	clk_freq = 122880000;
	31	break;
	32	case alt_core_clk:
	33	clk_freq = 125000000;
	34	break;
	35	case pa_clk:
	36	clk_freq = 122880000;
	37	break;
	38	case tetris_clk:
	39	clk_freq = 125000000;
	40	break;
	41	case ddr3a_clk:
	42	clk_freq = 100000000;
	43	break;
	44	case ddr3b_clk:
	45	clk_freq = 100000000;
	46	break;
	47	default:
	48	clk_freq = 0;
	49	break;
	50	}
	51
	52	return clk_freq;
	53	}
	54
7b50e159 LV	55	static struct pll_init_data core_pll_config[NUM_SPDS] = {
	56	[SPD800] = CORE_PLL_799,
	57	[SPD1000] = CORE_PLL_999,
	58	[SPD1200] = CORE_PLL_1200,
61f66fd5 VA	59	};
61f66fd5 VA	60
c321a236 LV	61	s16 divn_val[16] = {
	62	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	63	};
	64
61f66fd5	65	static struct pll_init_data tetris_pll_config[] = {
7b50e159 LV	66	[SPD800] = TETRIS_PLL_800,
	67	[SPD1000] = TETRIS_PLL_1000,
	68	[SPD1200] = TETRIS_PLL_1200,
	69	[SPD1350] = TETRIS_PLL_1350,
	70	[SPD1400] = TETRIS_PLL_1400,
e595107e HZ	71	};
e595107e HZ	72
61f66fd5 VA	73	static struct pll_init_data pa_pll_config =
	74	PASS_PLL_983;
	75
94069301 LV	76	struct pll_init_data *get_pll_init_data(int pll)
	77	{
	78	int speed;
	79	struct pll_init_data *data;
	80
	81	switch (pll) {
	82	case MAIN_PLL:
5cd1f6bd	83	speed = get_max_dev_speed(speeds);
94069301 LV	84	data = &core_pll_config[speed];
	85	break;
	86	case TETRIS_PLL:
5cd1f6bd	87	speed = get_max_arm_speed(speeds);
94069301 LV	88	data = &tetris_pll_config[speed];
	89	break;
	90	case PASS_PLL:
	91	data = &pa_pll_config;
	92	break;
	93	default:
	94	data = NULL;
	95	}
	96
	97	return data;
	98	}
	99
e595107e HZ	100	#ifdef CONFIG_BOARD_EARLY_INIT_F
	101	int board_early_init_f(void)
	102	{
94069301	103	init_plls();
61f66fd5	104
e595107e HZ	105	return 0;
	106	}
	107	#endif
5ec66b14	108
11955590	109	#if defined(CONFIG_MULTI_DTB_FIT)
7234f215 CJF	110	int board_fit_config_name_match(const char *name)
	111	{
	112	if (!strcmp(name, "keystone-k2hk-evm"))
	113	return 0;
	114
	115	return -1;
	116	}
	117	#endif
	118
5ec66b14	119	#ifdef CONFIG_SPL_BUILD
5ec66b14 HZ	120	void spl_init_keystone_plls(void)
5ec66b14 HZ	121	{
94069301	122	init_plls();
5ec66b14 HZ	123	}
5ec66b14 HZ	124	#endif