[people/ms/u-boot.git] / board / ti / omap1610inn / omap1610innovator.c

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <Kshitij@ti.com>
 *
 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <netdev.h>
#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_CS_AUTOBOOT
unsigned long omap_flash_base;
#endif

void flash__init (void);
void ether__init (void);
void set_muxconf_regs (void);
void peripheral_power_enable (void);

#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)

static inline void delay (unsigned long loops)
{
	__asm__ volatile ("1:\n"
		"subs %0, %1, #1\n"
		"bne 1b":"=r" (loops):"0" (loops));
}

/*
 * Miscellaneous platform dependent initialisations
 */

int board_init (void)
{
	if (machine_is_omap_h2())
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
	else if (machine_is_omap_innovator())
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
	else
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x10000100;

	/* Configure MUX settings */
	set_muxconf_regs ();
	peripheral_power_enable ();

/* this speeds up your boot a quite a bit.  However to make it
 *  work, you need make sure your kernel startup flush bug is fixed.
 *  ... rkw ...
 */
	icache_enable ();

	flash__init ();
	ether__init ();
	return 0;
}


int misc_init_r (void)
{
	/* currently empty */
	return (0);
}

/******************************
 Routine:
 Description:
******************************/
void flash__init (void)
{
#define EMIFS_GlB_Config_REG 0xfffecc0c
	unsigned int regval;

#ifdef CONFIG_CS_AUTOBOOT
	 /* Check swapping of CS0 and CS3, set flash base accordingly */
	omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
					PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
#endif
	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
	/* Turn off write protection for flash devices. */
	regval = regval | 0x0001;
	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
}
/*************************************************************
 Routine:ether__init
 Description: take the Ethernet controller out of reset and wait
			   for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
#define ETH_CONTROL_REG 0x0400030b

#ifdef CONFIG_H2_OMAP1610
	#define LAN_RESET_REGISTER 0x0400001c

	/* The debug board on which the lan chip resides may not be powered
	 * ON at the same time as the OMAP chip. So wait in a loop until the
	 * lan reset register (on the debug board) is available (powered on)
	 * and reset the lan chip.
	 */

	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
	do {
		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
		udelay (3);
	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);

	do {
		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
		udelay (3);
	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
#endif

	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
	udelay (3);
}

/******************************
 Routine:
 Description:
******************************/
int dram_init (void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

	return 0;
}

/******************************************************
 Routine: set_muxconf_regs
 Description: Setting up the configuration Mux registers
			  specific to the hardware
*******************************************************/
void set_muxconf_regs (void)
{
	volatile unsigned int *MuxConfReg;
	/* set each registers to its reset value; */
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
	/* setup for UART1 */
	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
	/* setup for UART2 */
	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
	/* Disable Uwire CS Hi-Z */
	*MuxConfReg |= 0x08000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
	/*setup mux for UART3 */
	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
	*MuxConfReg &= ~0x0000003e;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
	/* Disable Uwire CS Hi-Z */
	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
	/*  hardware will actually use TX and RTS based on bit 25 in  */
	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!  */
	*MuxConfReg |= 0x00201000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
	/* setup for UART2 */
	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
	/*  hardware will actually use TX and RTS based on bit 24 in  */
	/*  FUNC_MUX_CTRL_0. */
	*MuxConfReg |= 0x09000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
	*MuxConfReg = 0x00000000;
	/* mux setup for SD/MMC driver */
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
	*MuxConfReg &= 0xFFFE0FFF;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
	/* bit 13 for MMC2 XOR_CLK */
	*MuxConfReg &= ~(0x00002000);
	/* bit 29 for UART 1 */
	*MuxConfReg &= ~(0x00002000);
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
	*MuxConfReg |= 0x000C0000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
	*MuxConfReg &= ~(0x00000070);
	*MuxConfReg &= ~(0x00000008);
	*MuxConfReg |= 0x00000003;
	*MuxConfReg |= 0x00000180;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
	/* bit 17, software controls VBUS */
	*MuxConfReg &= ~(0x00020000);
	/* Enable USB 48 and 12M clocks */
	*MuxConfReg |= 0x00000200;
	*MuxConfReg &= ~(0x00000180);
	/*2.75V for MMCSDIO1 */
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
	*MuxConfReg = 0x00001FE7;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
	*MuxConfReg = 0x00000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
	*MuxConfReg = 0x00000000;
	/* Turn on UART2 48 MHZ clock */
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
	*MuxConfReg |= 0x40000000;
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
	/* setup for USB VBus detection OMAP161x */
	*MuxConfReg |= 0x00040000;	/* bit 18 */
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
	/* PullUps for SD/MMC driver */
	*MuxConfReg |= ~(0xFFFE0FFF);
	MuxConfReg =
		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
	*MuxConfReg = COMP_MODE_ENABLE;
}

/******************************************************
 Routine: peripheral_power_enable
 Description: Enable the power for UART1
*******************************************************/
void peripheral_power_enable (void)
{
#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)

	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
}

#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_LAN91C96
	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
#endif
	return rc;
}
#endif
Commit	Line	Data
6f21347d WD	1	/*
	2	* (C) Copyright 2002
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	*
	6	* (C) Copyright 2002
	7	* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
	8	*
	9	* (C) Copyright 2003
	10	* Texas Instruments, <www.ti.com>
	11	* Kshitij Gupta <Kshitij@ti.com>
	12	*
63e73c9a	13	* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
028ab6b5	14	*
6f21347d WD	15	* See file CREDITS for list of people who contributed to this
	16	* project.
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License as
	20	* published by the Free Software Foundation; either version 2 of
	21	* the License, or (at your option) any later version.
	22	*
	23	* This program is distributed in the hope that it will be useful,
	24	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	26	* GNU General Public License for more details.
	27	*
	28	* You should have received a copy of the GNU General Public License
	29	* along with this program; if not, write to the Free Software
	30	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	31	* MA 02111-1307 USA
	32	*/
	33
	34	#include <common.h>
1ab70f6f	35	#include <netdev.h>
6f21347d WD	36	#if defined(CONFIG_OMAP1610)
	37	#include <./configs/omap1510.h>
	38	#endif
	39
d87080b7 WD	40	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	41
3ff02c27 WD	42	#ifdef CONFIG_CS_AUTOBOOT
	43	unsigned long omap_flash_base;
	44	#endif
	45
6f21347d WD	46	void flash__init (void);
	47	void ether__init (void);
	48	void set_muxconf_regs (void);
	49	void peripheral_power_enable (void);
	50
	51	#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
	52
	53	static inline void delay (unsigned long loops)
	54	{
	55	__asm__ volatile ("1:\n"
	56	"subs %0, %1, #1\n"
	57	"bne 1b":"=r" (loops):"0" (loops));
	58	}
	59
	60	/*
	61	* Miscellaneous platform dependent initialisations
	62	*/
	63
	64	int board_init (void)
	65	{
a1f4a3dd WD	66	if (machine_is_omap_h2())
	67	gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
	68	else if (machine_is_omap_innovator())
	69	gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
	70	else
	71	gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;
6f21347d WD	72
	73	/* adress of boot parameters */
	74	gd->bd->bi_boot_params = 0x10000100;
	75
	76	/* Configure MUX settings */
	77	set_muxconf_regs ();
	78	peripheral_power_enable ();
	79
	80	/* this speeds up your boot a quite a bit. However to make it
	81	* work, you need make sure your kernel startup flush bug is fixed.
	82	* ... rkw ...
	83	*/
	84	icache_enable ();
	85
	86	flash__init ();
	87	ether__init ();
	88	return 0;
	89	}
	90
	91
	92	int misc_init_r (void)
	93	{
	94	/* currently empty */
	95	return (0);
	96	}
	97
	98	/******************************
	99	Routine:
	100	Description:
	101	******************************/
	102	void flash__init (void)
	103	{
	104	#define EMIFS_GlB_Config_REG 0xfffecc0c
	105	unsigned int regval;
3ff02c27 WD	106
	107	#ifdef CONFIG_CS_AUTOBOOT
	108	/* Check swapping of CS0 and CS3, set flash base accordingly */
ca0e7748 WD	109	omap_flash_base = ((((u32 )OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
ca0e7748 WD	110	PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
3ff02c27	111	#endif
6f21347d WD	112	regval = ((volatile unsigned int ) EMIFS_GlB_Config_REG);
	113	/* Turn off write protection for flash devices. */
	114	regval = regval \| 0x0001;
	115	((volatile unsigned int ) EMIFS_GlB_Config_REG) = regval;
	116	}
	117	/*************************************************************
	118	Routine:ether__init
	119	Description: take the Ethernet controller out of reset and wait
53677ef1	120	for the EEPROM load to complete.
6f21347d WD	121	*************************************************************/
	122	void ether__init (void)
	123	{
63e73c9a WD	124	#define ETH_CONTROL_REG 0x0400030b
	125
	126	#ifdef CONFIG_H2_OMAP1610
	127	#define LAN_RESET_REGISTER 0x0400001c
	128
028ab6b5 WD	129	/* The debug board on which the lan chip resides may not be powered
	130	* ON at the same time as the OMAP chip. So wait in a loop until the
	131	* lan reset register (on the debug board) is available (powered on)
63e73c9a WD	132	* and reset the lan chip.
	133	*/
	134
	135	((volatile unsigned short ) LAN_RESET_REGISTER) = 0x0000;
	136	do {
	137	((volatile unsigned short ) LAN_RESET_REGISTER) = 0x0001;
	138	udelay (3);
	139	} while (((volatile unsigned short ) LAN_RESET_REGISTER) != 0x0001);
028ab6b5	140
63e73c9a WD	141	do {
	142	((volatile unsigned short ) LAN_RESET_REGISTER) = 0x0000;
	143	udelay (3);
	144	} while (((volatile unsigned short ) LAN_RESET_REGISTER) != 0x0000);
	145	#endif
6f21347d WD	146
	147	((volatile unsigned char ) ETH_CONTROL_REG) &= ~0x01;
	148	udelay (3);
	149	}
	150
	151	/******************************
	152	Routine:
	153	Description:
	154	******************************/
	155	int dram_init (void)
	156	{
6f21347d WD	157	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	158	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	159
	160	return 0;
	161	}
	162
	163	/******************************************************
	164	Routine: set_muxconf_regs
	165	Description: Setting up the configuration Mux registers
53677ef1	166	specific to the hardware
6f21347d WD	167	*******************************************************/
	168	void set_muxconf_regs (void)
	169	{
	170	volatile unsigned int *MuxConfReg;
	171	/* set each registers to its reset value; */
	172	MuxConfReg =
	173	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
	174	/* setup for UART1 */
	175	MuxConfReg &= ~(0x02000000); / bit 25 */
	176	/* setup for UART2 */
	177	MuxConfReg &= ~(0x01000000); / bit 24 */
	178	/* Disable Uwire CS Hi-Z */
	179	*MuxConfReg \|= 0x08000000;
	180	MuxConfReg =
	181	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
	182	*MuxConfReg = 0x00000000;
	183	MuxConfReg =
	184	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
	185	*MuxConfReg = 0x00000000;
	186	MuxConfReg =
	187	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
	188	*MuxConfReg = 0x00000000;
	189	MuxConfReg =
	190	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
	191	/setup mux for UART3 /
	192	MuxConfReg \|= 0x00000001; / bit3, 1, 0 (mux0 5,5,26) */
	193	*MuxConfReg &= ~0x0000003e;
	194	MuxConfReg =
	195	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
	196	*MuxConfReg = 0x00000000;
	197	MuxConfReg =
	198	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
	199	/* Disable Uwire CS Hi-Z */
	200	MuxConfReg \|= 0x00001200; /bit 9 for CS0 12 for CS3 */
	201	MuxConfReg =
	202	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
	203	/* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
	204	/* hardware will actually use TX and RTS based on bit 25 in */
	205	/* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
	206	*MuxConfReg \|= 0x00201000;
	207	MuxConfReg =
	208	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
	209	*MuxConfReg = 0x00000000;
	210	MuxConfReg =
	211	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
	212	*MuxConfReg = 0x00000000;
	213	MuxConfReg =
	214	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
	215	/* setup for UART2 */
	216	/* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
	217	/* hardware will actually use TX and RTS based on bit 24 in */
	218	/* FUNC_MUX_CTRL_0. */
	219	*MuxConfReg \|= 0x09000000;
	220	MuxConfReg =
	221	(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
	222	*MuxConfReg = 0x00000000;
	223	MuxConfReg =
	224	(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
	225	*MuxConfReg = 0x00000000;
	226	/* mux setup for SD/MMC driver */
	227	MuxConfReg =
	228	(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
	229	*MuxConfReg &= 0xFFFE0FFF;
	230	MuxConfReg =
231	(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
232	*MuxConfReg = 0x00000000;
233	MuxConfReg =
234	(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
235	/* bit 13 for MMC2 XOR_CLK */
236	*MuxConfReg &= ~(0x00002000);
237	/* bit 29 for UART 1 */
238	*MuxConfReg &= ~(0x00002000);
239	MuxConfReg =
240	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
241	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
242	*MuxConfReg \|= 0x000C0000;
243	MuxConfReg =
244	(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
245	*MuxConfReg &= ~(0x00000070);
246	*MuxConfReg &= ~(0x00000008);
247	*MuxConfReg \|= 0x00000003;
248	*MuxConfReg \|= 0x00000180;
249	MuxConfReg =
250	(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
251	/* bit 17, software controls VBUS */
252	*MuxConfReg &= ~(0x00020000);
253	/* Enable USB 48 and 12M clocks */
254	*MuxConfReg \|= 0x00000200;
255	*MuxConfReg &= ~(0x00000180);
256	/2.75V for MMCSDIO1 /
257	MuxConfReg =
258	(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
259	*MuxConfReg = 0x00001FE7;
260	MuxConfReg =
261	(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
262	*MuxConfReg = 0x00000000;
263	MuxConfReg =
264	(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
265	*MuxConfReg = 0x00000000;
266	MuxConfReg =
267	(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
268	*MuxConfReg = 0x00000000;
269	MuxConfReg =
270	(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
271	*MuxConfReg = 0x00000000;
272	MuxConfReg =
273	(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
274	*MuxConfReg = 0x00000000;
275	MuxConfReg =
276	(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
277	*MuxConfReg = 0x00000000;
278	/* Turn on UART2 48 MHZ clock */
279	MuxConfReg =
280	(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
281	*MuxConfReg \|= 0x40000000;
282	MuxConfReg =
283	(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
284	/* setup for USB VBus detection OMAP161x */
285	MuxConfReg \|= 0x00040000; / bit 18 */
286	MuxConfReg =
287	(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
288	/* PullUps for SD/MMC driver */
289	*MuxConfReg \|= ~(0xFFFE0FFF);
290	MuxConfReg =
291	(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
292	*MuxConfReg = COMP_MODE_ENABLE;
293	}
294
295	/******************************************************
296	Routine: peripheral_power_enable
297	Description: Enable the power for UART1
298	*******************************************************/
299	void peripheral_power_enable (void)
300	{
301	#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
302	#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
303
304	*SW_CLOCK_REQUEST \|= UART1_48MHZ_ENABLE;
305	}
1ab70f6f BW	306
	307	#ifdef CONFIG_CMD_NET
	308	int board_eth_init(bd_t *bis)
	309	{
	310	int rc = 0;
	311	#ifdef CONFIG_LAN91C96
	312	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
	313	#endif
	314	return rc;
	315	}
	316	#endif