[people/ms/u-boot.git] / board / ti / omap5_uevm / evm.c

/*
 * (C) Copyright 2010
 * Texas Instruments Incorporated, <www.ti.com>
 * Aneesh V       <aneesh@ti.com>
 * Steve Sakoman  <steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <palmas.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <tca642x.h>

#include "mux_data.h"

#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
#include <sata.h>
#include <usb.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include <asm/arch/sata.h>

#define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
#define DIE_ID_REG_OFFSET	0x200

#endif

DECLARE_GLOBAL_DATA_PTR;

const struct omap_sysinfo sysinfo = {
	"Board: OMAP5432 uEVM\n"
};

/**
 * @brief tca642x_init - uEVM default values for the GPIO expander
 * input reg, output reg, polarity reg, configuration reg
 */
struct tca642x_bank_info tca642x_init[] = {
	{ .input_reg = 0x00,
	  .output_reg = 0x04,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0x80 },
	{ .input_reg = 0x00,
	  .output_reg = 0x00,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0xff },
	{ .input_reg = 0x00,
	  .output_reg = 0x00,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0x40 },
};

/**
 * @brief board_init
 *
 * @return 0
 */
int board_init(void)
{
	gpmc_init();
	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */

	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	return 0;
}

#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
static void enable_host_clocks(void)
{
	int auxclk;
	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
				OPTFCLKEN_HSIC480M_P3_CLK |
				OPTFCLKEN_HSIC60M_P2_CLK |
				OPTFCLKEN_HSIC480M_P2_CLK |
				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);

	/* Enable port 2 and 3 clocks*/
	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);

	/* Enable port 2 and 3 usb host ports tll clocks*/
	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
#ifdef CONFIG_USB_XHCI_OMAP
	/* Enable the USB OTG Super speed clocks */
	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
			(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
#endif

	auxclk = readl((*prcm)->scrm_auxclk1);
	/* Request auxilary clock */
	auxclk |= AUXCLK_ENABLE_MASK;
	writel(auxclk, (*prcm)->scrm_auxclk1);
}
#endif

/**
 * @brief misc_init_r - Configure EVM board specific configurations
 * such as power configurations, ethernet initialization as phase2 of
 * boot sequence
 *
 * @return 0
 */
int misc_init_r(void)
{
	int reg;
	u32 id[4];

#ifdef CONFIG_PALMAS_POWER
	palmas_init_settings();
#endif

	reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;

	id[0] = readl(reg);
	id[1] = readl(reg + 0x8);
	id[2] = readl(reg + 0xC);
	id[3] = readl(reg + 0x10);
	usb_fake_mac_from_die_id(id);

	return 0;
}

void set_muxconf_regs_essential(void)
{
	do_set_mux((*ctrl)->control_padconf_core_base,
		   core_padconf_array_essential,
		   sizeof(core_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));

	do_set_mux((*ctrl)->control_padconf_wkup_base,
		   wkup_padconf_array_essential,
		   sizeof(wkup_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));
}

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
};

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	int ret;

	enable_host_clocks();

	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
	if (ret < 0) {
		puts("Failed to initialize ehci\n");
		return ret;
	}

	return 0;
}

int ehci_hcd_stop(void)
{
	int ret;

	ret = omap_ehci_hcd_stop();
	return ret;
}

void usb_hub_reset_devices(int port)
{
	/* The LAN9730 needs to be reset after the port power has been set. */
	if (port == 3) {
		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
		udelay(10);
		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
	}
}
#endif

#ifdef CONFIG_USB_XHCI_OMAP
/**
 * @brief board_usb_init - Configure EVM board specific configurations
 * for the LDO's and clocks for the USB blocks.
 *
 * @return 0
 */
int board_usb_init(int index, enum usb_init_type init)
{
	int ret;
#ifdef CONFIG_PALMAS_USB_SS_PWR
	ret = palmas_enable_ss_ldo();
#endif

	enable_host_clocks();

	return 0;
}
#endif
Commit	Line	Data
508a58fa S	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments Incorporated, <www.ti.com>
	4	* Aneesh V <aneesh@ti.com>
	5	* Steve Sakoman <steve@sakoman.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	8	*/
508a58fa S	9	#include <common.h>
cb199102	10	#include <palmas.h>
508a58fa S	11	#include <asm/arch/sys_proto.h>
508a58fa S	12	#include <asm/arch/mmc_host_def.h>
fdce7b63	13	#include <tca642x.h>
508a58fa S	14
	15	#include "mux_data.h"
	16
96805532	17	#if defined(CONFIG_USB_EHCI) \|\| defined(CONFIG_USB_XHCI_OMAP)
e9024ef2	18	#include <sata.h>
5e5cfaf9	19	#include <usb.h>
1572eadf	20	#include <asm/gpio.h>
5e5cfaf9 DM	21	#include <asm/arch/clock.h>
	22	#include <asm/arch/ehci.h>
	23	#include <asm/ehci-omap.h>
afdc6321	24	#include <asm/arch/sata.h>
04025b42 DM	25
	26	#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
	27	#define DIE_ID_REG_OFFSET 0x200
	28
5e5cfaf9 DM	29	#endif
5e5cfaf9 DM	30
508a58fa S	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	const struct omap_sysinfo sysinfo = {
5a7bd384	34	"Board: OMAP5432 uEVM\n"
508a58fa S	35	};
508a58fa S	36
fdce7b63 DM	37	/**
	38	* @brief tca642x_init - uEVM default values for the GPIO expander
	39	* input reg, output reg, polarity reg, configuration reg
	40	*/
	41	struct tca642x_bank_info tca642x_init[] = {
	42	{ .input_reg = 0x00,
	43	.output_reg = 0x04,
	44	.polarity_reg = 0x00,
	45	.configuration_reg = 0x80 },
	46	{ .input_reg = 0x00,
	47	.output_reg = 0x00,
	48	.polarity_reg = 0x00,
	49	.configuration_reg = 0xff },
	50	{ .input_reg = 0x00,
	51	.output_reg = 0x00,
	52	.polarity_reg = 0x00,
	53	.configuration_reg = 0x40 },
	54	};
	55
508a58fa S	56	/**
	57	* @brief board_init
	58	*
	59	* @return 0
	60	*/
	61	int board_init(void)
	62	{
	63	gpmc_init();
	64	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
	65	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
	66
fdce7b63 DM	67	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
fdce7b63 DM	68
508a58fa S	69	return 0;
	70	}
	71
	72	int board_eth_init(bd_t *bis)
	73	{
	74	return 0;
	75	}
	76
96805532 DM	77	#if defined(CONFIG_USB_EHCI) \|\| defined(CONFIG_USB_XHCI_OMAP)
	78	static void enable_host_clocks(void)
	79	{
	80	int auxclk;
	81	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK \|
	82	OPTFCLKEN_HSIC480M_P3_CLK \|
	83	OPTFCLKEN_HSIC60M_P2_CLK \|
	84	OPTFCLKEN_HSIC480M_P2_CLK \|
	85	OPTFCLKEN_UTMI_P3_CLK \| OPTFCLKEN_UTMI_P2_CLK);
	86
	87	/* Enable port 2 and 3 clocks*/
	88	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
	89
	90	/* Enable port 2 and 3 usb host ports tll clocks*/
	91	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
	92	(OPTFCLKEN_USB_CH1_CLK_ENABLE \| OPTFCLKEN_USB_CH2_CLK_ENABLE));
	93	#ifdef CONFIG_USB_XHCI_OMAP
	94	/* Enable the USB OTG Super speed clocks */
	95	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
	96	(OPTFCLKEN_REFCLK960M \| OTG_SS_CLKCTRL_MODULEMODE_HW));
	97	#endif
	98
	99	auxclk = readl((*prcm)->scrm_auxclk1);
	100	/* Request auxilary clock */
	101	auxclk \|= AUXCLK_ENABLE_MASK;
	102	writel(auxclk, (*prcm)->scrm_auxclk1);
	103	}
	104	#endif
	105
508a58fa S	106	/**
	107	* @brief misc_init_r - Configure EVM board specific configurations
	108	* such as power configurations, ethernet initialization as phase2 of
	109	* boot sequence
	110	*
	111	* @return 0
	112	*/
	113	int misc_init_r(void)
	114	{
ea02b653	115	int reg;
8a0c6d6f	116	u32 id[4];
ea02b653	117
cb199102	118	#ifdef CONFIG_PALMAS_POWER
12733881	119	palmas_init_settings();
508a58fa	120	#endif
96805532	121
8a0c6d6f NM	122	reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
	123
	124	id[0] = readl(reg);
	125	id[1] = readl(reg + 0x8);
	126	id[2] = readl(reg + 0xC);
	127	id[3] = readl(reg + 0x10);
	128	usb_fake_mac_from_die_id(id);
ea02b653	129
508a58fa S	130	return 0;
	131	}
	132
	133	void set_muxconf_regs_essential(void)
	134	{
9239f5b6 LV	135	do_set_mux((*ctrl)->control_padconf_core_base,
9239f5b6 LV	136	core_padconf_array_essential,
508a58fa S	137	sizeof(core_padconf_array_essential) /
	138	sizeof(struct pad_conf_entry));
	139
9239f5b6 LV	140	do_set_mux((*ctrl)->control_padconf_wkup_base,
9239f5b6 LV	141	wkup_padconf_array_essential,
508a58fa S	142	sizeof(wkup_padconf_array_essential) /
	143	sizeof(struct pad_conf_entry));
	144	}
	145
508a58fa S	146	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	147	int board_mmc_init(bd_t *bis)
	148	{
e3913f56 NK	149	omap_mmc_init(0, 0, 0, -1, -1);
e3913f56 NK	150	omap_mmc_init(1, 0, 0, -1, -1);
508a58fa S	151	return 0;
	152	}
	153	#endif
5e5cfaf9 DM	154
	155	#ifdef CONFIG_USB_EHCI
	156	static struct omap_usbhs_board_data usbhs_bdata = {
	157	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	158	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	159	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
	160	};
	161
127efc4f TK	162	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	163	struct ehci_hccr hccr, struct ehci_hcor hcor)
5e5cfaf9 DM	164	{
5e5cfaf9 DM	165	int ret;
5e5cfaf9 DM	166
	167	enable_host_clocks();
	168
16297cfb	169	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
5e5cfaf9 DM	170	if (ret < 0) {
	171	puts("Failed to initialize ehci\n");
	172	return ret;
	173	}
	174
	175	return 0;
	176	}
	177
	178	int ehci_hcd_stop(void)
	179	{
	180	int ret;
	181
	182	ret = omap_ehci_hcd_stop();
	183	return ret;
	184	}
1572eadf DM	185
	186	void usb_hub_reset_devices(int port)
	187	{
	188	/* The LAN9730 needs to be reset after the port power has been set. */
	189	if (port == 3) {
	190	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
	191	udelay(10);
	192	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
	193	}
	194	}
5e5cfaf9	195	#endif
96805532 DM	196
	197	#ifdef CONFIG_USB_XHCI_OMAP
	198	/**
	199	* @brief board_usb_init - Configure EVM board specific configurations
	200	* for the LDO's and clocks for the USB blocks.
	201	*
	202	* @return 0
	203	*/
7e575c46	204	int board_usb_init(int index, enum usb_init_type init)
96805532 DM	205	{
	206	int ret;
	207	#ifdef CONFIG_PALMAS_USB_SS_PWR
	208	ret = palmas_enable_ss_ldo();
	209	#endif
	210
	211	enable_host_clocks();
	212
	213	return 0;
	214	}
	215	#endif