[people/ms/u-boot.git] / board / ti / omap5_uevm / evm.c

/*
 * (C) Copyright 2010
 * Texas Instruments Incorporated, <www.ti.com>
 * Aneesh V       <aneesh@ti.com>
 * Steve Sakoman  <steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <palmas.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <tca642x.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>

#include "mux_data.h"

#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
#include <sata.h>
#include <usb.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include <asm/arch/sata.h>

#define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
#define DIE_ID_REG_OFFSET	0x200

#endif

DECLARE_GLOBAL_DATA_PTR;

const struct omap_sysinfo sysinfo = {
	"Board: OMAP5432 uEVM\n"
};

/**
 * @brief tca642x_init - uEVM default values for the GPIO expander
 * input reg, output reg, polarity reg, configuration reg
 */
struct tca642x_bank_info tca642x_init[] = {
	{ .input_reg = 0x00,
	  .output_reg = 0x04,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0x80 },
	{ .input_reg = 0x00,
	  .output_reg = 0x00,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0xff },
	{ .input_reg = 0x00,
	  .output_reg = 0x00,
	  .polarity_reg = 0x00,
	  .configuration_reg = 0x40 },
};

#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss = {
	.maximum_speed = USB_SPEED_SUPER,
	.base = OMAP5XX_USB_OTG_SS_BASE,
	.tx_fifo_resize = false,
	.index = 0,
};

static struct dwc3_omap_device usb_otg_ss_glue = {
	.base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.index = 0,
};

static struct ti_usb_phy_device usb_phy_device = {
	.pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
	.usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
	.usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
	.index = 0,
};

int board_usb_init(int index, enum usb_init_type init)
{
	if (index) {
		printf("Invalid Controller Index\n");
		return -EINVAL;
	}

	if (init == USB_INIT_DEVICE) {
		usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	} else {
		usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	}

	enable_usb_clocks(index);
	ti_usb_phy_uboot_init(&usb_phy_device);
	dwc3_omap_uboot_init(&usb_otg_ss_glue);
	dwc3_uboot_init(&usb_otg_ss);

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	if (index) {
		printf("Invalid Controller Index\n");
		return -EINVAL;
	}

	ti_usb_phy_uboot_exit(index);
	dwc3_uboot_exit(index);
	dwc3_omap_uboot_exit(index);
	disable_usb_clocks(index);

	return 0;
}

int usb_gadget_handle_interrupts(int index)
{
	u32 status;

	status = dwc3_omap_uboot_interrupt_status(index);
	if (status)
		dwc3_uboot_handle_interrupt(index);

	return 0;
}
#endif

/**
 * @brief board_init
 *
 * @return 0
 */
int board_init(void)
{
	gpmc_init();
	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */

	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	return 0;
}

#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
static void enable_host_clocks(void)
{
	int auxclk;
	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
				OPTFCLKEN_HSIC480M_P3_CLK |
				OPTFCLKEN_HSIC60M_P2_CLK |
				OPTFCLKEN_HSIC480M_P2_CLK |
				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);

	/* Enable port 2 and 3 clocks*/
	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);

	/* Enable port 2 and 3 usb host ports tll clocks*/
	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
#ifdef CONFIG_USB_XHCI_OMAP
	/* Enable the USB OTG Super speed clocks */
	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
			(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
#endif

	auxclk = readl((*prcm)->scrm_auxclk1);
	/* Request auxilary clock */
	auxclk |= AUXCLK_ENABLE_MASK;
	writel(auxclk, (*prcm)->scrm_auxclk1);
}
#endif

/**
 * @brief misc_init_r - Configure EVM board specific configurations
 * such as power configurations, ethernet initialization as phase2 of
 * boot sequence
 *
 * @return 0
 */
int misc_init_r(void)
{
	unsigned int die_id[4] = { 0 };

#ifdef CONFIG_PALMAS_POWER
	palmas_init_settings();
#endif

	omap_die_id(die_id);
	usb_fake_mac_from_die_id(die_id);

	return 0;
}

void set_muxconf_regs_essential(void)
{
	do_set_mux((*ctrl)->control_padconf_core_base,
		   core_padconf_array_essential,
		   sizeof(core_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));

	do_set_mux((*ctrl)->control_padconf_wkup_base,
		   wkup_padconf_array_essential,
		   sizeof(wkup_padconf_array_essential) /
		   sizeof(struct pad_conf_entry));
}

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
};

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	int ret;

	enable_host_clocks();

	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
	if (ret < 0) {
		puts("Failed to initialize ehci\n");
		return ret;
	}

	return 0;
}

int ehci_hcd_stop(void)
{
	int ret;

	ret = omap_ehci_hcd_stop();
	return ret;
}

void usb_hub_reset_devices(int port)
{
	/* The LAN9730 needs to be reset after the port power has been set. */
	if (port == 3) {
		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
		udelay(10);
		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
	}
}
#endif

#ifdef CONFIG_USB_XHCI_OMAP
/**
 * @brief board_usb_init - Configure EVM board specific configurations
 * for the LDO's and clocks for the USB blocks.
 *
 * @return 0
 */
int board_usb_init(int index, enum usb_init_type init)
{
	int ret;
#ifdef CONFIG_PALMAS_USB_SS_PWR
	ret = palmas_enable_ss_ldo();
#endif

	enable_host_clocks();

	return 0;
}
#endif
Commit	Line	Data
508a58fa S	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments Incorporated, <www.ti.com>
	4	* Aneesh V <aneesh@ti.com>
	5	* Steve Sakoman <steve@sakoman.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	8	*/
508a58fa S	9	#include <common.h>
cb199102	10	#include <palmas.h>
7ba792c0	11	#include <asm/arch/omap.h>
508a58fa S	12	#include <asm/arch/sys_proto.h>
508a58fa S	13	#include <asm/arch/mmc_host_def.h>
fdce7b63	14	#include <tca642x.h>
7ba792c0 KVA	15	#include <usb.h>
	16	#include <linux/usb/gadget.h>
	17	#include <dwc3-uboot.h>
	18	#include <dwc3-omap-uboot.h>
	19	#include <ti-usb-phy-uboot.h>
508a58fa S	20
	21	#include "mux_data.h"
	22
96805532	23	#if defined(CONFIG_USB_EHCI) \|\| defined(CONFIG_USB_XHCI_OMAP)
e9024ef2	24	#include <sata.h>
5e5cfaf9	25	#include <usb.h>
1572eadf	26	#include <asm/gpio.h>
5e5cfaf9 DM	27	#include <asm/arch/clock.h>
	28	#include <asm/arch/ehci.h>
	29	#include <asm/ehci-omap.h>
afdc6321	30	#include <asm/arch/sata.h>
04025b42 DM	31
	32	#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
	33	#define DIE_ID_REG_OFFSET 0x200
	34
5e5cfaf9 DM	35	#endif
5e5cfaf9 DM	36
508a58fa S	37	DECLARE_GLOBAL_DATA_PTR;
	38
	39	const struct omap_sysinfo sysinfo = {
5a7bd384	40	"Board: OMAP5432 uEVM\n"
508a58fa S	41	};
508a58fa S	42
fdce7b63 DM	43	/**
	44	* @brief tca642x_init - uEVM default values for the GPIO expander
	45	* input reg, output reg, polarity reg, configuration reg
	46	*/
	47	struct tca642x_bank_info tca642x_init[] = {
	48	{ .input_reg = 0x00,
	49	.output_reg = 0x04,
	50	.polarity_reg = 0x00,
	51	.configuration_reg = 0x80 },
	52	{ .input_reg = 0x00,
	53	.output_reg = 0x00,
	54	.polarity_reg = 0x00,
	55	.configuration_reg = 0xff },
	56	{ .input_reg = 0x00,
	57	.output_reg = 0x00,
	58	.polarity_reg = 0x00,
	59	.configuration_reg = 0x40 },
	60	};
	61
7ba792c0 KVA	62	#ifdef CONFIG_USB_DWC3
	63	static struct dwc3_device usb_otg_ss = {
	64	.maximum_speed = USB_SPEED_SUPER,
	65	.base = OMAP5XX_USB_OTG_SS_BASE,
	66	.tx_fifo_resize = false,
	67	.index = 0,
	68	};
	69
	70	static struct dwc3_omap_device usb_otg_ss_glue = {
	71	.base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
	72	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	73	.index = 0,
	74	};
	75
	76	static struct ti_usb_phy_device usb_phy_device = {
	77	.pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
	78	.usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
	79	.usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
	80	.index = 0,
	81	};
	82
	83	int board_usb_init(int index, enum usb_init_type init)
	84	{
	85	if (index) {
	86	printf("Invalid Controller Index\n");
	87	return -EINVAL;
	88	}
	89
	90	if (init == USB_INIT_DEVICE) {
	91	usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
	92	usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	93	} else {
	94	usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
	95	usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	96	}
	97
6f1af1e3	98	enable_usb_clocks(index);
7ba792c0 KVA	99	ti_usb_phy_uboot_init(&usb_phy_device);
	100	dwc3_omap_uboot_init(&usb_otg_ss_glue);
	101	dwc3_uboot_init(&usb_otg_ss);
	102
	103	return 0;
	104	}
	105
	106	int board_usb_cleanup(int index, enum usb_init_type init)
	107	{
	108	if (index) {
	109	printf("Invalid Controller Index\n");
	110	return -EINVAL;
	111	}
	112
	113	ti_usb_phy_uboot_exit(index);
	114	dwc3_uboot_exit(index);
	115	dwc3_omap_uboot_exit(index);
6f1af1e3	116	disable_usb_clocks(index);
7ba792c0 KVA	117
	118	return 0;
	119	}
	120
	121	int usb_gadget_handle_interrupts(int index)
	122	{
	123	u32 status;
	124
	125	status = dwc3_omap_uboot_interrupt_status(index);
	126	if (status)
	127	dwc3_uboot_handle_interrupt(index);
	128
	129	return 0;
	130	}
	131	#endif
	132
508a58fa S	133	/**
	134	* @brief board_init
	135	*
	136	* @return 0
	137	*/
	138	int board_init(void)
	139	{
	140	gpmc_init();
	141	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
	142	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
	143
fdce7b63 DM	144	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
fdce7b63 DM	145
508a58fa S	146	return 0;
	147	}
	148
	149	int board_eth_init(bd_t *bis)
	150	{
	151	return 0;
	152	}
	153
96805532 DM	154	#if defined(CONFIG_USB_EHCI) \|\| defined(CONFIG_USB_XHCI_OMAP)
	155	static void enable_host_clocks(void)
	156	{
	157	int auxclk;
	158	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK \|
	159	OPTFCLKEN_HSIC480M_P3_CLK \|
	160	OPTFCLKEN_HSIC60M_P2_CLK \|
	161	OPTFCLKEN_HSIC480M_P2_CLK \|
	162	OPTFCLKEN_UTMI_P3_CLK \| OPTFCLKEN_UTMI_P2_CLK);
	163
	164	/* Enable port 2 and 3 clocks*/
	165	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
	166
	167	/* Enable port 2 and 3 usb host ports tll clocks*/
	168	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
	169	(OPTFCLKEN_USB_CH1_CLK_ENABLE \| OPTFCLKEN_USB_CH2_CLK_ENABLE));
	170	#ifdef CONFIG_USB_XHCI_OMAP
	171	/* Enable the USB OTG Super speed clocks */
	172	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
	173	(OPTFCLKEN_REFCLK960M \| OTG_SS_CLKCTRL_MODULEMODE_HW));
	174	#endif
	175
	176	auxclk = readl((*prcm)->scrm_auxclk1);
	177	/* Request auxilary clock */
	178	auxclk \|= AUXCLK_ENABLE_MASK;
	179	writel(auxclk, (*prcm)->scrm_auxclk1);
	180	}
	181	#endif
	182
508a58fa S	183	/**
	184	* @brief misc_init_r - Configure EVM board specific configurations
	185	* such as power configurations, ethernet initialization as phase2 of
	186	* boot sequence
	187	*
	188	* @return 0
	189	*/
	190	int misc_init_r(void)
	191	{
9fd54016	192	unsigned int die_id[4] = { 0 };
ea02b653	193
cb199102	194	#ifdef CONFIG_PALMAS_POWER
12733881	195	palmas_init_settings();
508a58fa	196	#endif
96805532	197
9fd54016 PK	198	omap_die_id(die_id);
9fd54016 PK	199	usb_fake_mac_from_die_id(die_id);
ea02b653	200
508a58fa S	201	return 0;
	202	}
	203
	204	void set_muxconf_regs_essential(void)
	205	{
9239f5b6 LV	206	do_set_mux((*ctrl)->control_padconf_core_base,
9239f5b6 LV	207	core_padconf_array_essential,
508a58fa S	208	sizeof(core_padconf_array_essential) /
	209	sizeof(struct pad_conf_entry));
	210
9239f5b6 LV	211	do_set_mux((*ctrl)->control_padconf_wkup_base,
9239f5b6 LV	212	wkup_padconf_array_essential,
508a58fa S	213	sizeof(wkup_padconf_array_essential) /
	214	sizeof(struct pad_conf_entry));
	215	}
	216
508a58fa S	217	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	218	int board_mmc_init(bd_t *bis)
	219	{
e3913f56 NK	220	omap_mmc_init(0, 0, 0, -1, -1);
e3913f56 NK	221	omap_mmc_init(1, 0, 0, -1, -1);
508a58fa S	222	return 0;
	223	}
	224	#endif
5e5cfaf9 DM	225
	226	#ifdef CONFIG_USB_EHCI
	227	static struct omap_usbhs_board_data usbhs_bdata = {
	228	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	229	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	230	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
	231	};
	232
127efc4f TK	233	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	234	struct ehci_hccr hccr, struct ehci_hcor hcor)
5e5cfaf9 DM	235	{
5e5cfaf9 DM	236	int ret;
5e5cfaf9 DM	237
	238	enable_host_clocks();
	239
16297cfb	240	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
5e5cfaf9 DM	241	if (ret < 0) {
	242	puts("Failed to initialize ehci\n");
	243	return ret;
	244	}
	245
	246	return 0;
	247	}
	248
	249	int ehci_hcd_stop(void)
	250	{
	251	int ret;
	252
	253	ret = omap_ehci_hcd_stop();
	254	return ret;
	255	}
1572eadf DM	256
	257	void usb_hub_reset_devices(int port)
	258	{
	259	/* The LAN9730 needs to be reset after the port power has been set. */
	260	if (port == 3) {
	261	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
	262	udelay(10);
	263	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
	264	}
	265	}
5e5cfaf9	266	#endif
96805532 DM	267
	268	#ifdef CONFIG_USB_XHCI_OMAP
	269	/**
	270	* @brief board_usb_init - Configure EVM board specific configurations
	271	* for the LDO's and clocks for the USB blocks.
	272	*
	273	* @return 0
	274	*/
7e575c46	275	int board_usb_init(int index, enum usb_init_type init)
96805532 DM	276	{
	277	int ret;
	278	#ifdef CONFIG_PALMAS_USB_SS_PWR
	279	ret = palmas_enable_ss_ldo();
	280	#endif
	281
	282	enable_host_clocks();
	283
	284	return 0;
	285	}
	286	#endif