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508a58fa S |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Texas Instruments Incorporated, <www.ti.com> | |
4 | * Aneesh V <aneesh@ti.com> | |
5 | * Steve Sakoman <steve@sakoman.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
508a58fa S |
8 | */ |
9 | #include <common.h> | |
cb199102 | 10 | #include <palmas.h> |
7ba792c0 | 11 | #include <asm/arch/omap.h> |
508a58fa S |
12 | #include <asm/arch/sys_proto.h> |
13 | #include <asm/arch/mmc_host_def.h> | |
fdce7b63 | 14 | #include <tca642x.h> |
7ba792c0 KVA |
15 | #include <usb.h> |
16 | #include <linux/usb/gadget.h> | |
17 | #include <dwc3-uboot.h> | |
18 | #include <dwc3-omap-uboot.h> | |
19 | #include <ti-usb-phy-uboot.h> | |
508a58fa S |
20 | |
21 | #include "mux_data.h" | |
22 | ||
96805532 | 23 | #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) |
e9024ef2 | 24 | #include <sata.h> |
5e5cfaf9 | 25 | #include <usb.h> |
1572eadf | 26 | #include <asm/gpio.h> |
5e5cfaf9 DM |
27 | #include <asm/arch/clock.h> |
28 | #include <asm/arch/ehci.h> | |
29 | #include <asm/ehci-omap.h> | |
afdc6321 | 30 | #include <asm/arch/sata.h> |
04025b42 DM |
31 | |
32 | #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) | |
33 | #define DIE_ID_REG_OFFSET 0x200 | |
34 | ||
5e5cfaf9 DM |
35 | #endif |
36 | ||
508a58fa S |
37 | DECLARE_GLOBAL_DATA_PTR; |
38 | ||
39 | const struct omap_sysinfo sysinfo = { | |
5a7bd384 | 40 | "Board: OMAP5432 uEVM\n" |
508a58fa S |
41 | }; |
42 | ||
fdce7b63 DM |
43 | /** |
44 | * @brief tca642x_init - uEVM default values for the GPIO expander | |
45 | * input reg, output reg, polarity reg, configuration reg | |
46 | */ | |
47 | struct tca642x_bank_info tca642x_init[] = { | |
48 | { .input_reg = 0x00, | |
49 | .output_reg = 0x04, | |
50 | .polarity_reg = 0x00, | |
51 | .configuration_reg = 0x80 }, | |
52 | { .input_reg = 0x00, | |
53 | .output_reg = 0x00, | |
54 | .polarity_reg = 0x00, | |
55 | .configuration_reg = 0xff }, | |
56 | { .input_reg = 0x00, | |
57 | .output_reg = 0x00, | |
58 | .polarity_reg = 0x00, | |
59 | .configuration_reg = 0x40 }, | |
60 | }; | |
61 | ||
7ba792c0 KVA |
62 | #ifdef CONFIG_USB_DWC3 |
63 | static struct dwc3_device usb_otg_ss = { | |
64 | .maximum_speed = USB_SPEED_SUPER, | |
65 | .base = OMAP5XX_USB_OTG_SS_BASE, | |
66 | .tx_fifo_resize = false, | |
67 | .index = 0, | |
68 | }; | |
69 | ||
70 | static struct dwc3_omap_device usb_otg_ss_glue = { | |
71 | .base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE, | |
72 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, | |
73 | .index = 0, | |
74 | }; | |
75 | ||
76 | static struct ti_usb_phy_device usb_phy_device = { | |
77 | .pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL, | |
78 | .usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER, | |
79 | .usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER, | |
80 | .index = 0, | |
81 | }; | |
82 | ||
83 | int board_usb_init(int index, enum usb_init_type init) | |
84 | { | |
85 | if (index) { | |
86 | printf("Invalid Controller Index\n"); | |
87 | return -EINVAL; | |
88 | } | |
89 | ||
90 | if (init == USB_INIT_DEVICE) { | |
91 | usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL; | |
92 | usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; | |
93 | } else { | |
94 | usb_otg_ss.dr_mode = USB_DR_MODE_HOST; | |
95 | usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; | |
96 | } | |
97 | ||
6f1af1e3 | 98 | enable_usb_clocks(index); |
7ba792c0 KVA |
99 | ti_usb_phy_uboot_init(&usb_phy_device); |
100 | dwc3_omap_uboot_init(&usb_otg_ss_glue); | |
101 | dwc3_uboot_init(&usb_otg_ss); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | int board_usb_cleanup(int index, enum usb_init_type init) | |
107 | { | |
108 | if (index) { | |
109 | printf("Invalid Controller Index\n"); | |
110 | return -EINVAL; | |
111 | } | |
112 | ||
113 | ti_usb_phy_uboot_exit(index); | |
114 | dwc3_uboot_exit(index); | |
115 | dwc3_omap_uboot_exit(index); | |
6f1af1e3 | 116 | disable_usb_clocks(index); |
7ba792c0 KVA |
117 | |
118 | return 0; | |
119 | } | |
120 | ||
121 | int usb_gadget_handle_interrupts(int index) | |
122 | { | |
123 | u32 status; | |
124 | ||
125 | status = dwc3_omap_uboot_interrupt_status(index); | |
126 | if (status) | |
127 | dwc3_uboot_handle_interrupt(index); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | #endif | |
132 | ||
508a58fa S |
133 | /** |
134 | * @brief board_init | |
135 | * | |
136 | * @return 0 | |
137 | */ | |
138 | int board_init(void) | |
139 | { | |
140 | gpmc_init(); | |
141 | gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; | |
142 | gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ | |
143 | ||
fdce7b63 DM |
144 | tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); |
145 | ||
508a58fa S |
146 | return 0; |
147 | } | |
148 | ||
149 | int board_eth_init(bd_t *bis) | |
150 | { | |
151 | return 0; | |
152 | } | |
153 | ||
96805532 DM |
154 | #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) |
155 | static void enable_host_clocks(void) | |
156 | { | |
157 | int auxclk; | |
158 | int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | | |
159 | OPTFCLKEN_HSIC480M_P3_CLK | | |
160 | OPTFCLKEN_HSIC60M_P2_CLK | | |
161 | OPTFCLKEN_HSIC480M_P2_CLK | | |
162 | OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); | |
163 | ||
164 | /* Enable port 2 and 3 clocks*/ | |
165 | setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); | |
166 | ||
167 | /* Enable port 2 and 3 usb host ports tll clocks*/ | |
168 | setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, | |
169 | (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); | |
170 | #ifdef CONFIG_USB_XHCI_OMAP | |
171 | /* Enable the USB OTG Super speed clocks */ | |
172 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, | |
173 | (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW)); | |
174 | #endif | |
175 | ||
176 | auxclk = readl((*prcm)->scrm_auxclk1); | |
177 | /* Request auxilary clock */ | |
178 | auxclk |= AUXCLK_ENABLE_MASK; | |
179 | writel(auxclk, (*prcm)->scrm_auxclk1); | |
180 | } | |
181 | #endif | |
182 | ||
508a58fa S |
183 | /** |
184 | * @brief misc_init_r - Configure EVM board specific configurations | |
185 | * such as power configurations, ethernet initialization as phase2 of | |
186 | * boot sequence | |
187 | * | |
188 | * @return 0 | |
189 | */ | |
190 | int misc_init_r(void) | |
191 | { | |
cb199102 | 192 | #ifdef CONFIG_PALMAS_POWER |
12733881 | 193 | palmas_init_settings(); |
508a58fa | 194 | #endif |
96805532 | 195 | |
07815eb9 | 196 | omap_die_id_usbethaddr(); |
ea02b653 | 197 | |
508a58fa S |
198 | return 0; |
199 | } | |
200 | ||
201 | void set_muxconf_regs_essential(void) | |
202 | { | |
9239f5b6 LV |
203 | do_set_mux((*ctrl)->control_padconf_core_base, |
204 | core_padconf_array_essential, | |
508a58fa S |
205 | sizeof(core_padconf_array_essential) / |
206 | sizeof(struct pad_conf_entry)); | |
207 | ||
9239f5b6 LV |
208 | do_set_mux((*ctrl)->control_padconf_wkup_base, |
209 | wkup_padconf_array_essential, | |
508a58fa S |
210 | sizeof(wkup_padconf_array_essential) / |
211 | sizeof(struct pad_conf_entry)); | |
212 | } | |
213 | ||
508a58fa S |
214 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
215 | int board_mmc_init(bd_t *bis) | |
216 | { | |
e3913f56 NK |
217 | omap_mmc_init(0, 0, 0, -1, -1); |
218 | omap_mmc_init(1, 0, 0, -1, -1); | |
508a58fa S |
219 | return 0; |
220 | } | |
221 | #endif | |
5e5cfaf9 DM |
222 | |
223 | #ifdef CONFIG_USB_EHCI | |
224 | static struct omap_usbhs_board_data usbhs_bdata = { | |
225 | .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, | |
226 | .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, | |
227 | .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, | |
228 | }; | |
229 | ||
127efc4f TK |
230 | int ehci_hcd_init(int index, enum usb_init_type init, |
231 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) | |
5e5cfaf9 DM |
232 | { |
233 | int ret; | |
5e5cfaf9 DM |
234 | |
235 | enable_host_clocks(); | |
236 | ||
16297cfb | 237 | ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); |
5e5cfaf9 DM |
238 | if (ret < 0) { |
239 | puts("Failed to initialize ehci\n"); | |
240 | return ret; | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | int ehci_hcd_stop(void) | |
247 | { | |
248 | int ret; | |
249 | ||
250 | ret = omap_ehci_hcd_stop(); | |
251 | return ret; | |
252 | } | |
1572eadf DM |
253 | |
254 | void usb_hub_reset_devices(int port) | |
255 | { | |
256 | /* The LAN9730 needs to be reset after the port power has been set. */ | |
257 | if (port == 3) { | |
258 | gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); | |
259 | udelay(10); | |
260 | gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); | |
261 | } | |
262 | } | |
5e5cfaf9 | 263 | #endif |
96805532 DM |
264 | |
265 | #ifdef CONFIG_USB_XHCI_OMAP | |
266 | /** | |
267 | * @brief board_usb_init - Configure EVM board specific configurations | |
268 | * for the LDO's and clocks for the USB blocks. | |
269 | * | |
270 | * @return 0 | |
271 | */ | |
7e575c46 | 272 | int board_usb_init(int index, enum usb_init_type init) |
96805532 DM |
273 | { |
274 | int ret; | |
275 | #ifdef CONFIG_PALMAS_USB_SS_PWR | |
276 | ret = palmas_enable_ss_ldo(); | |
277 | #endif | |
278 | ||
279 | enable_host_clocks(); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | #endif |