[people/ms/u-boot.git] / board / ti / omap730p2 / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003-2004
 *
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <Kshitij@ti.com>
 *
 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
 *
 * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
 * (http://www.mpc-data.co.uk)
 *
 * TODO : Tidy up and change to use system register defines
 *        from omap730.h where possible.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP730)
#include <./configs/omap730.h>
#endif

_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */

.globl lowlevel_init
lowlevel_init:
	/* Save callers address in r11 - r11 must never be modified */
	mov r11, lr

	/*------------------------------------------------------*
	 *mask all IRQs by setting all bits in the INTMR default*
	 *------------------------------------------------------*/
	mov	r1,	#0xffffffff
	ldr	r0,	=REG_IHL1_MIR
	str	r1,	[r0]
	ldr	r0,	=REG_IHL2_MIR
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT1)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT1
	ldr	r1,	VAL_ARM_IDLECT1
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT2)		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT2
	ldr	r1,	VAL_ARM_IDLECT2
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT3)		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT3
	ldr	r1,	VAL_ARM_IDLECT3
	str	r1,	[r0]


	mov	r1,	#0x01		/* PER_EN bit */
	ldr	r0,	REG_ARM_RSTCT2
	strh	r1,	[r0]		/* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable	*/
	/* I supposedly need to enable the dsp clock before switching */
	mov	r1,	#0x1000
	ldr	r0,	REG_ARM_SYSST
	strh	r1,	[r0]
	mov	r0,	#0x400
1:
	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
	bne	1b
	ldr	r1,	VAL_ARM_CKCTL
	ldr	r0,	REG_ARM_CKCTL
	strh	r1,	[r0]

	/* a few nops to let settle */
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	/* setup DPLL 1 */
	/* Ramp up the clock to 96Mhz */
	ldr	r1,	VAL_DPLL1_CTL
	ldr	r0,	REG_DPLL1_CTL
	strh	r1,	[r0]
	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
	beq	lock_end	/* Do not look for lock if BYPASS selected */
2:
	ldrh	r1,	[r0]
	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
	beq 2b			/*	loop until bit goes hi. */
lock_end:

	/*------------------------------------------------------*
	 * Turn off the watchdog during init...			*
	 *------------------------------------------------------*/
	ldr	r0,	REG_WATCHDOG
	ldr	r1,	WATCHDOG_VAL1
	str	r1,	[r0]
	ldr	r1,	WATCHDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL1
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG

watch1Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch1Wait

	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG
watch2Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch2Wait

	/* Set memory timings corresponding to the new clock speed */

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	/* Compare physical SDRAM base & current execution location. */
	and     r0, pc, #0xF0000000
	/* Compare. */
	cmp     r0, #0
	/* Skip over EMIF-fast initialization if running from SDRAM. */
	bne	skip_sdram

	/*
	* Delay for SDRAM initialization.
	*/
	mov	r3,	#0x1800		/* value should be checked */
3:
	subs	r3,	r3,	#0x1	/* Decrement count */
	bne	3b

	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

	ldr	r0,	REG_SDRAM_MRS_LEGACY
	ldr	r1,	SDRAM_MRS_VAL
	str	r1,	[r0]

skip_sdram:

common_tc:
	/* slow interface */
	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
	str	r1,	[r0] /* Chip Select 0 */

	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
	str	r1,	[r0] /* Chip Select 1 */
	ldr	r1,	VAL_TC_EMIFS_CS2_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS2_CONFIG
	str	r1,	[r0] /* Chip Select 2 */
	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
	str	r1,	[r0] /* Chip Select 3 */

	/* 48MHz clock request for UART1 */
	ldr	r1,	PERSEUS2_CONFIG_BASE
	ldrh	r0,	[r1, #CONFIG_PCC_CONF]
	orr	r0,	r0, #CONF_MOD_UART1_CLK_MODE_R
	strh	r0,	[r1, #CONFIG_PCC_CONF]

	/* Initialize public and private rheas
	 *  - set access factor 2 on both rhea / strobe
	 *  - disable write buffer on strb0, enable write buffer on strb1
	 */

	ldr	R0,	REG_RHEA_PUB_CTL
	ldr	R1,	REG_RHEA_PRIV_CTL
	ldr	R2,	VAL_RHEA_CTL
	strh	R2,	[R0]
	strh	R2,	[R1]
	mov	R3,	#2          /* disable write buffer on strb0, enable write buffer on strb1 */
	strh	R3,	[R0, #0x08]	/* arm rhea control reg */
	strh	R3,	[R1, #0x08]

	/* enable IRQ and FIQ */

	mrs	r4,	CPSR
	bic	r4,	r4, #IRQ_MASK
	bic	r4,	r4, #FIQ_MASK
	msr	CPSR,	r4

	/* set TAP CONF to TRI EMULATION */

	ldr	r1,	[r0, #CONFIG_MODE2]
	bic	r1,	r1, #0x18
	orr	r1,	r1, #0x10
	str	r1,	[r0, #CONFIG_MODE2]

	/* set tdbgen to 1 */

	ldr	r0,	PERSEUS2_CONFIG_BASE
	ldr	r1,	[r0, #CONFIG_MODE1]
	mov	r2,	#0x10000
	orr	r1,	r1, r2
	str	r1,	[r0, #CONFIG_MODE1]

#ifdef CONFIG_P2_OMAP1610
	/* inserting additional 2 clock cycle hold time for LAN */
	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
	str     r1,     [r0]
#endif
	/* Start MPU Timer 1 */
	ldr	r0,	REG_MPU_LOAD_TIMER
	ldr	r1,	VAL_MPU_LOAD_TIMER
	str	r1,	[r0]

	ldr	r0,	REG_MPU_CNTL_TIMER
	ldr	r1,	VAL_MPU_CNTL_TIMER
	str	r1,	[r0]

	/* back to arch calling code */
	mov	pc,	r11

	/* the literal pools origin */
	.ltorg

REG_TC_EMIFS_CONFIG:		/* 32 bits */
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c

#ifdef CONFIG_P2_OMAP730
REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
	.word 0xfffecc54
#endif

/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00

REG_ARM_IDLECT3:		/* 16 bits */
	.word 0xfffece24
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_IDLECT1:		/* 16 bits */
	.word 0xfffece04

REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00

/* Watch Dog register */
/* secure watchdog stop */
REG_WSPRDOG:
	.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
	.word 0xfffeb034

WSPRDOG_VAL1:
	.word 0x0000aaaa
WSPRDOG_VAL2:
	.word 0x00005555

/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 counter @8192 rows, 10 ns, 8 burst */
REG_SDRAM_CONFIG:
	.word 0xfffecc20

REG_SDRAM_MRS_LEGACY:
	.word 0xfffecc24

REG_WATCHDOG:
	.word 0xfffec808

REG_MPU_LOAD_TIMER:
	.word 0xfffec504
REG_MPU_CNTL_TIMER:
	.word 0xfffec500

/* Public and private rhea bridge registers definition */

REG_RHEA_PUB_CTL:
	.word 0xFFFECA00

REG_RHEA_PRIV_CTL:
	.word 0xFFFED300

/* EMIFF SDRAM Configuration register
   - self refresh disable
   - auto refresh enabled
   - SDRAM type 64 Mb, 16 bits bus 4 banks
   - power down enabled
   - SDRAM clock disabled
 */
SDRAM_CONFIG_VAL:
	.word 0x0C017DF4

/* Burst full page length ; cas latency = 3 */
SDRAM_MRS_VAL:
	.word 0x00000037

VAL_ARM_CKCTL:
	.word 0x6505
VAL_DPLL1_CTL:
	.word 0x3412

#ifdef CONFIG_P2_OMAP730
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x0000FFF3
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x00004278
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x00004278
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x00004278
VAL_TC_EMIFS_CS1_ADVANCED:
	.word 0x00000022
#endif

VAL_ARM_IDLECT1:
	.word 0x00000400
VAL_ARM_IDLECT2:
	.word 0x00000886
VAL_ARM_IDLECT3:
	.word 0x00000015

WATCHDOG_VAL1:
	.word 0x000000f5
WATCHDOG_VAL2:
	.word 0x000000a0

VAL_MPU_LOAD_TIMER:
	.word 0xffffffff
VAL_MPU_CNTL_TIMER:
	.word 0xffffffa1

VAL_RHEA_CTL:
	.word			0xFF22

/* Config Register vals */
PERSEUS2_CONFIG_BASE:
	.word			0xFFFE1000

.equ	CONFIG_PCC_CONF,	0xB4
.equ	CONFIG_MODE1,		0x10
.equ	CONFIG_MODE2,		0x14
.equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A

/* misc values */
.equ	IRQ_MASK,		0x80           /* IRQ mask value */
.equ	FIQ_MASK,		0x40           /* FIQ mask value */
Commit	Line	Data
a56bd922 WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003-2004
	5	*
	6	* Texas Instruments, <www.ti.com>
	7	* Kshitij Gupta <Kshitij@ti.com>
	8	*
	9	* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
	10	*
	11	* Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
	12	* (http://www.mpc-data.co.uk)
	13	*
	14	* TODO : Tidy up and change to use system register defines
	15	* from omap730.h where possible.
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35
	36	#include <config.h>
	37	#include <version.h>
	38
	39	#if defined(CONFIG_OMAP730)
	40	#include <./configs/omap730.h>
	41	#endif
	42
	43	_TEXT_BASE:
14d0a02a	44	.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
a56bd922	45
87cb6862 WD	46	.globl lowlevel_init
87cb6862 WD	47	lowlevel_init:
a56bd922 WD	48	/* Save callers address in r11 - r11 must never be modified */
	49	mov r11, lr
	50
	51	/------------------------------------------------------
	52	mask all IRQs by setting all bits in the INTMR default
	53	------------------------------------------------------/
	54	mov r1, #0xffffffff
	55	ldr r0, =REG_IHL1_MIR
	56	str r1, [r0]
	57	ldr r0, =REG_IHL2_MIR
	58	str r1, [r0]
	59
	60	/------------------------------------------------------
	61	* Set up ARM CLM registers (IDLECT1) *
	62	------------------------------------------------------/
	63	ldr r0, REG_ARM_IDLECT1
	64	ldr r1, VAL_ARM_IDLECT1
	65	str r1, [r0]
	66
	67	/------------------------------------------------------
53677ef1	68	* Set up ARM CLM registers (IDLECT2) *
a56bd922 WD	69	------------------------------------------------------/
	70	ldr r0, REG_ARM_IDLECT2
	71	ldr r1, VAL_ARM_IDLECT2
	72	str r1, [r0]
	73
	74	/------------------------------------------------------
	75	* Set up ARM CLM registers (IDLECT3) *
	76	------------------------------------------------------/
	77	ldr r0, REG_ARM_IDLECT3
	78	ldr r1, VAL_ARM_IDLECT3
	79	str r1, [r0]
	80
	81
	82	mov r1, #0x01 /* PER_EN bit */
	83	ldr r0, REG_ARM_RSTCT2
	84	strh r1, [r0] /* CLKM; Peripheral reset. */
	85
	86	/* Set CLKM to Sync-Scalable */
	87	/* I supposedly need to enable the dsp clock before switching */
	88	mov r1, #0x1000
	89	ldr r0, REG_ARM_SYSST
	90	strh r1, [r0]
	91	mov r0, #0x400
	92	1:
	93	subs r0, r0, #0x1 /* wait for any bubbles to finish */
	94	bne 1b
	95	ldr r1, VAL_ARM_CKCTL
	96	ldr r0, REG_ARM_CKCTL
	97	strh r1, [r0]
	98
	99	/* a few nops to let settle */
	100	nop
	101	nop
	102	nop
	103	nop
	104	nop
	105	nop
	106	nop
	107	nop
	108	nop
	109	nop
	110
	111	/* setup DPLL 1 */
	112	/* Ramp up the clock to 96Mhz */
	113	ldr r1, VAL_DPLL1_CTL
	114	ldr r0, REG_DPLL1_CTL
	115	strh r1, [r0]
	116	ands r1, r1, #0x10 /* Check if PLL is enabled. */
	117	beq lock_end /* Do not look for lock if BYPASS selected */
	118	2:
	119	ldrh r1, [r0]
	120	ands r1, r1, #0x01 /* Check the LOCK bit.*/
	121	beq 2b /* loop until bit goes hi. */
	122	lock_end:
	123
	124	/------------------------------------------------------
	125	* Turn off the watchdog during init... *
53677ef1	126	------------------------------------------------------/
a56bd922 WD	127	ldr r0, REG_WATCHDOG
	128	ldr r1, WATCHDOG_VAL1
	129	str r1, [r0]
	130	ldr r1, WATCHDOG_VAL2
	131	str r1, [r0]
	132	ldr r0, REG_WSPRDOG
	133	ldr r1, WSPRDOG_VAL1
	134	str r1, [r0]
	135	ldr r0, REG_WWPSDOG
	136
	137	watch1Wait:
	138	ldr r1, [r0]
	139	tst r1, #0x10
	140	bne watch1Wait
	141
	142	ldr r0, REG_WSPRDOG
	143	ldr r1, WSPRDOG_VAL2
	144	str r1, [r0]
	145	ldr r0, REG_WWPSDOG
	146	watch2Wait:
	147	ldr r1, [r0]
	148	tst r1, #0x10
	149	bne watch2Wait
	150
	151	/* Set memory timings corresponding to the new clock speed */
	152
	153	/* Check execution location to determine current execution location
	154	* and branch to appropriate initialization code.
	155	*/
	156	/* Compare physical SDRAM base & current execution location. */
	157	and r0, pc, #0xF0000000
	158	/* Compare. */
	159	cmp r0, #0
	160	/* Skip over EMIF-fast initialization if running from SDRAM. */
53677ef1	161	bne skip_sdram
a56bd922 WD	162
	163	/*
	164	* Delay for SDRAM initialization.
	165	*/
	166	mov r3, #0x1800 /* value should be checked */
	167	3:
	168	subs r3, r3, #0x1 /* Decrement count */
53677ef1	169	bne 3b
a56bd922 WD	170
	171	ldr r0, REG_SDRAM_CONFIG
	172	ldr r1, SDRAM_CONFIG_VAL
	173	str r1, [r0]
	174
	175	ldr r0, REG_SDRAM_MRS_LEGACY
	176	ldr r1, SDRAM_MRS_VAL
	177	str r1, [r0]
	178
	179	skip_sdram:
	180
	181	common_tc:
	182	/* slow interface */
	183	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
	184	ldr r0, REG_TC_EMIFS_CS0_CONFIG
	185	str r1, [r0] /* Chip Select 0 */
	186
	187	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
	188	ldr r0, REG_TC_EMIFS_CS1_CONFIG
	189	str r1, [r0] /* Chip Select 1 */
	190	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
	191	ldr r0, REG_TC_EMIFS_CS2_CONFIG
	192	str r1, [r0] /* Chip Select 2 */
	193	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
	194	ldr r0, REG_TC_EMIFS_CS3_CONFIG
	195	str r1, [r0] /* Chip Select 3 */
	196
	197	/* 48MHz clock request for UART1 */
	198	ldr r1, PERSEUS2_CONFIG_BASE
	199	ldrh r0, [r1, #CONFIG_PCC_CONF]
	200	orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
	201	strh r0, [r1, #CONFIG_PCC_CONF]
	202
	203	/* Initialize public and private rheas
	204	* - set access factor 2 on both rhea / strobe
	205	* - disable write buffer on strb0, enable write buffer on strb1
	206	*/
	207
	208	ldr R0, REG_RHEA_PUB_CTL
	209	ldr R1, REG_RHEA_PRIV_CTL
	210	ldr R2, VAL_RHEA_CTL
	211	strh R2, [R0]
	212	strh R2, [R1]
	213	mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
	214	strh R3, [R0, #0x08] /* arm rhea control reg */
	215	strh R3, [R1, #0x08]
	216
	217	/* enable IRQ and FIQ */
	218
	219	mrs r4, CPSR
	220	bic r4, r4, #IRQ_MASK
	221	bic r4, r4, #FIQ_MASK
	222	msr CPSR, r4
	223
	224	/* set TAP CONF to TRI EMULATION */
	225
	226	ldr r1, [r0, #CONFIG_MODE2]
	227	bic r1, r1, #0x18
	228	orr r1, r1, #0x10
	229	str r1, [r0, #CONFIG_MODE2]
	230
	231	/* set tdbgen to 1 */
	232
	233	ldr r0, PERSEUS2_CONFIG_BASE
234	ldr r1, [r0, #CONFIG_MODE1]
235	mov r2, #0x10000
236	orr r1, r1, r2
237	str r1, [r0, #CONFIG_MODE1]
238
239	#ifdef CONFIG_P2_OMAP1610
240	/* inserting additional 2 clock cycle hold time for LAN */
241	ldr r0, REG_TC_EMIFS_CS1_ADVANCED
53677ef1	242	ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
a56bd922 WD	243	str r1, [r0]
	244	#endif
	245	/* Start MPU Timer 1 */
	246	ldr r0, REG_MPU_LOAD_TIMER
	247	ldr r1, VAL_MPU_LOAD_TIMER
	248	str r1, [r0]
	249
	250	ldr r0, REG_MPU_CNTL_TIMER
	251	ldr r1, VAL_MPU_CNTL_TIMER
	252	str r1, [r0]
	253
	254	/* back to arch calling code */
	255	mov pc, r11
	256
	257	/* the literal pools origin */
	258	.ltorg
	259
	260	REG_TC_EMIFS_CONFIG: /* 32 bits */
	261	.word 0xfffecc0c
	262	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
	263	.word 0xfffecc10
	264	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
	265	.word 0xfffecc14
	266	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
	267	.word 0xfffecc18
	268	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
	269	.word 0xfffecc1c
	270
	271	#ifdef CONFIG_P2_OMAP730
	272	REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
	273	.word 0xfffecc54
	274	#endif
	275
	276	/* MPU clock/reset/power mode control registers */
	277	REG_ARM_CKCTL: /* 16 bits */
	278	.word 0xfffece00
	279
	280	REG_ARM_IDLECT3: /* 16 bits */
	281	.word 0xfffece24
	282	REG_ARM_IDLECT2: /* 16 bits */
	283	.word 0xfffece08
	284	REG_ARM_IDLECT1: /* 16 bits */
	285	.word 0xfffece04
	286
	287	REG_ARM_RSTCT2: /* 16 bits */
	288	.word 0xfffece14
	289	REG_ARM_SYSST: /* 16 bits */
	290	.word 0xfffece18
	291	/* DPLL control registers */
	292	REG_DPLL1_CTL: /* 16 bits */
	293	.word 0xfffecf00
	294
	295	/* Watch Dog register */
	296	/* secure watchdog stop */
	297	REG_WSPRDOG:
	298	.word 0xfffeb048
	299	/* watchdog write pending */
	300	REG_WWPSDOG:
	301	.word 0xfffeb034
	302
	303	WSPRDOG_VAL1:
	304	.word 0x0000aaaa
	305	WSPRDOG_VAL2:
	306	.word 0x00005555
307
308	/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
309	counter @8192 rows, 10 ns, 8 burst */
310	REG_SDRAM_CONFIG:
311	.word 0xfffecc20
312
313	REG_SDRAM_MRS_LEGACY:
314	.word 0xfffecc24
315
316	REG_WATCHDOG:
317	.word 0xfffec808
318
319	REG_MPU_LOAD_TIMER:
77f63342	320	.word 0xfffec504
a56bd922 WD	321	REG_MPU_CNTL_TIMER:
	322	.word 0xfffec500
	323
	324	/* Public and private rhea bridge registers definition */
	325
	326	REG_RHEA_PUB_CTL:
	327	.word 0xFFFECA00
	328
	329	REG_RHEA_PRIV_CTL:
	330	.word 0xFFFED300
	331
	332	/* EMIFF SDRAM Configuration register
	333	- self refresh disable
	334	- auto refresh enabled
	335	- SDRAM type 64 Mb, 16 bits bus 4 banks
	336	- power down enabled
	337	- SDRAM clock disabled
	338	*/
	339	SDRAM_CONFIG_VAL:
	340	.word 0x0C017DF4
	341
	342	/* Burst full page length ; cas latency = 3 */
	343	SDRAM_MRS_VAL:
	344	.word 0x00000037
	345
	346	VAL_ARM_CKCTL:
	347	.word 0x6505
	348	VAL_DPLL1_CTL:
	349	.word 0x3412
	350
	351	#ifdef CONFIG_P2_OMAP730
	352	VAL_TC_EMIFS_CS0_CONFIG:
	353	.word 0x0000FFF3
	354	VAL_TC_EMIFS_CS1_CONFIG:
	355	.word 0x00004278
	356	VAL_TC_EMIFS_CS2_CONFIG:
	357	.word 0x00004278
	358	VAL_TC_EMIFS_CS3_CONFIG:
	359	.word 0x00004278
	360	VAL_TC_EMIFS_CS1_ADVANCED:
	361	.word 0x00000022
	362	#endif
	363
	364	VAL_ARM_IDLECT1:
	365	.word 0x00000400
	366	VAL_ARM_IDLECT2:
	367	.word 0x00000886
	368	VAL_ARM_IDLECT3:
	369	.word 0x00000015
	370
	371	WATCHDOG_VAL1:
	372	.word 0x000000f5
	373	WATCHDOG_VAL2:
	374	.word 0x000000a0
	375
	376	VAL_MPU_LOAD_TIMER:
	377	.word 0xffffffff
	378	VAL_MPU_CNTL_TIMER:
	379	.word 0xffffffa1
	380
	381	VAL_RHEA_CTL:
	382	.word 0xFF22
	383
	384	/* Config Register vals */
385	PERSEUS2_CONFIG_BASE:
386	.word 0xFFFE1000
387
388	.equ CONFIG_PCC_CONF, 0xB4
389	.equ CONFIG_MODE1, 0x10
390	.equ CONFIG_MODE2, 0x14
391	.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A
392
393	/* misc values */
1eaeb58e WD	394	.equ IRQ_MASK, 0x80 /* IRQ mask value */
1eaeb58e WD	395	.equ FIQ_MASK, 0x40 /* FIQ mask value */