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1 | /* |
2 | * (C) Copyright 2004-2009 | |
3 | * Texas Instruments Incorporated, <www.ti.com> | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #include <common.h> | |
a1725999 | 25 | #include <netdev.h> |
e63e5904 TR |
26 | #include <twl4030.h> |
27 | #include <asm/io.h> | |
28 | #include <asm/arch/mux.h> | |
29 | #include <asm/arch/mem.h> | |
30 | #include <asm/arch/sys_proto.h> | |
31 | #include <asm/mach-types.h> | |
32 | #include "sdp.h" | |
33 | ||
34 | const omap3_sysinfo sysinfo = { | |
35 | DDR_DISCRETE, | |
36 | "OMAP3 SDP3430 board", | |
37 | #if defined(CONFIG_ENV_IS_IN_ONENAND) | |
38 | "OneNAND", | |
39 | #elif defined(CONFIG_ENV_IS_IN_NAND) | |
40 | "NAND", | |
41 | #else | |
42 | "NOR", | |
43 | #endif | |
44 | }; | |
45 | ||
46 | /* Timing definitions for GPMC controller for Sibley NOR */ | |
47 | static const u32 gpmc_sdp_nor[] = { | |
48 | SDP3430_NOR_GPMC_CONF1, | |
49 | SDP3430_NOR_GPMC_CONF2, | |
50 | SDP3430_NOR_GPMC_CONF3, | |
51 | SDP3430_NOR_GPMC_CONF4, | |
52 | SDP3430_NOR_GPMC_CONF5, | |
53 | SDP3430_NOR_GPMC_CONF6, | |
54 | /*CONF7- computed as params */ | |
55 | }; | |
56 | ||
57 | /* | |
58 | * Timing definitions for GPMC controller for Debug Board | |
59 | * Debug board contains access to ethernet and DIP Switch setting | |
60 | * information etc. | |
61 | */ | |
62 | static const u32 gpmc_sdp_debug[] = { | |
63 | SDP3430_DEBUG_GPMC_CONF1, | |
64 | SDP3430_DEBUG_GPMC_CONF2, | |
65 | SDP3430_DEBUG_GPMC_CONF3, | |
66 | SDP3430_DEBUG_GPMC_CONF4, | |
67 | SDP3430_DEBUG_GPMC_CONF5, | |
68 | SDP3430_DEBUG_GPMC_CONF6, | |
69 | /*CONF7- computed as params */ | |
70 | }; | |
71 | ||
72 | /* Timing defintions for GPMC OneNAND */ | |
73 | static const u32 gpmc_sdp_onenand[] = { | |
74 | SDP3430_ONENAND_GPMC_CONF1, | |
75 | SDP3430_ONENAND_GPMC_CONF2, | |
76 | SDP3430_ONENAND_GPMC_CONF3, | |
77 | SDP3430_ONENAND_GPMC_CONF4, | |
78 | SDP3430_ONENAND_GPMC_CONF5, | |
79 | SDP3430_ONENAND_GPMC_CONF6, | |
80 | /*CONF7- computed as params */ | |
81 | }; | |
82 | ||
83 | /* GPMC definitions for GPMC NAND */ | |
84 | static const u32 gpmc_sdp_nand[] = { | |
85 | SDP3430_NAND_GPMC_CONF1, | |
86 | SDP3430_NAND_GPMC_CONF2, | |
87 | SDP3430_NAND_GPMC_CONF3, | |
88 | SDP3430_NAND_GPMC_CONF4, | |
89 | SDP3430_NAND_GPMC_CONF5, | |
90 | SDP3430_NAND_GPMC_CONF6, | |
91 | /*CONF7- computed as params */ | |
92 | }; | |
93 | ||
94 | /* gpmc_cfg is initialized by gpmc_init and we use it here */ | |
95 | extern struct gpmc *gpmc_cfg; | |
96 | ||
97 | /** | |
98 | * @brief board_init - gpmc and basic setup as phase1 of boot sequence | |
99 | * | |
100 | * @return 0 | |
101 | */ | |
102 | int board_init(void) | |
103 | { | |
104 | DECLARE_GLOBAL_DATA_PTR; | |
105 | ||
106 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ | |
107 | /* TODO: Dynamically pop out CS mapping and program accordingly */ | |
108 | /* Configure devices for default ON ON ON settings */ | |
109 | enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0], | |
110 | CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M); | |
111 | enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000, | |
112 | GPMC_SIZE_16M); | |
113 | enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000, | |
114 | GPMC_SIZE_16M); | |
115 | enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE, | |
116 | GPMC_SIZE_16M); | |
117 | /* board id for Linux */ | |
118 | gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; | |
119 | /* boot param addr */ | |
120 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | #define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c) | |
126 | #define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b) | |
127 | ||
128 | /** | |
a1725999 | 129 | * @brief board_eth_init Take the Ethernet controller out of reset and wait |
e63e5904 TR |
130 | * for the EEPROM load to complete. |
131 | */ | |
a1725999 | 132 | int board_eth_init(bd_t *bis) |
e63e5904 | 133 | { |
a1725999 NM |
134 | int rc = 0; |
135 | #ifdef CONFIG_LAN91C96 | |
e63e5904 TR |
136 | int cnt = 20; |
137 | ||
138 | writew(0x0, LAN_RESET_REGISTER); | |
139 | do { | |
140 | writew(0x1, LAN_RESET_REGISTER); | |
141 | udelay(100); | |
142 | if (cnt == 0) | |
143 | goto reset_err_out; | |
144 | --cnt; | |
145 | } while (readw(LAN_RESET_REGISTER) != 0x1); | |
146 | ||
147 | cnt = 20; | |
148 | ||
149 | do { | |
150 | writew(0x0, LAN_RESET_REGISTER); | |
151 | udelay(100); | |
152 | if (cnt == 0) | |
153 | goto reset_err_out; | |
154 | --cnt; | |
155 | } while (readw(LAN_RESET_REGISTER) != 0x0000); | |
156 | udelay(1000); | |
157 | ||
158 | writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG); | |
159 | udelay(1000); | |
a1725999 | 160 | rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
e63e5904 | 161 | reset_err_out: |
e63e5904 TR |
162 | |
163 | #endif | |
a1725999 | 164 | return rc; |
e63e5904 TR |
165 | } |
166 | ||
167 | /** | |
168 | * @brief misc_init_r - Configure SDP board specific configurations | |
169 | * such as power configurations, ethernet initialization as phase2 of | |
170 | * boot sequence | |
171 | * | |
172 | * @return 0 | |
173 | */ | |
174 | int misc_init_r(void) | |
175 | { | |
176 | /* Partial setup: | |
177 | * VAUX3 - 2.8V for DVI | |
178 | * VPLL1 - 1.8V | |
179 | * VDAC - 1.8V | |
180 | * and turns on LEDA/LEDB (not needed ... NOP?) | |
181 | */ | |
182 | twl4030_power_init(); | |
183 | ||
184 | /* FIXME finish setup: | |
185 | * VAUX1 - 2.8V for mainboard I/O | |
186 | * VAUX2 - 2.8V for camera | |
187 | * VAUX4 - 1.8V for OMAP3 CSI | |
188 | * VMMC1 - 3.15V (init, variable) for MMC1 | |
189 | * VMMC2 - 1.85V for MMC2 | |
190 | * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM | |
191 | * VPLL2 - 1.8V | |
192 | */ | |
e63e5904 TR |
193 | |
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * @brief set_muxconf_regs Setting up the configuration Mux registers | |
199 | * specific to the hardware. Many pins need to be moved from protect | |
200 | * to primary mode. | |
201 | */ | |
202 | void set_muxconf_regs(void) | |
203 | { | |
204 | /* platform specific muxes */ | |
205 | MUX_SDP3430(); | |
206 | } |