]>
Commit | Line | Data |
---|---|---|
c35d7cf0 FK |
1 | /* |
2 | * (C) Copyright 2004-2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Author : | |
6 | * Sunil Kumar <sunilsaini05@gmail.com> | |
7 | * Shashi Ranjan <shashiranjanmca05@gmail.com> | |
8 | * | |
9 | * (C) Copyright 2009 | |
10 | * Frederik Kriewitz <frederik@kriewitz.eu> | |
11 | * | |
12 | * Derived from Beagle Board and 3430 SDP code by | |
13 | * Richard Woodruff <r-woodruff2@ti.com> | |
14 | * Syed Mohammed Khasim <khasim@ti.com> | |
15 | * | |
16 | * | |
1a459660 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
c35d7cf0 FK |
18 | */ |
19 | #include <common.h> | |
a91ef4ad AB |
20 | #include <dm.h> |
21 | #include <ns16550.h> | |
c35d7cf0 FK |
22 | #include <twl4030.h> |
23 | #include <asm/io.h> | |
f408501d | 24 | #include <asm/arch/mmc_host_def.h> |
c35d7cf0 FK |
25 | #include <asm/arch/mux.h> |
26 | #include <asm/arch/sys_proto.h> | |
27 | #include <asm/arch/mem.h> | |
28 | #include <asm/mach-types.h> | |
29 | #include "devkit8000.h" | |
2d52a9a3 | 30 | #include <asm/gpio.h> |
c35d7cf0 FK |
31 | #ifdef CONFIG_DRIVER_DM9000 |
32 | #include <net.h> | |
33 | #include <netdev.h> | |
34 | #endif | |
35 | ||
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
13b178ed TW |
38 | static u32 gpmc_net_config[GPMC_MAX_REG] = { |
39 | NET_GPMC_CONFIG1, | |
40 | NET_GPMC_CONFIG2, | |
41 | NET_GPMC_CONFIG3, | |
42 | NET_GPMC_CONFIG4, | |
43 | NET_GPMC_CONFIG5, | |
44 | NET_GPMC_CONFIG6, | |
45 | 0 | |
46 | }; | |
47 | ||
a91ef4ad | 48 | static const struct ns16550_platdata devkit8000_serial = { |
2f6ed3b8 AF |
49 | .base = OMAP34XX_UART3, |
50 | .reg_shift = 2, | |
17fa0326 HS |
51 | .clock = V_NS16550_CLK, |
52 | .fcr = UART_FCR_DEFVAL, | |
a91ef4ad AB |
53 | }; |
54 | ||
55 | U_BOOT_DEVICE(devkit8000_uart) = { | |
c7b9686d | 56 | "ns16550_serial", |
a91ef4ad AB |
57 | &devkit8000_serial |
58 | }; | |
59 | ||
c35d7cf0 FK |
60 | /* |
61 | * Routine: board_init | |
62 | * Description: Early hardware init. | |
63 | */ | |
64 | int board_init(void) | |
65 | { | |
66 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ | |
67 | /* board id for Linux */ | |
68 | gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000; | |
69 | /* boot param addr */ | |
70 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
9e70c08b SS |
75 | /* Configure GPMC registers for DM9000 */ |
76 | static void gpmc_dm9000_config(void) | |
77 | { | |
78 | enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], | |
79 | CONFIG_DM9000_BASE, GPMC_SIZE_16M); | |
80 | } | |
81 | ||
c35d7cf0 FK |
82 | /* |
83 | * Routine: misc_init_r | |
84 | * Description: Configure board specific parts | |
85 | */ | |
86 | int misc_init_r(void) | |
87 | { | |
88 | struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; | |
89 | #ifdef CONFIG_DRIVER_DM9000 | |
90 | uchar enetaddr[6]; | |
91 | u32 die_id_0; | |
92 | #endif | |
93 | ||
94 | twl4030_power_init(); | |
95 | #ifdef CONFIG_TWL4030_LED | |
ead39d7a | 96 | twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); |
c35d7cf0 FK |
97 | #endif |
98 | ||
99 | #ifdef CONFIG_DRIVER_DM9000 | |
100 | /* Configure GPMC registers for DM9000 */ | |
13b178ed TW |
101 | enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], |
102 | CONFIG_DM9000_BASE, GPMC_SIZE_16M); | |
c35d7cf0 FK |
103 | |
104 | /* Use OMAP DIE_ID as MAC address */ | |
35affd7a | 105 | if (!eth_env_get_enetaddr("ethaddr", enetaddr)) { |
c35d7cf0 FK |
106 | printf("ethaddr not set, using Die ID\n"); |
107 | die_id_0 = readl(&id_base->die_id_0); | |
108 | enetaddr[0] = 0x02; /* locally administered */ | |
109 | enetaddr[1] = readl(&id_base->die_id_1) & 0xff; | |
110 | enetaddr[2] = (die_id_0 & 0xff000000) >> 24; | |
111 | enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16; | |
112 | enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8; | |
113 | enetaddr[5] = (die_id_0 & 0x000000ff); | |
fd1e959e | 114 | eth_env_set_enetaddr("ethaddr", enetaddr); |
c35d7cf0 FK |
115 | } |
116 | #endif | |
117 | ||
679f82c3 | 118 | omap_die_id_display(); |
c35d7cf0 FK |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
123 | /* | |
124 | * Routine: set_muxconf_regs | |
125 | * Description: Setting up the configuration Mux registers specific to the | |
126 | * hardware. Many pins need to be moved from protect to primary | |
127 | * mode. | |
128 | */ | |
129 | void set_muxconf_regs(void) | |
130 | { | |
131 | MUX_DEVKIT8000(); | |
132 | } | |
133 | ||
4aa2ba3a | 134 | #if defined(CONFIG_MMC) |
f408501d TR |
135 | int board_mmc_init(bd_t *bis) |
136 | { | |
e3913f56 | 137 | return omap_mmc_init(0, 0, 0, -1, -1); |
f408501d TR |
138 | } |
139 | #endif | |
140 | ||
4aa2ba3a | 141 | #if defined(CONFIG_MMC) |
aac5450e PK |
142 | void board_mmc_power_init(void) |
143 | { | |
144 | twl4030_power_mmc_init(0); | |
145 | } | |
146 | #endif | |
147 | ||
3f6a4922 | 148 | #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) |
c35d7cf0 FK |
149 | /* |
150 | * Routine: board_eth_init | |
151 | * Description: Setting up the Ethernet hardware. | |
152 | */ | |
153 | int board_eth_init(bd_t *bis) | |
154 | { | |
155 | return dm9000_initialize(bis); | |
156 | } | |
157 | #endif | |
9ae0d550 | 158 | |
9e70c08b SS |
159 | #ifdef CONFIG_SPL_OS_BOOT |
160 | /* | |
fc0b5948 | 161 | * Do board specific preparation before SPL |
9e70c08b SS |
162 | * Linux boot |
163 | */ | |
164 | void spl_board_prepare_for_linux(void) | |
165 | { | |
166 | gpmc_dm9000_config(); | |
167 | } | |
168 | ||
2d52a9a3 SS |
169 | /* |
170 | * devkit8000 specific implementation of spl_start_uboot() | |
171 | * | |
172 | * RETURN | |
173 | * 0 if the button is not pressed | |
174 | * 1 if the button is pressed | |
175 | */ | |
176 | int spl_start_uboot(void) | |
177 | { | |
178 | int val = 0; | |
30372965 SB |
179 | if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) { |
180 | gpio_direction_input(SPL_OS_BOOT_KEY); | |
181 | val = gpio_get_value(SPL_OS_BOOT_KEY); | |
182 | gpio_free(SPL_OS_BOOT_KEY); | |
2d52a9a3 SS |
183 | } |
184 | return !val; | |
185 | } | |
9e70c08b SS |
186 | #endif |
187 | ||
9ae0d550 TR |
188 | /* |
189 | * Routine: get_board_mem_timings | |
190 | * Description: If we use SPL then there is no x-loader nor config header | |
191 | * so we have to setup the DDR timings ourself on the first bank. This | |
192 | * provides the timing values back to the function that configures | |
193 | * the memory. We have either one or two banks of 128MB DDR. | |
194 | */ | |
8c4445d2 | 195 | void get_board_mem_timings(struct board_sdrc_timings *timings) |
9ae0d550 TR |
196 | { |
197 | /* General SDRC config */ | |
8c4445d2 PB |
198 | timings->mcfg = MICRON_V_MCFG_165(128 << 20); |
199 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; | |
9ae0d550 TR |
200 | |
201 | /* AC timings */ | |
8c4445d2 PB |
202 | timings->ctrla = MICRON_V_ACTIMA_165; |
203 | timings->ctrlb = MICRON_V_ACTIMB_165; | |
9ae0d550 | 204 | |
8c4445d2 | 205 | timings->mr = MICRON_V_MR_165; |
9ae0d550 | 206 | } |