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c35d7cf0 FK |
1 | /* |
2 | * (C) Copyright 2004-2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Author : | |
6 | * Sunil Kumar <sunilsaini05@gmail.com> | |
7 | * Shashi Ranjan <shashiranjanmca05@gmail.com> | |
8 | * | |
9 | * (C) Copyright 2009 | |
10 | * Frederik Kriewitz <frederik@kriewitz.eu> | |
11 | * | |
12 | * Derived from Beagle Board and 3430 SDP code by | |
13 | * Richard Woodruff <r-woodruff2@ti.com> | |
14 | * Syed Mohammed Khasim <khasim@ti.com> | |
15 | * | |
16 | * | |
17 | * See file CREDITS for list of people who contributed to this | |
18 | * project. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License as | |
22 | * published by the Free Software Foundation; either version 2 of | |
23 | * the License, or (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
33 | * MA 02111-1307 USA | |
34 | */ | |
35 | #include <common.h> | |
36 | #include <twl4030.h> | |
37 | #include <asm/io.h> | |
f408501d | 38 | #include <asm/arch/mmc_host_def.h> |
c35d7cf0 FK |
39 | #include <asm/arch/mux.h> |
40 | #include <asm/arch/sys_proto.h> | |
41 | #include <asm/arch/mem.h> | |
42 | #include <asm/mach-types.h> | |
43 | #include "devkit8000.h" | |
44 | #ifdef CONFIG_DRIVER_DM9000 | |
45 | #include <net.h> | |
46 | #include <netdev.h> | |
47 | #endif | |
48 | ||
49 | DECLARE_GLOBAL_DATA_PTR; | |
50 | ||
13b178ed TW |
51 | static u32 gpmc_net_config[GPMC_MAX_REG] = { |
52 | NET_GPMC_CONFIG1, | |
53 | NET_GPMC_CONFIG2, | |
54 | NET_GPMC_CONFIG3, | |
55 | NET_GPMC_CONFIG4, | |
56 | NET_GPMC_CONFIG5, | |
57 | NET_GPMC_CONFIG6, | |
58 | 0 | |
59 | }; | |
60 | ||
c35d7cf0 FK |
61 | /* |
62 | * Routine: board_init | |
63 | * Description: Early hardware init. | |
64 | */ | |
65 | int board_init(void) | |
66 | { | |
67 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ | |
68 | /* board id for Linux */ | |
69 | gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000; | |
70 | /* boot param addr */ | |
71 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
9e70c08b SS |
76 | /* Configure GPMC registers for DM9000 */ |
77 | static void gpmc_dm9000_config(void) | |
78 | { | |
79 | enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], | |
80 | CONFIG_DM9000_BASE, GPMC_SIZE_16M); | |
81 | } | |
82 | ||
c35d7cf0 FK |
83 | /* |
84 | * Routine: misc_init_r | |
85 | * Description: Configure board specific parts | |
86 | */ | |
87 | int misc_init_r(void) | |
88 | { | |
89 | struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; | |
90 | #ifdef CONFIG_DRIVER_DM9000 | |
91 | uchar enetaddr[6]; | |
92 | u32 die_id_0; | |
93 | #endif | |
94 | ||
95 | twl4030_power_init(); | |
96 | #ifdef CONFIG_TWL4030_LED | |
ead39d7a | 97 | twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); |
c35d7cf0 FK |
98 | #endif |
99 | ||
100 | #ifdef CONFIG_DRIVER_DM9000 | |
101 | /* Configure GPMC registers for DM9000 */ | |
13b178ed TW |
102 | enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], |
103 | CONFIG_DM9000_BASE, GPMC_SIZE_16M); | |
c35d7cf0 FK |
104 | |
105 | /* Use OMAP DIE_ID as MAC address */ | |
106 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { | |
107 | printf("ethaddr not set, using Die ID\n"); | |
108 | die_id_0 = readl(&id_base->die_id_0); | |
109 | enetaddr[0] = 0x02; /* locally administered */ | |
110 | enetaddr[1] = readl(&id_base->die_id_1) & 0xff; | |
111 | enetaddr[2] = (die_id_0 & 0xff000000) >> 24; | |
112 | enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16; | |
113 | enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8; | |
114 | enetaddr[5] = (die_id_0 & 0x000000ff); | |
115 | eth_setenv_enetaddr("ethaddr", enetaddr); | |
116 | } | |
117 | #endif | |
118 | ||
119 | dieid_num_r(); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
124 | /* | |
125 | * Routine: set_muxconf_regs | |
126 | * Description: Setting up the configuration Mux registers specific to the | |
127 | * hardware. Many pins need to be moved from protect to primary | |
128 | * mode. | |
129 | */ | |
130 | void set_muxconf_regs(void) | |
131 | { | |
132 | MUX_DEVKIT8000(); | |
133 | } | |
134 | ||
c9f3cf14 | 135 | #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) |
f408501d TR |
136 | int board_mmc_init(bd_t *bis) |
137 | { | |
138 | omap_mmc_init(0); | |
139 | return 0; | |
140 | } | |
141 | #endif | |
142 | ||
3f6a4922 | 143 | #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) |
c35d7cf0 FK |
144 | /* |
145 | * Routine: board_eth_init | |
146 | * Description: Setting up the Ethernet hardware. | |
147 | */ | |
148 | int board_eth_init(bd_t *bis) | |
149 | { | |
150 | return dm9000_initialize(bis); | |
151 | } | |
152 | #endif | |
9ae0d550 | 153 | |
9e70c08b SS |
154 | #ifdef CONFIG_SPL_OS_BOOT |
155 | /* | |
156 | * Do board specific preperation before SPL | |
157 | * Linux boot | |
158 | */ | |
159 | void spl_board_prepare_for_linux(void) | |
160 | { | |
161 | gpmc_dm9000_config(); | |
162 | } | |
163 | ||
164 | #endif | |
165 | ||
9ae0d550 TR |
166 | /* |
167 | * Routine: get_board_mem_timings | |
168 | * Description: If we use SPL then there is no x-loader nor config header | |
169 | * so we have to setup the DDR timings ourself on the first bank. This | |
170 | * provides the timing values back to the function that configures | |
171 | * the memory. We have either one or two banks of 128MB DDR. | |
172 | */ | |
173 | void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, | |
174 | u32 *mr) | |
175 | { | |
176 | /* General SDRC config */ | |
177 | *mcfg = MICRON_V_MCFG_165(128 << 20); | |
178 | *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; | |
179 | ||
180 | /* AC timings */ | |
181 | *ctrla = MICRON_V_ACTIMA_165; | |
182 | *ctrlb = MICRON_V_ACTIMB_165; | |
183 | ||
184 | *mr = MICRON_V_MR_165; | |
185 | } |