[people/ms/u-boot.git] / board / toradex / apalis-tk1 / apalis-tk1.c

/*
 * Copyright (c) 2016 Toradex, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch-tegra/ap.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <power/as3722.h>

#include "../common/tdx-common.h"
#include "pinmux-config-apalis-tk1.h"

#define LAN_RESET_N TEGRA_GPIO(S, 2)

int arch_misc_init(void)
{
	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
	    NVBOOTTYPE_RECOVERY)
		printf("USB recovery mode\n");

	return 0;
}

int checkboard(void)
{
	puts("Model: Toradex Apalis TK1 2GB\n");

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	return ft_common_board_setup(blob, bd);
}
#endif

/*
 * Routine: pinmux_init
 * Description: Do individual peripheral pinmux configs
 */
void pinmux_init(void)
{
	pinmux_clear_tristate_input_clamping();

	gpio_config_table(apalis_tk1_gpio_inits,
			  ARRAY_SIZE(apalis_tk1_gpio_inits));

	pinmux_config_pingrp_table(apalis_tk1_pingrps,
				   ARRAY_SIZE(apalis_tk1_pingrps));

	pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
				   ARRAY_SIZE(apalis_tk1_drvgrps));
}

#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
	/* TODO: Convert to driver model
	struct udevice *pmic;
	int err;

	err = as3722_init(&pmic);
	if (err) {
		error("failed to initialize AS3722 PMIC: %d\n", err);
		return err;
	}

	err = as3722_sd_enable(pmic, 4);
	if (err < 0) {
		error("failed to enable SD4: %d\n", err);
		return err;
	}

	err = as3722_sd_set_voltage(pmic, 4, 0x24);
	if (err < 0) {
		error("failed to set SD4 voltage: %d\n", err);
		return err;
	}

	err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
					     AS3722_GPIO_INVERT);
	if (err < 0) {
		error("failed to configure GPIO#1 as output: %d\n", err);
		return err;
	}

	err = as3722_gpio_direction_output(pmic, 2, 1);
	if (err < 0) {
		error("failed to set GPIO#2 high: %d\n", err);
		return err;
	}
	*/

	/* Reset I210 Gigabit Ethernet Controller */
	gpio_request(LAN_RESET_N, "LAN_RESET_N");
	gpio_direction_output(LAN_RESET_N, 0);

	/*
	 * Make sure we don't get any back feeding from LAN_WAKE_N resp.
	 * DEV_OFF_N
	 */
	gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
	gpio_direction_output(TEGRA_GPIO(O, 5), 0);

	gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
	gpio_direction_output(TEGRA_GPIO(O, 6), 0);

	/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
	/* TODO: Convert to driver model
	err = as3722_ldo_enable(pmic, 9);
	if (err < 0) {
		error("failed to enable LDO9: %d\n", err);
		return err;
	}
	err = as3722_ldo_enable(pmic, 10);
	if (err < 0) {
		error("failed to enable LDO10: %d\n", err);
		return err;
	}
	err = as3722_ldo_set_voltage(pmic, 9, 0x80);
	if (err < 0) {
		error("failed to set LDO9 voltage: %d\n", err);
		return err;
	}
	err = as3722_ldo_set_voltage(pmic, 10, 0x80);
	if (err < 0) {
		error("failed to set LDO10 voltage: %d\n", err);
		return err;
	}
	*/

	mdelay(100);

	/* Make sure controller gets enabled by disabling DEV_OFF_N */
	gpio_set_value(TEGRA_GPIO(O, 6), 1);

	/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
	/* TODO: Convert to driver model
	err = as3722_ldo_set_voltage(pmic, 9, 0xff);
	if (err < 0) {
		error("failed to set LDO9 voltage: %d\n", err);
		return err;
	}
	err = as3722_ldo_set_voltage(pmic, 10, 0xff);
	if (err < 0) {
		error("failed to set LDO10 voltage: %d\n", err);
		return err;
	}
	*/

	mdelay(100);
	gpio_set_value(LAN_RESET_N, 1);

#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
#define PEX_PERST_N	TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
#define RESET_MOCI_CTRL	TEGRA_GPIO(U, 4)

	/* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
	   Board */
	gpio_request(PEX_PERST_N, "PEX_PERST_N");
	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
	gpio_direction_output(PEX_PERST_N, 0);
	gpio_direction_output(RESET_MOCI_CTRL, 0);
	/* Must be asserted for 100 ms after power and clocks are stable */
	mdelay(100);
	gpio_set_value(PEX_PERST_N, 1);
	/* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
	   900 us After PEX_PERST# De-assertion */
	mdelay(1);
	gpio_set_value(RESET_MOCI_CTRL, 1);
#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */

	return 0;
}
#endif /* CONFIG_PCI_TEGRA */
Commit	Line	Data
f38f5f4b MZ	1	/*
	2	* Copyright (c) 2016 Toradex, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <asm/arch-tegra/ap.h>
	9	#include <asm/gpio.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/gpio.h>
	12	#include <asm/arch/pinmux.h>
	13	#include <power/as3722.h>
	14
	15	#include "../common/tdx-common.h"
	16	#include "pinmux-config-apalis-tk1.h"
	17
	18	#define LAN_RESET_N TEGRA_GPIO(S, 2)
	19
	20	int arch_misc_init(void)
	21	{
	22	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
	23	NVBOOTTYPE_RECOVERY)
	24	printf("USB recovery mode\n");
	25
	26	return 0;
	27	}
	28
	29	int checkboard(void)
	30	{
	31	puts("Model: Toradex Apalis TK1 2GB\n");
	32
	33	return 0;
	34	}
	35
	36	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	37	int ft_board_setup(void blob, bd_t bd)
	38	{
	39	return ft_common_board_setup(blob, bd);
	40	}
	41	#endif
	42
	43	/*
	44	* Routine: pinmux_init
	45	* Description: Do individual peripheral pinmux configs
	46	*/
	47	void pinmux_init(void)
	48	{
	49	pinmux_clear_tristate_input_clamping();
	50
	51	gpio_config_table(apalis_tk1_gpio_inits,
	52	ARRAY_SIZE(apalis_tk1_gpio_inits));
	53
	54	pinmux_config_pingrp_table(apalis_tk1_pingrps,
	55	ARRAY_SIZE(apalis_tk1_pingrps));
	56
	57	pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
	58	ARRAY_SIZE(apalis_tk1_drvgrps));
	59	}
	60
	61	#ifdef CONFIG_PCI_TEGRA
	62	int tegra_pcie_board_init(void)
	63	{
e3f44f5c	64	/* TODO: Convert to driver model
f38f5f4b MZ	65	struct udevice *pmic;
	66	int err;
	67
	68	err = as3722_init(&pmic);
	69	if (err) {
	70	error("failed to initialize AS3722 PMIC: %d\n", err);
	71	return err;
	72	}
	73
	74	err = as3722_sd_enable(pmic, 4);
	75	if (err < 0) {
	76	error("failed to enable SD4: %d\n", err);
	77	return err;
	78	}
	79
	80	err = as3722_sd_set_voltage(pmic, 4, 0x24);
	81	if (err < 0) {
	82	error("failed to set SD4 voltage: %d\n", err);
	83	return err;
	84	}
	85
	86	err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH \|
	87	AS3722_GPIO_INVERT);
	88	if (err < 0) {
	89	error("failed to configure GPIO#1 as output: %d\n", err);
	90	return err;
	91	}
	92
	93	err = as3722_gpio_direction_output(pmic, 2, 1);
	94	if (err < 0) {
	95	error("failed to set GPIO#2 high: %d\n", err);
	96	return err;
	97	}
e3f44f5c	98	*/
f38f5f4b MZ	99
	100	/* Reset I210 Gigabit Ethernet Controller */
	101	gpio_request(LAN_RESET_N, "LAN_RESET_N");
	102	gpio_direction_output(LAN_RESET_N, 0);
	103
	104	/*
	105	* Make sure we don't get any back feeding from LAN_WAKE_N resp.
	106	* DEV_OFF_N
	107	*/
	108	gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
	109	gpio_direction_output(TEGRA_GPIO(O, 5), 0);
	110
	111	gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
	112	gpio_direction_output(TEGRA_GPIO(O, 6), 0);
	113
	114	/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
e3f44f5c	115	/* TODO: Convert to driver model
f38f5f4b MZ	116	err = as3722_ldo_enable(pmic, 9);
	117	if (err < 0) {
	118	error("failed to enable LDO9: %d\n", err);
	119	return err;
	120	}
	121	err = as3722_ldo_enable(pmic, 10);
	122	if (err < 0) {
	123	error("failed to enable LDO10: %d\n", err);
	124	return err;
	125	}
	126	err = as3722_ldo_set_voltage(pmic, 9, 0x80);
	127	if (err < 0) {
	128	error("failed to set LDO9 voltage: %d\n", err);
	129	return err;
	130	}
	131	err = as3722_ldo_set_voltage(pmic, 10, 0x80);
	132	if (err < 0) {
	133	error("failed to set LDO10 voltage: %d\n", err);
	134	return err;
	135	}
e3f44f5c	136	*/
f38f5f4b MZ	137
	138	mdelay(100);
	139
	140	/* Make sure controller gets enabled by disabling DEV_OFF_N */
	141	gpio_set_value(TEGRA_GPIO(O, 6), 1);
	142
	143	/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
e3f44f5c	144	/* TODO: Convert to driver model
f38f5f4b MZ	145	err = as3722_ldo_set_voltage(pmic, 9, 0xff);
	146	if (err < 0) {
	147	error("failed to set LDO9 voltage: %d\n", err);
	148	return err;
	149	}
	150	err = as3722_ldo_set_voltage(pmic, 10, 0xff);
	151	if (err < 0) {
	152	error("failed to set LDO10 voltage: %d\n", err);
	153	return err;
	154	}
e3f44f5c	155	*/
f38f5f4b MZ	156
	157	mdelay(100);
	158	gpio_set_value(LAN_RESET_N, 1);
	159
	160	#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
	161	#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
	162	#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
	163
	164	/* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
	165	Board */
	166	gpio_request(PEX_PERST_N, "PEX_PERST_N");
	167	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
	168	gpio_direction_output(PEX_PERST_N, 0);
	169	gpio_direction_output(RESET_MOCI_CTRL, 0);
	170	/* Must be asserted for 100 ms after power and clocks are stable */
	171	mdelay(100);
	172	gpio_set_value(PEX_PERST_N, 1);
	173	/* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
	174	900 us After PEX_PERST# De-assertion */
	175	mdelay(1);
	176	gpio_set_value(RESET_MOCI_CTRL, 1);
	177	#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
	178
	179	return 0;
	180	}
	181	#endif /* CONFIG_PCI_TEGRA */