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common: Drop image.h from common header
[thirdparty/u-boot.git] / board / toradex / apalis_imx6 / apalis_imx6.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
592f4aed
MK		 2/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5177087f 5 * Copyright (C) 2014-2019, Toradex AG
592f4aed 6 * copied from nitrogen6x
592f4aed
MK		 7 */
8
9#include <common.h>
9a3b4ceb 10#include <cpu_func.h>
9d922450 11#include <dm.h>
4d72caa5 12#include <image.h>
5255932f 13#include <init.h>
90526e9f 14#include <net.h>
5177087f 15
72b49e2c 16#include <ahci.h>
592f4aed
MK		 17#include <asm/arch/clock.h>
18#include <asm/arch/crm_regs.h>
592f4aed 19#include <asm/arch/imx-regs.h>
592f4aed 20#include <asm/arch/mx6-ddr.h>
5177087f
MZ		 21#include <asm/arch/mx6-pins.h>
22#include <asm/arch/mxc_hdmi.h>
23#include <asm/arch/sys_proto.h>
592f4aed
MK		 24#include <asm/bootm.h>
25#include <asm/gpio.h>
5177087f 26#include <asm/mach-imx/boot_mode.h>
552a848e 27#include <asm/mach-imx/iomux-v3.h>
552a848e 28#include <asm/mach-imx/sata.h>
552a848e 29#include <asm/mach-imx/video.h>
72b49e2c 30#include <dm/device-internal.h>
592f4aed 31#include <dm/platform_data/serial_mxc.h>
72b49e2c 32#include <dwc_ahsata.h>
9fb625ce 33#include <env.h>
e37ac717 34#include <fsl_esdhc_imx.h>
592f4aed 35#include <imx_thermal.h>
592f4aed
MK		 36#include <micrel.h>
37#include <miiphy.h>
38#include <netdev.h>
39
40#include "../common/tdx-cfg-block.h"
41#ifdef CONFIG_TDX_CMD_IMX_MFGR
42#include "pf0100.h"
43#endif
44
45DECLARE_GLOBAL_DATA_PTR;
46
47#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50
51#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
3ef55a74
MK		 52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54
55#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
592f4aed
MK		 56 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
57 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58
59#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
61
592f4aed
MK		 62#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
64 PAD_CTL_SRE_SLOW)
65
592f4aed
MK		 66#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
67 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
68 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
69
70#define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
71
592f4aed
MK		 72#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
73
72b49e2c
MZ		 74#define APALIS_IMX6_SATA_INIT_RETRIES 10
75
592f4aed
MK		 76int dram_init(void)
77{
78 /* use the DDR controllers configured size */
79 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
80 (ulong)imx_ddr_size());
81
82 return 0;
83}
84
85/* Apalis UART1 */
86iomux_v3_cfg_t const uart1_pads_dce[] = {
87 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
88 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
89};
90iomux_v3_cfg_t const uart1_pads_dte[] = {
91 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
92 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
93};
94
536c564b 95#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
592f4aed
MK		 96/* Apalis MMC1 */
97iomux_v3_cfg_t const usdhc1_pads[] = {
98 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
109# define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
110};
111
112/* Apalis SD1 */
113iomux_v3_cfg_t const usdhc2_pads[] = {
114 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
121# define GPIO_SD_CD IMX_GPIO_NR(6, 14)
122};
123
124/* eMMC */
125iomux_v3_cfg_t const usdhc3_pads[] = {
3ef55a74
MK		 126 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
127 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
128 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
129 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
130 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
131 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
132 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
133 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
134 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
135 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
5177087f 136 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
592f4aed 137};
e37ac717 138#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
592f4aed
MK		 139
140int mx6_rgmii_rework(struct phy_device *phydev)
141{
f72e48ba
PS		 142 int tmp;
143
144 switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
145 case PHY_ID_KSZ9131:
146 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
147 tmp = ksz9031_phy_extended_read(phydev, 0x02,
148 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
149 MII_KSZ9031_MOD_DATA_NO_POST_INC);
150 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
151 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
152 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
153 ksz9031_phy_extended_write(phydev, 0x02,
154 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
155 MII_KSZ9031_MOD_DATA_NO_POST_INC,
156 tmp);
157 /* read txc dll control - devaddr = 0x02, register = 0x4d */
158 tmp = ksz9031_phy_extended_read(phydev, 0x02,
159 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
160 MII_KSZ9031_MOD_DATA_NO_POST_INC);
161 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
162 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
163 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
164 ksz9031_phy_extended_write(phydev, 0x02,
165 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
166 MII_KSZ9031_MOD_DATA_NO_POST_INC,
167 tmp);
168
169 /* control data pad skew - devaddr = 0x02, register = 0x04 */
170 ksz9031_phy_extended_write(phydev, 0x02,
171 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
172 MII_KSZ9031_MOD_DATA_NO_POST_INC,
173 0x007d);
174 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
175 ksz9031_phy_extended_write(phydev, 0x02,
176 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
177 MII_KSZ9031_MOD_DATA_NO_POST_INC,
178 0x7777);
179 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
180 ksz9031_phy_extended_write(phydev, 0x02,
181 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
182 MII_KSZ9031_MOD_DATA_NO_POST_INC,
183 0xdddd);
184 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
185 ksz9031_phy_extended_write(phydev, 0x02,
186 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
187 MII_KSZ9031_MOD_DATA_NO_POST_INC,
188 0x0007);
189 break;
190 case PHY_ID_KSZ9031:
191 default:
192 /* control data pad skew - devaddr = 0x02, register = 0x04 */
193 ksz9031_phy_extended_write(phydev, 0x02,
194 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
195 MII_KSZ9031_MOD_DATA_NO_POST_INC,
196 0x0000);
197 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
198 ksz9031_phy_extended_write(phydev, 0x02,
199 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
200 MII_KSZ9031_MOD_DATA_NO_POST_INC,
201 0x0000);
202 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
203 ksz9031_phy_extended_write(phydev, 0x02,
204 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
205 MII_KSZ9031_MOD_DATA_NO_POST_INC,
206 0x0000);
207 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
208 ksz9031_phy_extended_write(phydev, 0x02,
209 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
210 MII_KSZ9031_MOD_DATA_NO_POST_INC,
211 0x03FF);
212 break;
213 }
214
592f4aed
MK		 215 return 0;
216}
217
218iomux_v3_cfg_t const enet_pads[] = {
219 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
220 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
221 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
222 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
223 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
224 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
225 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 /* KSZ9031 PHY Reset */
5177087f
MZ		 235 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
236 MUX_MODE_SION,
592f4aed
MK		 237# define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
238};
239
592f4aed
MK		 240/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
241iomux_v3_cfg_t const gpio_pads[] = {
242 /* Apalis GPIO1 - GPIO8 */
5177087f
MZ		 243 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
244 MUX_MODE_SION,
245 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
246 MUX_MODE_SION,
247 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
248 MUX_MODE_SION,
249 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
250 MUX_MODE_SION,
251 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
252 MUX_MODE_SION,
253 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
254 MUX_MODE_SION,
255 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
256 MUX_MODE_SION,
257 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
258 MUX_MODE_SION,
259 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
260 MUX_MODE_SION,
592f4aed
MK		 261};
262
263static void setup_iomux_gpio(void)
264{
265 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
266}
267
268iomux_v3_cfg_t const usb_pads[] = {
269 /* USBH_EN */
5177087f 270 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
592f4aed
MK		 271# define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
272 /* USB_VBUS_DET */
273 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
274# define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
275 /* USBO1_ID */
276 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
277 /* USBO1_EN */
5177087f 278 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
592f4aed
MK		 279# define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
280};
281
282/*
283 * UARTs are used in DTE mode, switch the mode on all UARTs before
284 * any pinmuxing connects a (DCE) output to a transceiver output.
285 */
389f61ef
MK		 286#define UCR3 0x88 /* FIFO Control Register */
287#define UCR3_RI BIT(8) /* RIDELT DTE mode */
288#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
592f4aed 289#define UFCR 0x90 /* FIFO Control Register */
389f61ef 290#define UFCR_DCEDTE BIT(6) /* DCE=0 */
592f4aed
MK		 291
292static void setup_dtemode_uart(void)
293{
294 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
295 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
296 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
297 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
389f61ef
MK		 298
299 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
300 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
301 clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
302 clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
592f4aed
MK		 303}
304static void setup_dcemode_uart(void)
305{
306 clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
307 clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
308 clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
309 clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
310}
311
312static void setup_iomux_dte_uart(void)
313{
314 setup_dtemode_uart();
315 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
316 ARRAY_SIZE(uart1_pads_dte));
317}
592f4aed
MK		 318static void setup_iomux_dce_uart(void)
319{
320 setup_dcemode_uart();
321 imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
322 ARRAY_SIZE(uart1_pads_dce));
323}
324
325#ifdef CONFIG_USB_EHCI_MX6
326int board_ehci_hcd_init(int port)
327{
328 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
329 return 0;
330}
592f4aed
MK		 331#endif
332
536c564b 333#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
5177087f 334/* use the following sequence: eMMC, MMC1, SD1 */
592f4aed
MK		 335struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
336 {USDHC3_BASE_ADDR},
337 {USDHC1_BASE_ADDR},
338 {USDHC2_BASE_ADDR},
339};
340
341int board_mmc_getcd(struct mmc *mmc)
342{
343 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
344 int ret = true; /* default: assume inserted */
345
346 switch (cfg->esdhc_base) {
347 case USDHC1_BASE_ADDR:
5177087f 348 gpio_request(GPIO_MMC_CD, "MMC_CD");
592f4aed
MK		 349 gpio_direction_input(GPIO_MMC_CD);
350 ret = !gpio_get_value(GPIO_MMC_CD);
351 break;
352 case USDHC2_BASE_ADDR:
5177087f 353 gpio_request(GPIO_MMC_CD, "SD_CD");
592f4aed
MK		 354 gpio_direction_input(GPIO_SD_CD);
355 ret = !gpio_get_value(GPIO_SD_CD);
356 break;
357 }
358
359 return ret;
360}
361
362int board_mmc_init(bd_t *bis)
363{
592f4aed
MK		 364 struct src *psrc = (struct src *)SRC_BASE_ADDR;
365 unsigned reg = readl(&psrc->sbmr1) >> 11;
366 /*
367 * Upon reading BOOT_CFG register the following map is done:
368 * Bit 11 and 12 of BOOT_CFG register can determine the current
369 * mmc port
370 * 0x1 SD1
371 * 0x2 SD2
372 * 0x3 SD4
373 */
374
375 switch (reg & 0x3) {
376 case 0x0:
377 imx_iomux_v3_setup_multiple_pads(
378 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
379 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
380 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
381 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
382 break;
383 case 0x1:
384 imx_iomux_v3_setup_multiple_pads(
385 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
386 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
387 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
388 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
389 break;
390 case 0x2:
391 imx_iomux_v3_setup_multiple_pads(
392 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
393 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
394 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
395 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
396 break;
397 default:
398 puts("MMC boot device not available");
399 }
400
401 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
592f4aed 402}
e37ac717 403#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
592f4aed
MK		 404
405int board_phy_config(struct phy_device *phydev)
406{
407 mx6_rgmii_rework(phydev);
408 if (phydev->drv->config)
409 phydev->drv->config(phydev);
410
411 return 0;
412}
413
592f4aed
MK		 414static iomux_v3_cfg_t const pwr_intb_pads[] = {
415 /*
416 * the bootrom sets the iomux to vselect, potentially connecting
417 * two outputs. Set this back to GPIO
418 */
419 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
420};
421
422#if defined(CONFIG_VIDEO_IPUV3)
423
424static iomux_v3_cfg_t const backlight_pads[] = {
425 /* Backlight on RGB connector: J15 */
5177087f
MZ		 426 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
427 MUX_MODE_SION,
592f4aed
MK		 428#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
429 /* additional CPU pin on BKL_PWM, keep in tristate */
430 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
431 /* Backlight PWM, used as GPIO in U-Boot */
5177087f
MZ		 432 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
433 MUX_MODE_SION,
592f4aed
MK		 434#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
435 /* buffer output enable 0: buffer enabled */
5177087f 436 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
592f4aed
MK		 437#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
438 /* PSAVE# integrated VDAC */
5177087f
MZ		 439 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
440 MUX_MODE_SION,
592f4aed
MK		 441#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
442};
443
444static iomux_v3_cfg_t const rgb_pads[] = {
445 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
446 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
447 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
448 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
449 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
450 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
451 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
452 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
453 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
454 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
455 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
456 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
457 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
458 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
459 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
460 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
461 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
462 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
463 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
464 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
465 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
466 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
467 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
468 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
469 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
470 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
471 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
472 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
473};
474
592f4aed
MK		 475static void do_enable_hdmi(struct display_info_t const *dev)
476{
477 imx_enable_hdmi_phy();
478}
479
592f4aed
MK		 480static void enable_lvds(struct display_info_t const *dev)
481{
482 struct iomuxc *iomux = (struct iomuxc *)
483 IOMUXC_BASE_ADDR;
484 u32 reg = readl(&iomux->gpr[2]);
485 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
486 writel(reg, &iomux->gpr[2]);
487 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
488 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
489 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
490}
491
492static void enable_rgb(struct display_info_t const *dev)
493{
494 imx_iomux_v3_setup_multiple_pads(
495 rgb_pads,
496 ARRAY_SIZE(rgb_pads));
497 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
498 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
499 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
500}
501
502static int detect_default(struct display_info_t const *dev)
503{
504 (void) dev;
505 return 1;
506}
507
508struct display_info_t const displays[] = {{
509 .bus = -1,
510 .addr = 0,
511 .pixfmt = IPU_PIX_FMT_RGB24,
512 .detect = detect_hdmi,
513 .enable = do_enable_hdmi,
514 .mode = {
515 .name = "HDMI",
516 .refresh = 60,
517 .xres = 1024,
518 .yres = 768,
519 .pixclock = 15385,
520 .left_margin = 220,
521 .right_margin = 40,
522 .upper_margin = 21,
523 .lower_margin = 7,
524 .hsync_len = 60,
525 .vsync_len = 10,
526 .sync = FB_SYNC_EXT,
527 .vmode = FB_VMODE_NONINTERLACED
528} }, {
529 .bus = -1,
530 .addr = 0,
531 .di = 1,
532 .pixfmt = IPU_PIX_FMT_RGB24,
533 .detect = detect_default,
534 .enable = enable_rgb,
535 .mode = {
536 .name = "vga-rgb",
537 .refresh = 60,
538 .xres = 640,
539 .yres = 480,
540 .pixclock = 33000,
541 .left_margin = 48,
542 .right_margin = 16,
543 .upper_margin = 31,
544 .lower_margin = 11,
545 .hsync_len = 96,
546 .vsync_len = 2,
547 .sync = 0,
548 .vmode = FB_VMODE_NONINTERLACED
549} }, {
550 .bus = -1,
551 .addr = 0,
552 .di = 1,
553 .pixfmt = IPU_PIX_FMT_RGB24,
554 .enable = enable_rgb,
555 .mode = {
556 .name = "wvga-rgb",
557 .refresh = 60,
558 .xres = 800,
559 .yres = 480,
560 .pixclock = 25000,
561 .left_margin = 40,
562 .right_margin = 88,
563 .upper_margin = 33,
564 .lower_margin = 10,
565 .hsync_len = 128,
566 .vsync_len = 2,
567 .sync = 0,
568 .vmode = FB_VMODE_NONINTERLACED
569} }, {
570 .bus = -1,
571 .addr = 0,
572 .pixfmt = IPU_PIX_FMT_LVDS666,
592f4aed
MK		 573 .enable = enable_lvds,
574 .mode = {
575 .name = "wsvga-lvds",
576 .refresh = 60,
577 .xres = 1024,
578 .yres = 600,
579 .pixclock = 15385,
580 .left_margin = 220,
581 .right_margin = 40,
582 .upper_margin = 21,
583 .lower_margin = 7,
584 .hsync_len = 60,
585 .vsync_len = 10,
586 .sync = FB_SYNC_EXT,
587 .vmode = FB_VMODE_NONINTERLACED
588} } };
589size_t display_count = ARRAY_SIZE(displays);
590
591static void setup_display(void)
592{
593 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
594 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
595 int reg;
596
597 enable_ipu_clock();
598 imx_setup_hdmi();
599 /* Turn on LDB0,IPU,IPU DI0 clocks */
600 reg = __raw_readl(&mxc_ccm->CCGR3);
601 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
602 writel(reg, &mxc_ccm->CCGR3);
603
604 /* set LDB0, LDB1 clk select to 011/011 */
605 reg = readl(&mxc_ccm->cs2cdr);
606 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
607 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
608 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
609 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
610 writel(reg, &mxc_ccm->cs2cdr);
611
612 reg = readl(&mxc_ccm->cscmr2);
613 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
614 writel(reg, &mxc_ccm->cscmr2);
615
616 reg = readl(&mxc_ccm->chsccdr);
617 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
618 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
619 writel(reg, &mxc_ccm->chsccdr);
620
621 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
622 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
623 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
624 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
625 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
626 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
627 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
628 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
629 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
630 writel(reg, &iomux->gpr[2]);
631
632 reg = readl(&iomux->gpr[3]);
633 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
634 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
635 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
636 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
637 writel(reg, &iomux->gpr[3]);
638
639 /* backlight unconditionally on for now */
640 imx_iomux_v3_setup_multiple_pads(backlight_pads,
641 ARRAY_SIZE(backlight_pads));
642 /* use 0 for EDT 7", use 1 for LG fullHD panel */
5177087f
MZ		 643 gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
644 gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
645 gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
592f4aed
MK		 646 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
647 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
648 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
649}
a3c90217
GS		 650
651/*
652 * Backlight off before OS handover
653 */
654void board_preboot_os(void)
655{
656 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
657 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
658}
592f4aed
MK		 659#endif /* defined(CONFIG_VIDEO_IPUV3) */
660
661int board_early_init_f(void)
662{
663 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
664 ARRAY_SIZE(pwr_intb_pads));
665#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
666 setup_iomux_dte_uart();
667#else
668 setup_iomux_dce_uart();
669#endif
592f4aed
MK		 670 return 0;
671}
672
673/*
674 * Do not overwrite the console
675 * Use always serial for U-Boot console
676 */
677int overwrite_console(void)
678{
679 return 1;
680}
681
682int board_init(void)
683{
684 /* address of boot parameters */
685 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
686
f89bfe7c
FE		 687#if defined(CONFIG_VIDEO_IPUV3)
688 setup_display();
689#endif
690
592f4aed
MK		 691#ifdef CONFIG_TDX_CMD_IMX_MFGR
692 (void) pmic_init();
693#endif
694
10e40d54 695#ifdef CONFIG_SATA
592f4aed
MK		 696 setup_sata();
697#endif
698
699 setup_iomux_gpio();
700
701 return 0;
702}
703
704#ifdef CONFIG_BOARD_LATE_INIT
705int board_late_init(void)
706{
707#if defined(CONFIG_REVISION_TAG) && \
708 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
709 char env_str[256];
710 u32 rev;
711
712 rev = get_board_rev();
713 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
382bee57 714 env_set("board_rev", env_str);
592f4aed
MK		 715
716#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
717 if ((rev & 0xfff0) == 0x0100) {
718 char *fdt_env;
719
720 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
721 setup_iomux_dce_uart();
722
723 /* if using the default device tree, use version for V1.0 HW */
00caae6d 724 fdt_env = env_get("fdt_file");
592f4aed 725 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
382bee57 726 env_set("fdt_file", FDT_FILE_V1_0);
592f4aed
MK		 727 printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
728#ifndef CONFIG_ENV_IS_NOWHERE
01510091 729 env_save();
592f4aed
MK		 730#endif
731 }
732 }
733#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
734#endif /* CONFIG_REVISION_TAG */
735
15834c63
SA		 736#ifdef CONFIG_CMD_USB_SDP
737 if (is_boot_from_usb()) {
738 printf("Serial Downloader recovery mode, using sdp command\n");
739 env_set("bootdelay", "0");
740 env_set("bootcmd", "sdp 0");
741 }
742#endif /* CONFIG_CMD_USB_SDP */
743
592f4aed
MK		 744 return 0;
745}
746#endif /* CONFIG_BOARD_LATE_INIT */
747
592f4aed
MK		 748int checkboard(void)
749{
750 char it[] = " IT";
751 int minc, maxc;
752
753 switch (get_cpu_temp_grade(&minc, &maxc)) {
754 case TEMP_AUTOMOTIVE:
755 case TEMP_INDUSTRIAL:
756 break;
757 case TEMP_EXTCOMMERCIAL:
758 default:
759 it[0] = 0;
760 };
761 printf("Model: Toradex Apalis iMX6 %s %s%s\n",
762 is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
763 (gd->ram_size == 0x80000000) ? "2GB" :
764 (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
765 return 0;
766}
767
768#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
769int ft_board_setup(void *blob, bd_t *bd)
770{
771 return ft_common_board_setup(blob, bd);
772}
773#endif
774
775#ifdef CONFIG_CMD_BMODE
776static const struct boot_mode board_boot_modes[] = {
777 /* 4-bit bus width */
778 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
779 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
780 {NULL, 0},
781};
782#endif
783
784int misc_init_r(void)
785{
786#ifdef CONFIG_CMD_BMODE
787 add_board_boot_modes(board_boot_modes);
788#endif
789 return 0;
790}
791
792#ifdef CONFIG_LDO_BYPASS_CHECK
793/* TODO, use external pmic, for now always ldo_enable */
794void ldo_mode_set(int ldo_bypass)
795{
796 return;
797}
798#endif
799
800#ifdef CONFIG_SPL_BUILD
801#include <spl.h>
b08c8c48 802#include <linux/libfdt.h>
592f4aed
MK		 803#include "asm/arch/mx6q-ddr.h"
804#include "asm/arch/iomux.h"
805#include "asm/arch/crm_regs.h"
806
807static int mx6_com_dcd_table[] = {
808/* ddr-setup.cfg */
809MX6_IOM_DRAM_SDQS0, 0x00000030,
810MX6_IOM_DRAM_SDQS1, 0x00000030,
811MX6_IOM_DRAM_SDQS2, 0x00000030,
812MX6_IOM_DRAM_SDQS3, 0x00000030,
813MX6_IOM_DRAM_SDQS4, 0x00000030,
814MX6_IOM_DRAM_SDQS5, 0x00000030,
815MX6_IOM_DRAM_SDQS6, 0x00000030,
816MX6_IOM_DRAM_SDQS7, 0x00000030,
817
818MX6_IOM_GRP_B0DS, 0x00000030,
819MX6_IOM_GRP_B1DS, 0x00000030,
820MX6_IOM_GRP_B2DS, 0x00000030,
821MX6_IOM_GRP_B3DS, 0x00000030,
822MX6_IOM_GRP_B4DS, 0x00000030,
823MX6_IOM_GRP_B5DS, 0x00000030,
824MX6_IOM_GRP_B6DS, 0x00000030,
825MX6_IOM_GRP_B7DS, 0x00000030,
826MX6_IOM_GRP_ADDDS, 0x00000030,
827/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
828MX6_IOM_GRP_CTLDS, 0x00000030,
829
830MX6_IOM_DRAM_DQM0, 0x00020030,
831MX6_IOM_DRAM_DQM1, 0x00020030,
832MX6_IOM_DRAM_DQM2, 0x00020030,
833MX6_IOM_DRAM_DQM3, 0x00020030,
834MX6_IOM_DRAM_DQM4, 0x00020030,
835MX6_IOM_DRAM_DQM5, 0x00020030,
836MX6_IOM_DRAM_DQM6, 0x00020030,
837MX6_IOM_DRAM_DQM7, 0x00020030,
838
839MX6_IOM_DRAM_CAS, 0x00020030,
840MX6_IOM_DRAM_RAS, 0x00020030,
841MX6_IOM_DRAM_SDCLK_0, 0x00020030,
842MX6_IOM_DRAM_SDCLK_1, 0x00020030,
843
844MX6_IOM_DRAM_RESET, 0x00020030,
845MX6_IOM_DRAM_SDCKE0, 0x00003000,
846MX6_IOM_DRAM_SDCKE1, 0x00003000,
847
848MX6_IOM_DRAM_SDODT0, 0x00003030,
849MX6_IOM_DRAM_SDODT1, 0x00003030,
850
851/* (differential input) */
852MX6_IOM_DDRMODE_CTL, 0x00020000,
853/* (differential input) */
854MX6_IOM_GRP_DDRMODE, 0x00020000,
855/* disable ddr pullups */
856MX6_IOM_GRP_DDRPKE, 0x00000000,
857MX6_IOM_DRAM_SDBA2, 0x00000000,
858/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
859MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
860
861/* Read data DQ Byte0-3 delay */
862MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
863MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
864MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
865MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
866MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
867MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
868MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
869MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
870
871/*
872 * MDMISC mirroring interleaved (row/bank/col)
873 */
874MX6_MMDC_P0_MDMISC, 0x00081740,
875
876/*
877 * MDSCR con_req
878 */
879MX6_MMDC_P0_MDSCR, 0x00008000,
880
881/* 1066mhz_4x128mx16.cfg */
882
883MX6_MMDC_P0_MDPDC, 0x00020036,
884MX6_MMDC_P0_MDCFG0, 0x555A7954,
885MX6_MMDC_P0_MDCFG1, 0xDB328F64,
886MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
887MX6_MMDC_P0_MDRWD, 0x000026D2,
888MX6_MMDC_P0_MDOR, 0x005A1023,
889MX6_MMDC_P0_MDOTC, 0x09555050,
890MX6_MMDC_P0_MDPDC, 0x00025576,
891MX6_MMDC_P0_MDASP, 0x00000027,
892MX6_MMDC_P0_MDCTL, 0x831A0000,
893MX6_MMDC_P0_MDSCR, 0x04088032,
894MX6_MMDC_P0_MDSCR, 0x00008033,
895MX6_MMDC_P0_MDSCR, 0x00428031,
896MX6_MMDC_P0_MDSCR, 0x19308030,
897MX6_MMDC_P0_MDSCR, 0x04008040,
898MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
899MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
900MX6_MMDC_P0_MDREF, 0x00005800,
901MX6_MMDC_P0_MPODTCTRL, 0x00000000,
902MX6_MMDC_P1_MPODTCTRL, 0x00000000,
903
904MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
905MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
906MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
907MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
908
909MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
910MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
911
912MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
913MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
914
915MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
916MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
917MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
918MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
919
920MX6_MMDC_P0_MPMUR0, 0x00000800,
921MX6_MMDC_P1_MPMUR0, 0x00000800,
922MX6_MMDC_P0_MDSCR, 0x00000000,
923MX6_MMDC_P0_MAPSR, 0x00011006,
924};
925
926static int mx6_it_dcd_table[] = {
927/* ddr-setup.cfg */
928MX6_IOM_DRAM_SDQS0, 0x00000030,
929MX6_IOM_DRAM_SDQS1, 0x00000030,
930MX6_IOM_DRAM_SDQS2, 0x00000030,
931MX6_IOM_DRAM_SDQS3, 0x00000030,
932MX6_IOM_DRAM_SDQS4, 0x00000030,
933MX6_IOM_DRAM_SDQS5, 0x00000030,
934MX6_IOM_DRAM_SDQS6, 0x00000030,
935MX6_IOM_DRAM_SDQS7, 0x00000030,
936
937MX6_IOM_GRP_B0DS, 0x00000030,
938MX6_IOM_GRP_B1DS, 0x00000030,
939MX6_IOM_GRP_B2DS, 0x00000030,
940MX6_IOM_GRP_B3DS, 0x00000030,
941MX6_IOM_GRP_B4DS, 0x00000030,
942MX6_IOM_GRP_B5DS, 0x00000030,
943MX6_IOM_GRP_B6DS, 0x00000030,
944MX6_IOM_GRP_B7DS, 0x00000030,
945MX6_IOM_GRP_ADDDS, 0x00000030,
946/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
947MX6_IOM_GRP_CTLDS, 0x00000030,
948
949MX6_IOM_DRAM_DQM0, 0x00020030,
950MX6_IOM_DRAM_DQM1, 0x00020030,
951MX6_IOM_DRAM_DQM2, 0x00020030,
952MX6_IOM_DRAM_DQM3, 0x00020030,
953MX6_IOM_DRAM_DQM4, 0x00020030,
954MX6_IOM_DRAM_DQM5, 0x00020030,
955MX6_IOM_DRAM_DQM6, 0x00020030,
956MX6_IOM_DRAM_DQM7, 0x00020030,
957
958MX6_IOM_DRAM_CAS, 0x00020030,
959MX6_IOM_DRAM_RAS, 0x00020030,
960MX6_IOM_DRAM_SDCLK_0, 0x00020030,
961MX6_IOM_DRAM_SDCLK_1, 0x00020030,
962
963MX6_IOM_DRAM_RESET, 0x00020030,
964MX6_IOM_DRAM_SDCKE0, 0x00003000,
965MX6_IOM_DRAM_SDCKE1, 0x00003000,
966
967MX6_IOM_DRAM_SDODT0, 0x00003030,
968MX6_IOM_DRAM_SDODT1, 0x00003030,
969
970/* (differential input) */
971MX6_IOM_DDRMODE_CTL, 0x00020000,
972/* (differential input) */
973MX6_IOM_GRP_DDRMODE, 0x00020000,
974/* disable ddr pullups */
975MX6_IOM_GRP_DDRPKE, 0x00000000,
976MX6_IOM_DRAM_SDBA2, 0x00000000,
977/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
978MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
979
980/* Read data DQ Byte0-3 delay */
981MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
982MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
983MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
984MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
985MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
986MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
987MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
988MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
989
990/*
991 * MDMISC mirroring interleaved (row/bank/col)
992 */
993MX6_MMDC_P0_MDMISC, 0x00081740,
994
995/*
996 * MDSCR con_req
997 */
998MX6_MMDC_P0_MDSCR, 0x00008000,
999
1000/* 1066mhz_4x256mx16.cfg */
1001
1002MX6_MMDC_P0_MDPDC, 0x00020036,
1003MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1004MX6_MMDC_P0_MDCFG1, 0xff328f64,
1005MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1006MX6_MMDC_P0_MDRWD, 0x000026D2,
1007MX6_MMDC_P0_MDOR, 0x008E1023,
1008MX6_MMDC_P0_MDOTC, 0x09444040,
1009MX6_MMDC_P0_MDPDC, 0x00025576,
1010MX6_MMDC_P0_MDASP, 0x00000047,
1011MX6_MMDC_P0_MDCTL, 0x841A0000,
1012MX6_MMDC_P0_MDSCR, 0x02888032,
1013MX6_MMDC_P0_MDSCR, 0x00008033,
1014MX6_MMDC_P0_MDSCR, 0x00048031,
1015MX6_MMDC_P0_MDSCR, 0x19408030,
1016MX6_MMDC_P0_MDSCR, 0x04008040,
1017MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1018MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1019MX6_MMDC_P0_MDREF, 0x00007800,
1020MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1021MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1022
1023MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1024MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1025MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1026MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1027
1028MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1029MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1030
1031MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1032MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1033
1034MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1035MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1036MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1037MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1038
1039MX6_MMDC_P0_MPMUR0, 0x00000800,
1040MX6_MMDC_P1_MPMUR0, 0x00000800,
1041MX6_MMDC_P0_MDSCR, 0x00000000,
1042MX6_MMDC_P0_MAPSR, 0x00011006,
1043};
1044
592f4aed
MK		 1045static void ccgr_init(void)
1046{
1047 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1048
1049 writel(0x00C03F3F, &ccm->CCGR0);
1050 writel(0x0030FC03, &ccm->CCGR1);
1051 writel(0x0FFFFFF3, &ccm->CCGR2);
1052 writel(0x3FF0300F, &ccm->CCGR3);
1053 writel(0x00FFF300, &ccm->CCGR4);
1054 writel(0x0F0000F3, &ccm->CCGR5);
1055 writel(0x000003FF, &ccm->CCGR6);
1056
1057/*
1058 * Setup CCM_CCOSR register as follows:
1059 *
1060 * cko1_en = 1 --> CKO1 enabled
1061 * cko1_div = 111 --> divide by 8
1062 * cko1_sel = 1011 --> ahb_clk_root
1063 *
1064 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1065 */
1066 writel(0x000000FB, &ccm->ccosr);
1067}
1068
592f4aed
MK		 1069static void ddr_init(int *table, int size)
1070{
1071 int i;
1072
1073 for (i = 0; i < size / 2 ; i++)
1074 writel(table[2 * i + 1], table[2 * i]);
1075}
1076
1077static void spl_dram_init(void)
1078{
1079 int minc, maxc;
1080
1081 switch (get_cpu_temp_grade(&minc, &maxc)) {
1082 case TEMP_COMMERCIAL:
1083 case TEMP_EXTCOMMERCIAL:
1084 puts("Commercial temperature grade DDR3 timings.\n");
1085 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1086 break;
1087 case TEMP_INDUSTRIAL:
1088 case TEMP_AUTOMOTIVE:
1089 default:
1090 puts("Industrial temperature grade DDR3 timings.\n");
1091 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1092 break;
1093 };
1094 udelay(100);
1095}
1096
1097void board_init_f(ulong dummy)
1098{
1099 /* setup AIPS and disable watchdog */
1100 arch_cpu_init();
1101
1102 ccgr_init();
1103 gpr_init();
1104
ab92352d 1105 /* iomux */
592f4aed
MK		 1106 board_early_init_f();
1107
1108 /* setup GP timer */
1109 timer_init();
1110
1111 /* UART clocks enabled and gd valid - init serial console */
1112 preloader_console_init();
1113
1114#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1115 /* Make sure we use dte mode */
1116 setup_dtemode_uart();
1117#endif
1118
1119 /* DDR initialization */
1120 spl_dram_init();
1121
1122 /* Clear the BSS. */
1123 memset(__bss_start, 0, __bss_end - __bss_start);
1124
1125 /* load/boot image from boot device */
1126 board_init_r(NULL, 0);
1127}
1128
6f8ef051
RS		 1129#ifdef CONFIG_SPL_LOAD_FIT
1130int board_fit_config_name_match(const char *name)
1131{
1132 if (!strcmp(name, "imx6-apalis"))
1133 return 0;
1134
1135 return -1;
1136}
1137#endif
1138
592f4aed
MK		 1139void reset_cpu(ulong addr)
1140{
1141}
1142
5177087f 1143#endif /* CONFIG_SPL_BUILD */
592f4aed
MK		 1144
1145static struct mxc_serial_platdata mxc_serial_plat = {
1146 .reg = (struct mxc_uart *)UART1_BASE,
1147 .use_dte = true,
1148};
1149
1150U_BOOT_DEVICE(mxc_serial) = {
1151 .name = "serial_mxc",
1152 .platdata = &mxc_serial_plat,
1153};
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