]>
Commit | Line | Data |
---|---|---|
592f4aed MK |
1 | /* |
2 | * Copyright (C) 2013 Boundary Devices | |
3 | * Copyright (C) 2014-2016, Toradex AG | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | * | |
7 | * Device Configuration Data (DCD) | |
8 | * | |
9 | * Each entry must have the format: | |
10 | * Addr-type Address Value | |
11 | * | |
12 | * where: | |
13 | * Addr-type register length (1,2 or 4 bytes) | |
14 | * Address absolute address of the register | |
15 | * value value to be stored in the register | |
16 | */ | |
17 | ||
18 | /* | |
19 | * DDR3 settings | |
20 | * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), | |
21 | * memory bus width: 64 bits x16/x32/x64 | |
22 | * MX6DL ddr is limited to 800 MHz(400 MHz clock) | |
23 | * memory bus width: 64 bits x16/x32/x64 | |
24 | * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) | |
25 | * memory bus width: 32 bits x16/x32 | |
26 | */ | |
27 | DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 | |
28 | DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 | |
29 | DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 | |
30 | DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 | |
31 | DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 | |
32 | DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 | |
33 | DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 | |
34 | DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 | |
35 | ||
36 | DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 | |
37 | DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 | |
38 | DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 | |
39 | DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 | |
40 | DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 | |
41 | DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 | |
42 | DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 | |
43 | DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 | |
44 | DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 | |
45 | /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ | |
46 | DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 | |
47 | ||
48 | DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 | |
49 | DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 | |
50 | DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 | |
51 | DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 | |
52 | DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 | |
53 | DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 | |
54 | DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 | |
55 | DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 | |
56 | ||
57 | DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 | |
58 | DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 | |
59 | DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 | |
60 | DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 | |
61 | ||
62 | DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 | |
63 | DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 | |
64 | DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 | |
65 | ||
66 | DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 | |
67 | DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 | |
68 | ||
69 | /* (differential input) */ | |
70 | DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 | |
71 | /* (differential input) */ | |
72 | DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 | |
73 | /* disable ddr pullups */ | |
74 | DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 | |
75 | DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 | |
76 | /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ | |
77 | DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 | |
78 | ||
79 | /* Read data DQ Byte0-3 delay */ | |
80 | DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 | |
81 | DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 | |
82 | DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 | |
83 | DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 | |
84 | DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 | |
85 | DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 | |
86 | DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 | |
87 | DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 | |
88 | ||
89 | /* | |
90 | * MDMISC mirroring interleaved (row/bank/col) | |
91 | */ | |
92 | DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 | |
93 | ||
94 | /* | |
95 | * MDSCR con_req | |
96 | */ | |
97 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |