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[thirdparty/u-boot.git] / board / toradex / colibri_imx7 / colibri_imx7.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
ae440ab0
SA		 2/*
3 * Copyright (C) 2016 Toradex AG
ae440ab0
SA		 4 */
5
6#include <asm/arch/clock.h>
7#include <asm/arch/crm_regs.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/mx7-pins.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/gpio.h>
552a848e
SB		 12#include <asm/mach-imx/boot_mode.h>
13#include <asm/mach-imx/iomux-v3.h>
ae440ab0
SA		 14#include <asm/io.h>
15#include <common.h>
16#include <dm.h>
17#include <dm/platform_data/serial_mxc.h>
64095704 18#include <fdt_support.h>
ae440ab0 19#include <fsl_esdhc.h>
64095704 20#include <jffs2/load_kernel.h>
ae440ab0
SA		 21#include <linux/sizes.h>
22#include <mmc.h>
23#include <miiphy.h>
64095704 24#include <mtd_node.h>
ae440ab0 25#include <netdev.h>
02ad90ec
SA		 26#include <power/pmic.h>
27#include <power/rn5t567_pmic.h>
5a986dfe 28#include <usb.h>
ae440ab0 29#include <usb/ehci-ci.h>
37fa4125 30#include "../common/tdx-common.h"
ae440ab0
SA		 31
32DECLARE_GLOBAL_DATA_PTR;
33
34#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
35 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
36
37#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
38 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
39
40#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
41#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
42
43#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
44
ae440ab0
SA		 45#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
46 PAD_CTL_DSE_3P3V_49OHM)
47
48#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
49
50#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
51
5a986dfe
SA		 52#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
53
ae440ab0
SA		 54int dram_init(void)
55{
56 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
57
58 return 0;
59}
60
61static iomux_v3_cfg_t const uart1_pads[] = {
62 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
63 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
66};
67
68static iomux_v3_cfg_t const usdhc1_pads[] = {
69 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75
76 MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
77};
78
5a986dfe
SA		 79#ifdef CONFIG_USB_EHCI_MX7
80static iomux_v3_cfg_t const usb_cdet_pads[] = {
81 MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
82};
83#endif
84
ae440ab0
SA		 85#ifdef CONFIG_NAND_MXS
86static iomux_v3_cfg_t const gpmi_pads[] = {
87 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
88 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
89 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
90 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
91 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
92 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
93 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
94 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
95 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
96 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
97 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
98 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
99 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
100 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
101 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
102};
103
104static void setup_gpmi_nand(void)
105{
106 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
107
108 /* NAND_USDHC_BUS_CLK is set in rom */
109 set_clk_nand();
110}
111#endif
112
ae440ab0
SA		 113#ifdef CONFIG_VIDEO_MXS
114static iomux_v3_cfg_t const lcd_pads[] = {
115 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
116 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
117 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
122 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
123 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
125 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
126 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
127 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
128 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
129 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
130 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
131 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
132 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137};
138
139static iomux_v3_cfg_t const backlight_pads[] = {
140 /* Backlight On */
141 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
142 /* Backlight PWM<A> (multiplexed pin) */
143 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
145};
146
147#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
148#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
149
150static int setup_lcd(void)
151{
152 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
153
154 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
155
156 /* Set BL_ON */
157 gpio_request(GPIO_BL_ON, "BL_ON");
158 gpio_direction_output(GPIO_BL_ON, 1);
159
160 /* Set PWM<A> to full brightness (assuming inversed polarity) */
161 gpio_request(GPIO_PWM_A, "PWM<A>");
162 gpio_direction_output(GPIO_PWM_A, 0);
163
164 return 0;
165}
166#endif
167
168#ifdef CONFIG_FEC_MXC
169static iomux_v3_cfg_t const fec1_pads[] = {
170#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
171 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
172#else
173 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
174#endif
175 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
176 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
177 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
178 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
179 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
180 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
181 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
182 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
183 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
184};
185
186static void setup_iomux_fec(void)
187{
188 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
189}
190#endif
191
192static void setup_iomux_uart(void)
193{
194 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
195}
196
197#ifdef CONFIG_FSL_ESDHC
198
199#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
200
201static struct fsl_esdhc_cfg usdhc_cfg[] = {
202 {USDHC1_BASE_ADDR, 0, 4},
203};
204
205int board_mmc_getcd(struct mmc *mmc)
206{
207 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
208 int ret = 0;
209
210 switch (cfg->esdhc_base) {
211 case USDHC1_BASE_ADDR:
212 ret = !gpio_get_value(USDHC1_CD_GPIO);
213 break;
214 }
215
216 return ret;
217}
218
219int board_mmc_init(bd_t *bis)
220{
221 int i, ret;
222 /* USDHC1 is mmc0 */
223 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
224 switch (i) {
225 case 0:
226 imx_iomux_v3_setup_multiple_pads(
227 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
228 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
229 gpio_direction_input(USDHC1_CD_GPIO);
230 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
231 break;
232 default:
233 printf("Warning: you configured more USDHC controllers"
234 "(%d) than supported by the board\n", i + 1);
235 return -EINVAL;
236 }
237
238 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
239 if (ret)
240 return ret;
241 }
242
243 return 0;
244}
245#endif
246
247#ifdef CONFIG_FEC_MXC
248int board_eth_init(bd_t *bis)
249{
250 int ret;
251
252 setup_iomux_fec();
253
254 ret = fecmxc_initialize_multi(bis, 0,
255 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
256 if (ret)
257 printf("FEC1 MXC: %s:failed\n", __func__);
258
259 return ret;
260}
261
262static int setup_fec(void)
263{
264 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
265 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
266
267#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
268 /*
269 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
270 * and output it on the pin
271 */
272 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
273 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
274 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
275#else
276 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
277 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
278 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
279 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
280#endif
281
8590786a 282 return set_clk_enet(ENET_50MHZ);
ae440ab0
SA		 283}
284
285int board_phy_config(struct phy_device *phydev)
286{
287 if (phydev->drv->config)
288 phydev->drv->config(phydev);
289 return 0;
290}
291#endif
292
293int board_early_init_f(void)
294{
295 setup_iomux_uart();
296
ae440ab0
SA		 297 return 0;
298}
299
300int board_init(void)
301{
302 /* address of boot parameters */
303 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
304
305#ifdef CONFIG_FEC_MXC
306 setup_fec();
307#endif
308
309#ifdef CONFIG_NAND_MXS
310 setup_gpmi_nand();
311#endif
312
313#ifdef CONFIG_VIDEO_MXS
314 setup_lcd();
315#endif
316
5a986dfe
SA		 317#ifdef CONFIG_USB_EHCI_MX7
318 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
319 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
320#endif
321
ae440ab0
SA		 322 return 0;
323}
324
325#ifdef CONFIG_CMD_BMODE
326static const struct boot_mode board_boot_modes[] = {
327 /* 4 bit bus width */
328 {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
329 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
330 {NULL, 0},
331};
332#endif
333
334int board_late_init(void)
335{
336#ifdef CONFIG_CMD_BMODE
337 add_board_boot_modes(board_boot_modes);
338#endif
339
340 return 0;
341}
342
02ad90ec
SA		 343#ifdef CONFIG_DM_PMIC
344int power_init_board(void)
345{
346 struct udevice *dev;
347 int reg, ver;
348 int ret;
349
350
351 ret = pmic_get("rn5t567", &dev);
352 if (ret)
353 return ret;
354 ver = pmic_reg_read(dev, RN5T567_LSIVER);
355 reg = pmic_reg_read(dev, RN5T567_OTPVER);
356
357 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
358
359 /* set judge and press timer of N_OE to minimal values */
360 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
361
05ed964d
SA		 362 /* configure sleep slot for 3.3V Ethernet */
363 reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
364 reg = (reg & 0xf0) | reg >> 4;
365 pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
366
367 /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
368 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
369
370 /* configure sleep slot for ARM rail */
371 reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
372 reg = (reg & 0xf0) | reg >> 4;
373 pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
374
375 /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
376 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
377
02ad90ec
SA		 378 return 0;
379}
380
381void reset_cpu(ulong addr)
382{
383 struct udevice *dev;
384
385 pmic_get("rn5t567", &dev);
386
387 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
388 pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
389 pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
390
391 /*
392 * Re-power factor detection on PMIC side is not instant. 1ms
393 * proved to be enough time until reset takes effect.
394 */
395 mdelay(1);
396}
397#endif
398
ae440ab0
SA		 399int checkboard(void)
400{
401 printf("Model: Toradex Colibri iMX7%c\n",
402 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
403
404 return 0;
405}
406
37fa4125
SA		 407#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
408int ft_board_setup(void *blob, bd_t *bd)
409{
64095704
SA		 410#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
411 static struct node_info nodes[] = {
412 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
413 };
414
415 /* Update partition nodes using info from mtdparts env var */
416 puts(" Updating MTD partitions...\n");
417 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
418#endif
419
37fa4125
SA		 420 return ft_common_board_setup(blob, bd);
421}
422#endif
423
ae440ab0
SA		 424#ifdef CONFIG_USB_EHCI_MX7
425static iomux_v3_cfg_t const usb_otg2_pads[] = {
426 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
427};
428
429int board_ehci_hcd_init(int port)
430{
431 switch (port) {
432 case 0:
433 break;
434 case 1:
435 if (is_cpu_type(MXC_CPU_MX7S))
436 return -ENODEV;
437
438 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
439 ARRAY_SIZE(usb_otg2_pads));
440 break;
441 default:
442 return -EINVAL;
443 }
444 return 0;
445}
5a986dfe
SA		 446
447int board_usb_phy_mode(int port)
448{
449 switch (port) {
450 case 0:
451 if (gpio_get_value(USB_CDET_GPIO))
452 return USB_INIT_DEVICE;
453 else
454 return USB_INIT_HOST;
455 case 1:
456 default:
457 return USB_INIT_HOST;
458 }
459}
ae440ab0 460#endif
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