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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
ae440ab0 SA |
2 | /* |
3 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
4 | * 2015 Toradex AG | |
5 | * | |
03bf9d58 | 6 | * Refer doc/README.imximage for more details about how-to configure |
ae440ab0 SA |
7 | * and create imximage boot image |
8 | * | |
9 | * The syntax is taken as close as possible with the kwbimage | |
10 | */ | |
11 | ||
12 | #define __ASSEMBLY__ | |
13 | #include <config.h> | |
14 | ||
15 | /* image version */ | |
16 | ||
17 | IMAGE_VERSION 2 | |
18 | ||
19 | /* | |
20 | * Boot Device : sd | |
21 | */ | |
22 | ||
23 | BOOT_FROM sd | |
24 | ||
25 | /* | |
26 | * Secure boot support | |
27 | */ | |
28 | #ifdef CONFIG_SECURE_BOOT | |
29 | CSF CONFIG_CSF_SIZE | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * Device Configuration Data (DCD) | |
34 | * | |
35 | * Each entry must have the format: | |
36 | * Addr-type Address Value | |
37 | * | |
38 | * where: | |
39 | * Addr-type register length (1,2 or 4 bytes) | |
40 | * Address absolute address of the register | |
41 | * value value to be stored in the register | |
42 | */ | |
43 | ||
44 | /* IOMUXC_GPR_GPR1 */ | |
45 | DATA 4 0x30340004 0x4F400005 | |
46 | ||
47 | /* DDR3L */ | |
48 | /* assuming MEMC_FREQ_RATIO = 2 */ | |
49 | /* SRC_DDRC_RCR */ | |
50 | DATA 4 0x30391000 0x00000002 | |
51 | /* DDRC_MSTR */ | |
52 | DATA 4 0x307a0000 0x01040001 | |
53 | /* DDRC_DFIUPD0 */ | |
54 | DATA 4 0x307a01a0 0x80400003 | |
55 | /* DDRC_DFIUPD1 */ | |
56 | DATA 4 0x307a01a4 0x00100020 | |
57 | /* DDRC_DFIUPD2 */ | |
58 | DATA 4 0x307a01a8 0x80100004 | |
59 | /* DDRC_RFSHTMG */ | |
60 | DATA 4 0x307a0064 0x00400045 | |
61 | /* DDRC_MP_PCTRL_0 */ | |
62 | DATA 4 0x307a0490 0x00000001 | |
63 | /* DDRC_INIT0 */ | |
64 | DATA 4 0x307a00d0 0x00020083 | |
65 | /* DDRC_INIT1 */ | |
66 | DATA 4 0x307a00d4 0x00690000 | |
67 | /* DDRC_INIT3 MR0/MR1 */ | |
68 | DATA 4 0x307a00dc 0x09300004 | |
69 | /* DDRC_INIT4 MR2/MR3 */ | |
70 | DATA 4 0x307a00e0 0x04480000 | |
71 | /* DDRC_INIT5 */ | |
72 | DATA 4 0x307a00e4 0x00100004 | |
73 | /* DDRC_RANKCTL */ | |
74 | DATA 4 0x307a00f4 0x0000033f | |
75 | /* DDRC_DRAMTMG0 */ | |
76 | DATA 4 0x307a0100 0x090b090a | |
77 | /* DDRC_DRAMTMG1 */ | |
78 | DATA 4 0x307a0104 0x000d020d | |
79 | /* DDRC_DRAMTMG2 */ | |
80 | DATA 4 0x307a0108 0x03040307 | |
81 | /* DDRC_DRAMTMG3 */ | |
82 | DATA 4 0x307a010c 0x00002006 | |
83 | /* DDRC_DRAMTMG4 */ | |
84 | DATA 4 0x307a0110 0x04020205 | |
85 | /* DDRC_DRAMTMG5 */ | |
86 | DATA 4 0x307a0114 0x03030202 | |
87 | /* DDRC_DRAMTMG8 */ | |
88 | DATA 4 0x307a0120 0x00000803 | |
89 | /* DDRC_ZQCTL0 */ | |
90 | DATA 4 0x307a0180 0x00800020 | |
91 | /* DDRC_ZQCTL1 */ | |
92 | DATA 4 0x307a0184 0x02001000 | |
93 | /* DDRC_DFITMG0 */ | |
94 | DATA 4 0x307a0190 0x02098204 | |
95 | /* DDRC_DFITMG1 */ | |
96 | DATA 4 0x307a0194 0x00030303 | |
97 | /* DDRC_ADDRMAP0 */ | |
98 | DATA 4 0x307a0200 0x0000001f | |
99 | /* DDRC_ADDRMAP1 */ | |
100 | DATA 4 0x307a0204 0x00080808 | |
101 | /* DDRC_ADDRMAP5 */ | |
102 | DATA 4 0x307a0214 0x07070707 | |
103 | /* DDRC_ADDRMAP6 */ | |
104 | DATA 4 0x307a0218 0x07070707 | |
105 | /* DDRC_ODTCFG */ | |
106 | DATA 4 0x307a0240 0x06000601 | |
107 | /* DDRC_ODTMAP */ | |
108 | DATA 4 0x307a0244 0x00000011 | |
109 | /* SRC_DDRC_RCR */ | |
110 | DATA 4 0x30391000 0x00000000 | |
111 | /* DDR_PHY_PHY_CON0 */ | |
112 | DATA 4 0x30790000 0x17420f40 | |
113 | /* DDR_PHY_PHY_CON1 */ | |
114 | DATA 4 0x30790004 0x10210100 | |
115 | /* DDR_PHY_PHY_CON4 */ | |
116 | DATA 4 0x30790010 0x00060807 | |
117 | /* DDR_PHY_MDLL_CON0 */ | |
118 | DATA 4 0x307900b0 0x1010007e | |
119 | /* DDR_PHY_DRVDS_CON0 */ | |
120 | DATA 4 0x3079009c 0x00000d6e | |
121 | /* DDR_PHY_OFFSET_RD_CON0 */ | |
122 | DATA 4 0x30790020 0x08080808 | |
123 | /* DDR_PHY_OFFSET_WR_CON0 */ | |
124 | DATA 4 0x30790030 0x08080808 | |
125 | /* DDR_PHY_CMD_SDLL_CON0 */ | |
126 | DATA 4 0x30790050 0x01000010 | |
127 | DATA 4 0x30790050 0x00000010 | |
128 | ||
129 | /* DDR_PHY_ZQ_CON0 */ | |
130 | DATA 4 0x307900c0 0x0e407304 | |
131 | DATA 4 0x307900c0 0x0e447304 | |
132 | DATA 4 0x307900c0 0x0e447306 | |
133 | /* DDR_PHY_ZQ_CON1 */ | |
134 | CHECK_BITS_SET 4 0x307900c4 0x1 | |
135 | /* DDR_PHY_ZQ_CON0 */ | |
136 | DATA 4 0x307900c0 0x0e447304 | |
137 | DATA 4 0x307900c0 0x0e407304 | |
138 | ||
139 | /* CCM_CCGRn */ | |
140 | DATA 4 0x30384130 0x00000000 | |
141 | /* IOMUXC_GPR_GPR8 */ | |
142 | DATA 4 0x30340020 0x00000178 | |
143 | /* CCM_CCGRn */ | |
144 | DATA 4 0x30384130 0x00000002 | |
145 | /* DDR_PHY_LP_CON0 */ | |
146 | DATA 4 0x30790018 0x0000000f | |
147 | ||
148 | /* DDRC_STAT */ | |
149 | CHECK_BITS_SET 4 0x307a0004 0x1 |