[people/ms/u-boot.git] / board / toradex / colibri_pxa270 / colibri_pxa270.c

/*
 * Toradex Colibri PXA270 Support
 *
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/regs-mmc.h>
#include <asm/arch/pxa.h>
#include <netdev.h>
#include <asm/io.h>
#include <serial.h>
#include <usb.h>

DECLARE_GLOBAL_DATA_PTR;

int board_init(void)
{
	/* We have RAM, disable cache */
	dcache_disable();
	icache_disable();

	/* arch number of vpac270 */
	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0xa0000100;

	return 0;
}

int dram_init(void)
{
	pxa2xx_dram_init();
	gd->ram_size = PHYS_SDRAM_1_SIZE;
	return 0;
}

#ifdef	CONFIG_CMD_USB
int board_usb_init(int index, enum usb_init_type init)
{
	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
		UHCHR);

	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);

	while (UHCHR & UHCHR_FSBIR)
		;

	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);

	/* Clear any OTG Pin Hold */
	if (readl(PSSR) & PSSR_OTGPH)
		writel(readl(PSSR) | PSSR_OTGPH, PSSR);

	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
	writel(readl(UHCRHDA) | 0x100, UHCRHDA);

	/* Set port power control mask bits, only 3 ports. */
	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);

	/* enable port 2 */
	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	return 0;
}

void usb_board_stop(void)
{
	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
	udelay(11);
	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);

	writel(readl(UHCCOMS) | 1, UHCCOMS);
	udelay(10);

	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);

	return;
}
#endif

#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
	return dm9000_initialize(bis);
}
#endif

#ifdef	CONFIG_CMD_MMC
int board_mmc_init(bd_t *bis)
{
	pxa_mmc_register(0);
	return 0;
}
#endif
Commit	Line	Data
2e49984b MV	1	/*
	2	* Toradex Colibri PXA270 Support
	3	*
	4	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
2e49984b MV	7	*/
	8
	9	#include <common.h>
	10	#include <asm/arch/hardware.h>
f9f5486c	11	#include <asm/arch/regs-mmc.h>
4438a45f	12	#include <asm/arch/pxa.h>
c7e61334	13	#include <netdev.h>
3ba8bf7c	14	#include <asm/io.h>
f9f5486c	15	#include <serial.h>
16297cfb	16	#include <usb.h>
2e49984b MV	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
f9f5486c	20	int board_init(void)
2e49984b	21	{
d94bbbeb MV	22	/* We have RAM, disable cache */
	23	dcache_disable();
	24	icache_disable();
2e49984b MV	25
	26	/* arch number of vpac270 */
	27	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
	28
	29	/* adress of boot parameters */
	30	gd->bd->bi_boot_params = 0xa0000100;
	31
	32	return 0;
	33	}
	34
d94bbbeb	35	int dram_init(void)
2e49984b	36	{
f68d2a22	37	pxa2xx_dram_init();
d94bbbeb MV	38	gd->ram_size = PHYS_SDRAM_1_SIZE;
	39	return 0;
	40	}
2e49984b	41
2e49984b	42	#ifdef CONFIG_CMD_USB
bba67914	43	int board_usb_init(int index, enum usb_init_type init)
2e49984b	44	{
3ba8bf7c MV	45	writel((readl(UHCHR) \| UHCHR_PCPL \| UHCHR_PSPL) &
	46	~(UHCHR_SSEP0 \| UHCHR_SSEP1 \| UHCHR_SSEP2 \| UHCHR_SSE),
	47	UHCHR);
2e49984b	48
3ba8bf7c	49	writel(readl(UHCHR) \| UHCHR_FSBIR, UHCHR);
2e49984b	50
f9f5486c MV	51	while (UHCHR & UHCHR_FSBIR)
f9f5486c MV	52	;
2e49984b	53
3ba8bf7c MV	54	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
3ba8bf7c MV	55	writel((UHCHIE_UPRIE \| UHCHIE_RWIE), UHCHIE);
2e49984b MV	56
2e49984b MV	57	/* Clear any OTG Pin Hold */
3ba8bf7c MV	58	if (readl(PSSR) & PSSR_OTGPH)
3ba8bf7c MV	59	writel(readl(PSSR) \| PSSR_OTGPH, PSSR);
2e49984b	60
3ba8bf7c MV	61	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
3ba8bf7c MV	62	writel(readl(UHCRHDA) \| 0x100, UHCRHDA);
2e49984b MV	63
2e49984b MV	64	/* Set port power control mask bits, only 3 ports. */
3ba8bf7c	65	writel(readl(UHCRHDB) \| (0x7<<17), UHCRHDB);
2e49984b MV	66
2e49984b MV	67	/* enable port 2 */
3ba8bf7c MV	68	writel(readl(UP2OCR) \| UP2OCR_HXOE \| UP2OCR_HXS \|
3ba8bf7c MV	69	UP2OCR_DMPDE \| UP2OCR_DPPDE, UP2OCR);
2e49984b MV	70
	71	return 0;
	72	}
	73
bba67914	74	int board_usb_cleanup(int index, enum usb_init_type init)
2e49984b	75	{
16297cfb	76	return 0;
2e49984b MV	77	}
	78
	79	void usb_board_stop(void)
	80	{
3ba8bf7c	81	writel(readl(UHCHR) \| UHCHR_FHR, UHCHR);
2e49984b	82	udelay(11);
3ba8bf7c	83	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
2e49984b	84
3ba8bf7c	85	writel(readl(UHCCOMS) \| 1, UHCCOMS);
2e49984b MV	86	udelay(10);
2e49984b MV	87
3ba8bf7c	88	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
2e49984b MV	89
	90	return;
	91	}
	92	#endif
	93
	94	#ifdef CONFIG_DRIVER_DM9000
	95	int board_eth_init(bd_t *bis)
	96	{
	97	return dm9000_initialize(bis);
	98	}
	99	#endif
f9f5486c MV	100
	101	#ifdef CONFIG_CMD_MMC
	102	int board_mmc_init(bd_t *bis)
	103	{
	104	pxa_mmc_register(0);
	105	return 0;
	106	}
	107	#endif