[thirdparty/u-boot.git] / board / toradex / verdin-imx8mm / spl.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2020 Toradex
 */

#include <common.h>
#include <image.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <cpu_func.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <hang.h>
#include <power/bd71837.h>
#include <power/pmic.h>
#include <spl.h>

DECLARE_GLOBAL_DATA_PTR;

int spl_board_boot_device(enum boot_device boot_dev_spl)
{
	switch (boot_dev_spl) {
	case MMC1_BOOT:
		return BOOT_DEVICE_MMC1;
	case SD2_BOOT:
	case MMC2_BOOT:
		return BOOT_DEVICE_MMC2;
	case SD3_BOOT:
	case MMC3_BOOT:
		return BOOT_DEVICE_MMC1;
	case USB_BOOT:
		return BOOT_DEVICE_BOARD;
	default:
		return BOOT_DEVICE_NONE;
	}
}

void spl_dram_init(void)
{
	ddr_init(&dram_timing);
}

void spl_board_init(void)
{
	/* Serial download mode */
	if (is_usb_boot()) {
		puts("Back to ROM, SDP\n");
		restore_boot_params();
	}
	puts("Normal Boot\n");
}

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	/* Just empty function now - can't decide what to choose */
	debug("%s: %s\n", __func__, name);

	return 0;
}
#endif

#define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

/* Verdin UART_3, Console/Debug UART */
static iomux_v3_cfg_t const uart_pads[] = {
	IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const wdog_pads[] = {
	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};

int board_early_init_f(void)
{
	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

	set_wdog_reset(wdog);

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));

	return 0;
}

int power_init_board(void)
{
	struct udevice *dev;
	int ret;

	ret = pmic_get("pmic@4b", &dev);
	if (ret == -ENODEV) {
		puts("No pmic\n");
		return 0;
	}
	if (ret != 0)
		return ret;

	/* decrease RESET key long push time from the default 10s to 10ms */
	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);

	/* unlock the PMIC regs */
	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);

	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);

	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);

#ifndef CONFIG_IMX8M_LPDDR4
	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
#endif

	/* lock the PMIC regs */
	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);

	return 0;
}

void board_init_f(ulong dummy)
{
	struct udevice *dev;
	int ret;

	arch_cpu_init();

	init_uart_clk(0);

	board_early_init_f();

	timer_init();

	preloader_console_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	ret = spl_early_init();
	if (ret) {
		debug("spl_early_init() failed: %d\n", ret);
		hang();
	}

	ret = uclass_get_device_by_name(UCLASS_CLK,
					"clock-controller@30380000",
					&dev);
	if (ret < 0) {
		printf("Failed to find clock node. Check device tree\n");
		hang();
	}

	enable_tzc380();

	power_init_board();

	/* DDR initialization */
	spl_dram_init();

	board_init_r(NULL, 0);
}
Commit	Line	Data
14d5aeff IO	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2020 Toradex
	4	*/
	5
	6	#include <common.h>
4d72caa5	7	#include <image.h>
14d5aeff IO	8	#include <asm/arch/clock.h>
	9	#include <asm/arch/ddr.h>
	10	#include <asm/arch/imx8mm_pins.h>
	11	#include <asm/arch/sys_proto.h>
	12	#include <asm/io.h>
	13	#include <asm/mach-imx/boot_mode.h>
	14	#include <asm/mach-imx/iomux-v3.h>
	15	#include <cpu_func.h>
	16	#include <dm/device.h>
	17	#include <dm/device-internal.h>
	18	#include <dm/uclass.h>
	19	#include <dm/uclass-internal.h>
	20	#include <hang.h>
	21	#include <power/bd71837.h>
	22	#include <power/pmic.h>
	23	#include <spl.h>
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	int spl_board_boot_device(enum boot_device boot_dev_spl)
	28	{
	29	switch (boot_dev_spl) {
	30	case MMC1_BOOT:
	31	return BOOT_DEVICE_MMC1;
	32	case SD2_BOOT:
	33	case MMC2_BOOT:
	34	return BOOT_DEVICE_MMC2;
	35	case SD3_BOOT:
	36	case MMC3_BOOT:
	37	return BOOT_DEVICE_MMC1;
	38	case USB_BOOT:
	39	return BOOT_DEVICE_BOARD;
	40	default:
	41	return BOOT_DEVICE_NONE;
	42	}
	43	}
	44
	45	void spl_dram_init(void)
	46	{
	47	ddr_init(&dram_timing);
	48	}
	49
	50	void spl_board_init(void)
	51	{
	52	/* Serial download mode */
	53	if (is_usb_boot()) {
	54	puts("Back to ROM, SDP\n");
	55	restore_boot_params();
	56	}
	57	puts("Normal Boot\n");
	58	}
	59
	60	#ifdef CONFIG_SPL_LOAD_FIT
	61	int board_fit_config_name_match(const char *name)
	62	{
	63	/* Just empty function now - can't decide what to choose */
	64	debug("%s: %s\n", __func__, name);
	65
	66	return 0;
	67	}
	68	#endif
	69
	70	#define UART_PAD_CTRL (PAD_CTL_PUE \| PAD_CTL_PE \| PAD_CTL_DSE4)
	71	#define WDOG_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_ODE \| PAD_CTL_PUE \| PAD_CTL_PE)
72
73	/* Verdin UART_3, Console/Debug UART */
74	static iomux_v3_cfg_t const uart_pads[] = {
75	IMX8MM_PAD_SAI2_RXFS_UART1_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
76	IMX8MM_PAD_SAI2_RXC_UART1_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
77	};
78
79	static iomux_v3_cfg_t const wdog_pads[] = {
80	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B \| MUX_PAD_CTRL(WDOG_PAD_CTRL),
81	};
82
83	int board_early_init_f(void)
84	{
85	struct wdog_regs wdog = (struct wdog_regs )WDOG1_BASE_ADDR;
86
87	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
88
89	set_wdog_reset(wdog);
90
91	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
92
93	return 0;
94	}
95
96	int power_init_board(void)
97	{
98	struct udevice *dev;
99	int ret;
100
101	ret = pmic_get("pmic@4b", &dev);
102	if (ret == -ENODEV) {
103	puts("No pmic\n");
104	return 0;
105	}
106	if (ret != 0)
107	return ret;
108
109	/* decrease RESET key long push time from the default 10s to 10ms */
110	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
111
112	/* unlock the PMIC regs */
113	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
114
115	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
116	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
117
118	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
119	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
120
121	#ifndef CONFIG_IMX8M_LPDDR4
122	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
123	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
124	#endif
125
126	/* lock the PMIC regs */
127	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
128
129	return 0;
130	}
131
132	void board_init_f(ulong dummy)
133	{
134	struct udevice *dev;
135	int ret;
136
137	arch_cpu_init();
138
139	init_uart_clk(0);
140
141	board_early_init_f();
142
143	timer_init();
144
145	preloader_console_init();
146
147	/* Clear the BSS. */
148	memset(__bss_start, 0, __bss_end - __bss_start);
149
150	ret = spl_early_init();
151	if (ret) {
152	debug("spl_early_init() failed: %d\n", ret);
153	hang();
154	}
155
156	ret = uclass_get_device_by_name(UCLASS_CLK,
157	"clock-controller@30380000",
158	&dev);
159	if (ret < 0) {
160	printf("Failed to find clock node. Check device tree\n");
161	hang();
162	}
163
164	enable_tzc380();
165
166	power_init_board();
167
168	/* DDR initialization */
169	spl_dram_init();
170
171	board_init_r(NULL, 0);
172	}