[people/ms/u-boot.git] / board / tqc / tqm85xx / sdram.c

/*
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>

struct sdram_conf_s {
	unsigned long size;
	unsigned long reg;
#ifdef CONFIG_TQM8548
	unsigned long refresh;
#endif /* CONFIG_TQM8548 */
};

typedef struct sdram_conf_s sdram_conf_t;

#ifdef CONFIG_TQM8548
sdram_conf_t ddr_cs_conf[] = {
	{(512 << 20), 0x80044102, 0x0001A000},	/* 512MB, 13x10(4)	*/
	{(256 << 20), 0x80040102, 0x00014000},	/* 256MB, 13x10(4)	*/
	{(128 << 20), 0x80040101, 0x0000C000},	/* 128MB, 13x9(4)	*/
};
#else /* !CONFIG_TQM8548 */
sdram_conf_t ddr_cs_conf[] = {
	{(512 << 20), 0x80000202},	/* 512MB, 14x10(4)	*/
	{(256 << 20), 0x80000102},	/* 256MB, 13x10(4)	*/
	{(128 << 20), 0x80000101},	/* 128MB, 13x9(4)	*/
	{( 64 << 20), 0x80000001},	/*  64MB, 12x9(4)	*/
};
#endif /* CONFIG_TQM8548 */

#define	N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))

int cas_latency (void);

/*
 * Autodetect onboard DDR SDRAM on 85xx platforms
 *
 * NOTE: Some of the hardcoded values are hardware dependant,
 *       so this should be extended for other future boards
 *       using this routine!
 */
long int sdram_setup (int casl)
{
	int i;
	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#ifdef CONFIG_TQM8548
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#else /* !CONFIG_TQM8548 */
	unsigned long cfg_ddr_timing1;
	unsigned long cfg_ddr_mode;
#endif /* CONFIG_TQM8548 */

	/*
	 * Disable memory controller.
	 */
	ddr->cs0_config = 0;
	ddr->sdram_cfg = 0;

#ifdef CONFIG_TQM8548
	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
	ddr->cs0_config = ddr_cs_conf[0].reg;
	ddr->timing_cfg_3 = 0x00010000;

	/* TIMING CFG 1, 533MHz
	 * PRETOACT: 4 Clocks
	 * ACTTOPRE: 12 Clocks
	 * ACTTORW:  4 Clocks
	 * CASLAT:   4 Clocks
	 * REFREC:   34 Clocks
	 * WRREC:    4 Clocks
	 * ACTTOACT: 3 Clocks
	 * WRTORD:   2 Clocks
	 */
	ddr->timing_cfg_1 = 0x4C47A432;

	/* TIMING CFG 2, 533MHz
	 * ADD_LAT:       3 Clocks
	 * CPO:           READLAT + 1
	 * WR_LAT:        3 Clocks
	 * RD_TO_PRE:     2 Clocks
	 * WR_DATA_DELAY: 1/2 Clock
	 * CKE_PLS:       1 Clock
	 * FOUR_ACT:      13 Clocks
	 */
	ddr->timing_cfg_2 = 0x3318484D;

	/* DDR SDRAM Mode, 533MHz
	 * MRS:          Extended Mode Register
	 * OUT:          Outputs enabled
	 * RDQS:         no
	 * DQS:          enabled
	 * OCD:          default state
	 * RTT:          75 Ohms
	 * Posted CAS:   3 Clocks
	 * ODS:          reduced strength
	 * DLL:          enabled
	 * MR:           Mode Register
	 * PD:           fast exit
	 * WR:           4 Clocks
	 * DLL:          no DLL reset
	 * TM:           normal
	 * CAS latency:  4 Clocks
	 * BT:           sequential
	 * Burst length: 4
	 */
	ddr->sdram_mode = 0x439E0642;

	/* DDR SDRAM Interval, 533MHz
	 * REFINT:  1040 Clocks
	 * BSTOPRE: 256
	 */
	ddr->sdram_interval = (1040 << 16) | 0x100;

	/*
	 * workaround for erratum DD10 of MPC8458 family below rev. 2.0:
	 * DDR IO receiver must be set to an acceptable bias point by modifying
	 * a hidden register.
	 */
	if (SVR_REV (get_svr ()) < 0x20) {
		gur->ddrioovcr = 0x90000000;	/* enable, VSEL 1.8V */
	}

	/* DDR SDRAM CFG 2
	 * FRC_SR:      normal mode
	 * SR_IE:       no self-refresh interrupt
	 * DLL_RST_DIS: don't care, leave at reset value
	 * DQS_CFG:     differential DQS signals
	 * ODT_CFG:     assert ODT to internal IOs only during reads to DRAM
	 * LVWx_CFG:    don't care, leave at reset value
	 * NUM_PR:      1 refresh will be issued at a time
	 * DM_CFG:      don't care, leave at reset value
	 * D_INIT:      no data initialization
	 */
	ddr->sdram_cfg_2 = 0x04401000;

	/* DDR SDRAM MODE 2
	 * MRS: Extended Mode Register 2
	 */
	ddr->sdram_mode_2 = 0x8000C000;

	/* DDR SDRAM CLK CNTL
	 * CLK_ADJUST: 1/2 Clock 0x02000000
	 * CLK_ADJUST: 5/8 Clock 0x02800000
	 */
	ddr->sdram_clk_cntl = 0x02800000;

	/* wait for clock stabilization */
	asm ("sync;isync;msync");
	udelay(1000);

	/* DDR SDRAM CLK CNTL
	 * MEM_EN:       enabled
	 * SREN:         don't care, leave at reset value
	 * ECC_EN:       no error report
	 * RD_EN:        no register DIMMs
	 * SDRAM_TYPE:   DDR2
	 * DYN_PWR:      no power management
	 * 32_BE:        don't care, leave at reset value
	 * 8_BE:         4 beat burst
	 * NCAP:         don't care, leave at reset value
	 * 2T_EN:        1T Timing
	 * BA_INTLV_CTL: no interleaving
	 * x32_EN:       x16 organization
	 * PCHB8:        MA[10] for auto-precharge
	 * HSE:          half strength for single and 2-layer stacks
	 * (full strength for 3- and 4-layer stacks no yet considered)
	 * MEM_HALT:     no halt
	 * BI:           automatic initialization
	 */
	ddr->sdram_cfg = 0x83000008;
	asm ("sync; isync; msync");
	udelay(1000);

#else /* !CONFIG_TQM8548 */
	switch (casl) {
	case 20:
		cfg_ddr_timing1 = 0x47405331 | (3 << 16);
		cfg_ddr_mode = 0x40020002 | (2 << 4);
		break;

	case 25:
		cfg_ddr_timing1 = 0x47405331 | (4 << 16);
		cfg_ddr_mode = 0x40020002 | (6 << 4);
		break;

	case 30:
	default:
		cfg_ddr_timing1 = 0x47405331 | (5 << 16);
		cfg_ddr_mode = 0x40020002 | (3 << 4);
		break;
	}

	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
	ddr->cs0_config = ddr_cs_conf[0].reg;
	ddr->timing_cfg_1 = cfg_ddr_timing1;
	ddr->timing_cfg_2 = 0x00000800;		/* P9-45,may need tuning */
	ddr->sdram_mode = cfg_ddr_mode;
	ddr->sdram_interval = 0x05160100;	/* autocharge,no open page */
	ddr->err_disable = 0x0000000D;

	asm ("sync; isync; msync");
	udelay (1000);

	ddr->sdram_cfg = 0xc2000000;		/* unbuffered,no DYN_PWR */
	asm ("sync; isync; msync");
	udelay (1000);
#endif /* CONFIG_TQM8548 */

	for (i = 0; i < N_DDR_CS_CONF; i++) {
		ddr->cs0_config = ddr_cs_conf[i].reg;

		if (get_ram_size (0, ddr_cs_conf[i].size) ==
		    ddr_cs_conf[i].size) {
			/*
			 * size detected -> set Chip Select Bounds Register
			 */
			ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;

			break;
		}
	}

#ifdef CONFIG_TQM8548
	if (i < N_DDR_CS_CONF) {
		/* Adjust refresh rate for DDR2 */

		ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;

		ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
		    (ddr_cs_conf[i].refresh & 0x0000F000);

		return ddr_cs_conf[i].size;
	}
#endif /* CONFIG_TQM8548 */

	/* return size if detected, else return 0 */
	return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}

void board_add_ram_info (int use_default)
{
	int casl;

	if (use_default)
		casl = CONFIG_DDR_DEFAULT_CL;
	else
		casl = cas_latency ();

	puts (" (CL=");
	switch (casl) {
	case 20:
		puts ("2)");
		break;

	case 25:
		puts ("2.5)");
		break;

	case 30:
		puts ("3)");
		break;
	}
}

phys_size_t initdram (int board_type)
{
	long dram_size = 0;
	int casl;

#if defined(CONFIG_DDR_DLL)
	/*
	 * This DLL-Override only used on TQM8540 and TQM8560
	 */
	{
		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
		int i, x;

		x = 10;

		/*
		 * Work around to stabilize DDR DLL
		 */
		gur->ddrdllcr = 0x81000000;
		asm ("sync; isync; msync");
		udelay (200);
		while (gur->ddrdllcr != 0x81000100) {
			gur->devdisr = gur->devdisr | 0x00010000;
			asm ("sync; isync; msync");
			for (i = 0; i < x; i++)
				;
			gur->devdisr = gur->devdisr & 0xfff7ffff;
			asm ("sync; isync; msync");
			x++;
		}
	}
#endif

	casl = cas_latency ();
	dram_size = sdram_setup (casl);
	if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
		/*
		 * Try again with default CAS latency
		 */
		puts ("Problem with CAS lantency");
		board_add_ram_info (1);
		puts (", using default CL!\n");
		casl = CONFIG_DDR_DEFAULT_CL;
		dram_size = sdram_setup (casl);
		puts ("       ");
	}

	return dram_size;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf ("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf ("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf ("SDRAM test passed.\n");
	return 0;
}
#endif
Commit	Line	Data
d96f41e0 SR	1	/*
	2	* (C) Copyright 2005
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
d96f41e0 SR	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <asm/immap_85xx.h>
	27	#include <asm/processor.h>
	28	#include <asm/mmu.h>
d96f41e0 SR	29
	30	struct sdram_conf_s {
	31	unsigned long size;
	32	unsigned long reg;
1287e0c5 WG	33	#ifdef CONFIG_TQM8548
	34	unsigned long refresh;
	35	#endif /* CONFIG_TQM8548 */
d96f41e0 SR	36	};
	37
	38	typedef struct sdram_conf_s sdram_conf_t;
	39
1287e0c5 WG	40	#ifdef CONFIG_TQM8548
	41	sdram_conf_t ddr_cs_conf[] = {
	42	{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
	43	{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
	44	{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
	45	};
	46	#else /* !CONFIG_TQM8548 */
d96f41e0 SR	47	sdram_conf_t ddr_cs_conf[] = {
	48	{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
	49	{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
	50	{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
b99ba167	51	{( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
d96f41e0	52	};
1287e0c5	53	#endif /* CONFIG_TQM8548 */
d96f41e0 SR	54
	55	#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
	56
b99ba167	57	int cas_latency (void);
d96f41e0 SR	58
	59	/*
	60	* Autodetect onboard DDR SDRAM on 85xx platforms
	61	*
	62	* NOTE: Some of the hardcoded values are hardware dependant,
	63	* so this should be extended for other future boards
	64	* using this routine!
	65	*/
b99ba167	66	long int sdram_setup (int casl)
d96f41e0 SR	67	{
d96f41e0 SR	68	int i;
6d0f6bcf	69	volatile ccsr_ddr_t ddr = (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
1287e0c5	70	#ifdef CONFIG_TQM8548
6d0f6bcf	71	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1287e0c5	72	#else /* !CONFIG_TQM8548 */
d96f41e0 SR	73	unsigned long cfg_ddr_timing1;
d96f41e0 SR	74	unsigned long cfg_ddr_mode;
1287e0c5	75	#endif /* CONFIG_TQM8548 */
d96f41e0 SR	76
	77	/*
	78	* Disable memory controller.
	79	*/
	80	ddr->cs0_config = 0;
	81	ddr->sdram_cfg = 0;
	82
1287e0c5 WG	83	#ifdef CONFIG_TQM8548
	84	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
	85	ddr->cs0_config = ddr_cs_conf[0].reg;
	86	ddr->timing_cfg_3 = 0x00010000;
	87
	88	/* TIMING CFG 1, 533MHz
	89	* PRETOACT: 4 Clocks
	90	* ACTTOPRE: 12 Clocks
	91	* ACTTORW: 4 Clocks
	92	* CASLAT: 4 Clocks
	93	* REFREC: 34 Clocks
	94	* WRREC: 4 Clocks
	95	* ACTTOACT: 3 Clocks
	96	* WRTORD: 2 Clocks
	97	*/
	98	ddr->timing_cfg_1 = 0x4C47A432;
	99
	100	/* TIMING CFG 2, 533MHz
	101	* ADD_LAT: 3 Clocks
	102	* CPO: READLAT + 1
	103	* WR_LAT: 3 Clocks
	104	* RD_TO_PRE: 2 Clocks
	105	* WR_DATA_DELAY: 1/2 Clock
	106	* CKE_PLS: 1 Clock
	107	* FOUR_ACT: 13 Clocks
	108	*/
	109	ddr->timing_cfg_2 = 0x3318484D;
	110
	111	/* DDR SDRAM Mode, 533MHz
	112	* MRS: Extended Mode Register
	113	* OUT: Outputs enabled
	114	* RDQS: no
	115	* DQS: enabled
	116	* OCD: default state
	117	* RTT: 75 Ohms
	118	* Posted CAS: 3 Clocks
	119	* ODS: reduced strength
	120	* DLL: enabled
	121	* MR: Mode Register
	122	* PD: fast exit
	123	* WR: 4 Clocks
	124	* DLL: no DLL reset
	125	* TM: normal
	126	* CAS latency: 4 Clocks
	127	* BT: sequential
	128	* Burst length: 4
	129	*/
	130	ddr->sdram_mode = 0x439E0642;
	131
	132	/* DDR SDRAM Interval, 533MHz
	133	* REFINT: 1040 Clocks
	134	* BSTOPRE: 256
	135	*/
	136	ddr->sdram_interval = (1040 << 16) \| 0x100;
	137
	138	/*
	139	* workaround for erratum DD10 of MPC8458 family below rev. 2.0:
	140	* DDR IO receiver must be set to an acceptable bias point by modifying
	141	* a hidden register.
	142	*/
	143	if (SVR_REV (get_svr ()) < 0x20) {
	144	gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
	145	}
	146
147	/* DDR SDRAM CFG 2
148	* FRC_SR: normal mode
149	* SR_IE: no self-refresh interrupt
150	* DLL_RST_DIS: don't care, leave at reset value
151	* DQS_CFG: differential DQS signals
152	* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
153	* LVWx_CFG: don't care, leave at reset value
154	* NUM_PR: 1 refresh will be issued at a time
155	* DM_CFG: don't care, leave at reset value
156	* D_INIT: no data initialization
157	*/
158	ddr->sdram_cfg_2 = 0x04401000;
159
160	/* DDR SDRAM MODE 2
161	* MRS: Extended Mode Register 2
162	*/
163	ddr->sdram_mode_2 = 0x8000C000;
164
165	/* DDR SDRAM CLK CNTL
166	* CLK_ADJUST: 1/2 Clock 0x02000000
167	* CLK_ADJUST: 5/8 Clock 0x02800000
168	*/
169	ddr->sdram_clk_cntl = 0x02800000;
170
171	/* wait for clock stabilization */
172	asm ("sync;isync;msync");
173	udelay(1000);
174
175	/* DDR SDRAM CLK CNTL
176	* MEM_EN: enabled
177	* SREN: don't care, leave at reset value
178	* ECC_EN: no error report
179	* RD_EN: no register DIMMs
180	* SDRAM_TYPE: DDR2
181	* DYN_PWR: no power management
182	* 32_BE: don't care, leave at reset value
183	* 8_BE: 4 beat burst
184	* NCAP: don't care, leave at reset value
185	* 2T_EN: 1T Timing
186	* BA_INTLV_CTL: no interleaving
187	* x32_EN: x16 organization
188	* PCHB8: MA[10] for auto-precharge
189	* HSE: half strength for single and 2-layer stacks
190	* (full strength for 3- and 4-layer stacks no yet considered)
191	* MEM_HALT: no halt
192	* BI: automatic initialization
193	*/
194	ddr->sdram_cfg = 0x83000008;
195	asm ("sync; isync; msync");
196	udelay(1000);
197
198	#else /* !CONFIG_TQM8548 */
d96f41e0 SR	199	switch (casl) {
	200	case 20:
	201	cfg_ddr_timing1 = 0x47405331 \| (3 << 16);
	202	cfg_ddr_mode = 0x40020002 \| (2 << 4);
	203	break;
	204
	205	case 25:
	206	cfg_ddr_timing1 = 0x47405331 \| (4 << 16);
	207	cfg_ddr_mode = 0x40020002 \| (6 << 4);
	208	break;
	209
	210	case 30:
	211	default:
	212	cfg_ddr_timing1 = 0x47405331 \| (5 << 16);
	213	cfg_ddr_mode = 0x40020002 \| (3 << 4);
	214	break;
	215	}
	216
	217	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
	218	ddr->cs0_config = ddr_cs_conf[0].reg;
	219	ddr->timing_cfg_1 = cfg_ddr_timing1;
	220	ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
	221	ddr->sdram_mode = cfg_ddr_mode;
	222	ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
	223	ddr->err_disable = 0x0000000D;
	224
b99ba167 WG	225	asm ("sync; isync; msync");
b99ba167 WG	226	udelay (1000);
d96f41e0 SR	227
	228	ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
	229	asm ("sync; isync; msync");
b99ba167	230	udelay (1000);
1287e0c5	231	#endif /* CONFIG_TQM8548 */
d96f41e0	232
b99ba167	233	for (i = 0; i < N_DDR_CS_CONF; i++) {
d96f41e0 SR	234	ddr->cs0_config = ddr_cs_conf[i].reg;
d96f41e0 SR	235
b99ba167 WG	236	if (get_ram_size (0, ddr_cs_conf[i].size) ==
b99ba167 WG	237	ddr_cs_conf[i].size) {
d96f41e0	238	/*
518d5cfe	239	* size detected -> set Chip Select Bounds Register
d96f41e0	240	*/
518d5cfe WG	241	ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
518d5cfe WG	242
1287e0c5	243	break;
d96f41e0 SR	244	}
	245	}
	246
1287e0c5 WG	247	#ifdef CONFIG_TQM8548
	248	if (i < N_DDR_CS_CONF) {
	249	/* Adjust refresh rate for DDR2 */
	250
	251	ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
	252
	253	ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) \|
	254	(ddr_cs_conf[i].refresh & 0x0000F000);
	255
	256	return ddr_cs_conf[i].size;
	257	}
	258	#endif /* CONFIG_TQM8548 */
	259
	260	/* return size if detected, else return 0 */
	261	return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
d96f41e0 SR	262	}
d96f41e0 SR	263
b99ba167	264	void board_add_ram_info (int use_default)
d96f41e0 SR	265	{
	266	int casl;
	267
	268	if (use_default)
	269	casl = CONFIG_DDR_DEFAULT_CL;
	270	else
b99ba167	271	casl = cas_latency ();
d96f41e0	272
b99ba167	273	puts (" (CL=");
d96f41e0 SR	274	switch (casl) {
d96f41e0 SR	275	case 20:
b99ba167	276	puts ("2)");
d96f41e0 SR	277	break;
	278
	279	case 25:
b99ba167	280	puts ("2.5)");
d96f41e0 SR	281	break;
	282
	283	case 30:
b99ba167	284	puts ("3)");
d96f41e0 SR	285	break;
	286	}
	287	}
	288
9973e3c6	289	phys_size_t initdram (int board_type)
d96f41e0 SR	290	{
	291	long dram_size = 0;
	292	int casl;
	293
	294	#if defined(CONFIG_DDR_DLL)
	295	/*
	296	* This DLL-Override only used on TQM8540 and TQM8560
	297	*/
	298	{
6d0f6bcf	299	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
b99ba167	300	int i, x;
d96f41e0 SR	301
	302	x = 10;
	303
	304	/*
	305	* Work around to stabilize DDR DLL
	306	*/
	307	gur->ddrdllcr = 0x81000000;
b99ba167	308	asm ("sync; isync; msync");
d96f41e0 SR	309	udelay (200);
	310	while (gur->ddrdllcr != 0x81000100) {
	311	gur->devdisr = gur->devdisr \| 0x00010000;
b99ba167 WG	312	asm ("sync; isync; msync");
b99ba167 WG	313	for (i = 0; i < x; i++)
d96f41e0 SR	314	;
d96f41e0 SR	315	gur->devdisr = gur->devdisr & 0xfff7ffff;
b99ba167	316	asm ("sync; isync; msync");
d96f41e0 SR	317	x++;
	318	}
	319	}
	320	#endif
	321
b99ba167 WG	322	casl = cas_latency ();
b99ba167 WG	323	dram_size = sdram_setup (casl);
d96f41e0 SR	324	if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
	325	/*
	326	* Try again with default CAS latency
	327	*/
b99ba167 WG	328	puts ("Problem with CAS lantency");
	329	board_add_ram_info (1);
	330	puts (", using default CL!\n");
d96f41e0	331	casl = CONFIG_DDR_DEFAULT_CL;
b99ba167 WG	332	dram_size = sdram_setup (casl);
b99ba167 WG	333	puts (" ");
d96f41e0 SR	334	}
	335
	336	return dram_size;
	337	}
	338
6d0f6bcf	339	#if defined(CONFIG_SYS_DRAM_TEST)
d96f41e0 SR	340	int testdram (void)
d96f41e0 SR	341	{
6d0f6bcf JCPV	342	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	343	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
d96f41e0 SR	344	uint *p;
	345
	346	printf ("SDRAM test phase 1:\n");
	347	for (p = pstart; p < pend; p++)
	348	*p = 0xaaaaaaaa;
	349
	350	for (p = pstart; p < pend; p++) {
	351	if (*p != 0xaaaaaaaa) {
	352	printf ("SDRAM test fails at: %08x\n", (uint) p);
	353	return 1;
	354	}
	355	}
	356
	357	printf ("SDRAM test phase 2:\n");
	358	for (p = pstart; p < pend; p++)
	359	*p = 0x55555555;
	360
	361	for (p = pstart; p < pend; p++) {
	362	if (*p != 0x55555555) {
	363	printf ("SDRAM test fails at: %08x\n", (uint) p);
	364	return 1;
	365	}
	366	}
	367
	368	printf ("SDRAM test passed.\n");
	369	return 0;
	370	}
	371	#endif