[people/ms/u-boot.git] / board / tqc / tqm85xx / tlb.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
		       CFG_INIT_RAM_ADDR + 4 * 1024,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
		       CFG_INIT_RAM_ADDR + 8 * 1024,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
		       CFG_INIT_RAM_ADDR + 12 * 1024,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),

	/*
	 * TLB 0, 1:	128M	Non-cacheable, guarded
	 * 0xf8000000	128M	FLASH
	 * Out of reset this entry is only 4K.
	 */
	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 1, BOOKE_PAGESZ_64M, 1),
	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
		       CFG_FLASH_BASE + 0x4000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 0, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 2:	256M	Non-cacheable, guarded
	 * 0x80000000	256M	PCI1 MEM First half
	 */
	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 2, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 3:	256M	Non-cacheable, guarded
	 * 0x90000000	256M	PCI1 MEM Second half
	 */
	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
		       CFG_PCI1_MEM_PHYS + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 3, BOOKE_PAGESZ_256M, 1),

#ifdef CONFIG_PCIE1
	/*
	 * TLB 4:	256M	Non-cacheable, guarded
	 * 0xc0000000	256M	PCI express MEM First half
	 */
	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 4, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 5:	256M	Non-cacheable, guarded
	 * 0xd0000000	256M	PCI express MEM Second half
	 */
	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
		       CFG_PCIE1_MEM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
	/*
	 * TLB 4:	256M	Non-cacheable, guarded
	 * 0xc0000000	256M	Rapid IO MEM First half
	 */
	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 4, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 5:	256M	Non-cacheable, guarded
	 * 0xd0000000	256M	Rapid IO MEM Second half
	 */
	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
		       CFG_RIO_MEM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 5, BOOKE_PAGESZ_256M, 1),
#endif /* CONFIG_PCIE */

	/*
	 * TLB 6:	 64M	Non-cacheable, guarded
	 * 0xe0000000	  1M	CCSRBAR
	 * 0xe2000000	 16M	PCI1 IO
	 * 0xe3000000	 16M	CAN and NAND Flash
	 */
	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 6, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 7+8:	512M	 DDR, cache disabled (needed for memory test)
	 * 0x00000000	512M	 DDR System memory
	 * Without SPD EEPROM configured DDR, this must be setup manually.
	 * Make sure the TLB count at the top of this table is correct.
	 * Likely it needs to be increased by two for these entries.
	 */
	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 7, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
		       CFG_DDR_SDRAM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 8, BOOKE_PAGESZ_256M, 1),

#ifdef CONFIG_PCIE1
	/*
	 * TLB 9:	 16M	Non-cacheable, guarded
	 * 0xef000000	 16M	PCI express IO
	 */
	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */

};

int num_tlb_entries = ARRAY_SIZE (tlb_table);
Commit	Line	Data
3b558e26 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/mmu.h>
	28
	29	struct fsl_e_tlb_entry tlb_table[] = {
	30	/* TLB 0 - for temp stack in cache */
b99ba167 WG	31	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
	32	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
	33	0, 0, BOOKE_PAGESZ_4K, 0),
	34	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
	35	CFG_INIT_RAM_ADDR + 4 * 1024,
	36	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
	37	0, 0, BOOKE_PAGESZ_4K, 0),
	38	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
	39	CFG_INIT_RAM_ADDR + 8 * 1024,
	40	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
	41	0, 0, BOOKE_PAGESZ_4K, 0),
	42	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
	43	CFG_INIT_RAM_ADDR + 12 * 1024,
	44	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
	45	0, 0, BOOKE_PAGESZ_4K, 0),
3b558e26 KG	46
	47	/*
	48	* TLB 0, 1: 128M Non-cacheable, guarded
	49	* 0xf8000000 128M FLASH
	50	* Out of reset this entry is only 4K.
	51	*/
b99ba167 WG	52	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
	53	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	54	0, 1, BOOKE_PAGESZ_64M, 1),
	55	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
	56	CFG_FLASH_BASE + 0x4000000,
	57	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	58	0, 0, BOOKE_PAGESZ_64M, 1),
3b558e26 KG	59
	60	/*
	61	* TLB 2: 256M Non-cacheable, guarded
	62	* 0x80000000 256M PCI1 MEM First half
	63	*/
b99ba167 WG	64	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
	65	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	66	0, 2, BOOKE_PAGESZ_256M, 1),
3b558e26 KG	67
	68	/*
	69	* TLB 3: 256M Non-cacheable, guarded
	70	* 0x90000000 256M PCI1 MEM Second half
	71	*/
b99ba167 WG	72	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
	73	CFG_PCI1_MEM_PHYS + 0x10000000,
	74	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	75	0, 3, BOOKE_PAGESZ_256M, 1),
3b558e26	76
b9e8078b WG	77	#ifdef CONFIG_PCIE1
	78	/*
	79	* TLB 4: 256M Non-cacheable, guarded
	80	* 0xc0000000 256M PCI express MEM First half
	81	*/
	82	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
	83	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	84	0, 4, BOOKE_PAGESZ_256M, 1),
	85
	86	/*
	87	* TLB 5: 256M Non-cacheable, guarded
	88	* 0xd0000000 256M PCI express MEM Second half
	89	*/
	90	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
	91	CFG_PCIE1_MEM_BASE + 0x10000000,
	92	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	93	0, 5, BOOKE_PAGESZ_256M, 1),
	94	#else /* !CONFIG_PCIE */
3b558e26 KG	95	/*
	96	* TLB 4: 256M Non-cacheable, guarded
	97	* 0xc0000000 256M Rapid IO MEM First half
	98	*/
b99ba167 WG	99	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
	100	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	101	0, 4, BOOKE_PAGESZ_256M, 1),
3b558e26 KG	102
	103	/*
	104	* TLB 5: 256M Non-cacheable, guarded
	105	* 0xd0000000 256M Rapid IO MEM Second half
	106	*/
b99ba167 WG	107	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
	108	CFG_RIO_MEM_BASE + 0x10000000,
	109	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	110	0, 5, BOOKE_PAGESZ_256M, 1),
b9e8078b	111	#endif /* CONFIG_PCIE */
3b558e26 KG	112
3b558e26 KG	113	/*
b99ba167 WG	114	* TLB 6: 64M Non-cacheable, guarded
	115	* 0xe0000000 1M CCSRBAR
	116	* 0xe2000000 16M PCI1 IO
1c2deff2	117	* 0xe3000000 16M CAN and NAND Flash
3b558e26	118	*/
b99ba167 WG	119	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
	120	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	121	0, 6, BOOKE_PAGESZ_64M, 1),
3b558e26 KG	122
3b558e26 KG	123	/*
b99ba167 WG	124	* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
b99ba167 WG	125	* 0x00000000 512M DDR System memory
3b558e26 KG	126	* Without SPD EEPROM configured DDR, this must be setup manually.
	127	* Make sure the TLB count at the top of this table is correct.
	128	* Likely it needs to be increased by two for these entries.
	129	*/
b99ba167 WG	130	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
	131	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	132	0, 7, BOOKE_PAGESZ_256M, 1),
3b558e26	133
b99ba167 WG	134	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
	135	CFG_DDR_SDRAM_BASE + 0x10000000,
	136	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	137	0, 8, BOOKE_PAGESZ_256M, 1),
b9e8078b WG	138
	139	#ifdef CONFIG_PCIE1
	140	/*
	141	* TLB 9: 16M Non-cacheable, guarded
	142	* 0xef000000 16M PCI express IO
	143	*/
	144	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
	145	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	146	0, 9, BOOKE_PAGESZ_16M, 1),
	147	#endif /* CONFIG_PCIE */
	148
3b558e26 KG	149	};
3b558e26 KG	150
b99ba167	151	int num_tlb_entries = ARRAY_SIZE (tlb_table);