]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/tqc/tqm85xx/tqm85xx.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / tqc / tqm85xx / tqm85xx.c
CommitLineData
f5c5ef4a 1/*
1287e0c5
WG		 2 * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
3 *
4 * (C) Copyright 2006
5 * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
6 *
d96f41e0
SR		 7 * (C) Copyright 2005
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
f5c5ef4a
WD		 10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2002,2003, Motorola Inc.
12 * Xianghua Xiao, (X.Xiao@motorola.com)
13 *
14 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
f5c5ef4a
WD		 35#include <common.h>
36#include <pci.h>
37#include <asm/processor.h>
38#include <asm/immap_85xx.h>
b9e8078b 39#include <asm/immap_fsl_pci.h>
d9ee843d 40#include <asm/io.h>
f5c5ef4a 41#include <ioports.h>
d96f41e0 42#include <flash.h>
25991353
WG		 43#include <libfdt.h>
44#include <fdt_support.h>
10efa024 45#include <netdev.h>
f5c5ef4a 46
d87080b7
WD		 47DECLARE_GLOBAL_DATA_PTR;
48
d96f41e0 49extern flash_info_t flash_info[]; /* FLASH chips info */
f5c5ef4a
WD		 50
51void local_bus_init (void);
f18e874a 52ulong flash_get_size (ulong base, int banknum);
966083e9 53
bd3143f0 54#ifdef CONFIG_PS2MULT
b99ba167 55void ps2mult_early_init (void);
bd3143f0 56#endif
f5c5ef4a 57
d96f41e0 58#ifdef CONFIG_CPM2
f5c5ef4a
WD		 59/*
60 * I/O Port configuration table
61 *
62 * if conf is 1, then that port pin will be configured at boot time
63 * according to the five values podr/pdir/ppar/psor/pdat for that entry
64 */
65
66const iop_conf_t iop_conf_tab[4][32] = {
67
b99ba167
WG		 68 /* Port A: conf, ppar, psor, pdir, podr, pdat */
69 {
70 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
71 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
72 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
73 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
74 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
75 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
76 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
77 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
78 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
79 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
80 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
81 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
82 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
83 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
84 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
85 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
86 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
87 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
88 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
89 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
90 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
91 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
92 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
93 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
94 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
95 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
96 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
97 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
98 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
99 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
100 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
101 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
102 },
103
104 /* Port B: conf, ppar, psor, pdir, podr, pdat */
105 {
106 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
107 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
108 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
109 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
110 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
111 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
112 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
113 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
114 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
115 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
116 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
117 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
118 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
119 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
120 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
121 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
122 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
123 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
124 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
125 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
126 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
127 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
128 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
129 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
130 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
131 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
132 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
133 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
134 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
135 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
136 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
137 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
138 },
139
140 /* Port C: conf, ppar, psor, pdir, podr, pdat */
141 {
142 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
143 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
144 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
145 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
146 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
147 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
148 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
149 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
150 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
151 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
152 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
153 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
154 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
155 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
156 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
157 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
158 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
159 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
160 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
161 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
162 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
163 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
164 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
165 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
166 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
167 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
168 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
169 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
170 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
171 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
172 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
173 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
174 },
175
176 /* Port D: conf, ppar, psor, pdir, podr, pdat */
177 {
5d5bd838 178#ifdef CONFIG_TQM8560
b99ba167
WG		 179 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
180 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
181 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
5d5bd838
WG		 182#else /* !CONFIG_TQM8560 */
183 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
184 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
185 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
186#endif /* CONFIG_TQM8560 */
b99ba167
WG		 187 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
188 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
189 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
190 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
191 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
192 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
193 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
194 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
195 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
196 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
197 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
198 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
199 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
200 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
201 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
202 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
203 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
204 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
205 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
206 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
207 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
208 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
209 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
210 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
211 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
212 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
213 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
214 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
215 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
216 }
f5c5ef4a 217};
d96f41e0
SR		 218#endif /* CONFIG_CPM2 */
219
220#define CASL_STRING1 "casl=xx"
221#define CASL_STRING2 "casl="
f5c5ef4a 222
d96f41e0
SR		 223static const int casl_table[] = { 20, 25, 30 };
224#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
f5c5ef4a 225
b99ba167 226int cas_latency (void)
f5c5ef4a 227{
b99ba167 228 char *s = getenv ("serial#");
d96f41e0
SR		 229 int casl;
230 int val;
231 int i;
232
233 casl = CONFIG_DDR_DEFAULT_CL;
234
235 if (s != NULL) {
b99ba167
WG		 236 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
237 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
238 val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
d96f41e0 239
b99ba167 240 for (i = 0; i < N_CASL; ++i) {
d96f41e0
SR		 241 if (val == casl_table[i]) {
242 return val;
243 }
244 }
245 }
246 }
247
248 return casl;
f5c5ef4a
WD		 249}
250
251int checkboard (void)
252{
b99ba167 253 char *s = getenv ("serial#");
d96f41e0 254
b99ba167 255 printf ("Board: %s", CONFIG_BOARDNAME);
d96f41e0 256 if (s != NULL) {
b99ba167
WG		 257 puts (", serial# ");
258 puts (s);
d96f41e0 259 }
b99ba167 260 putc ('\n');
f5c5ef4a 261
f5c5ef4a
WD		 262 /*
263 * Initialize local bus.
264 */
265 local_bus_init ();
266
267 return 0;
268}
269
d96f41e0 270int misc_init_r (void)
f5c5ef4a 271{
6d0f6bcf 272 volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
f5c5ef4a 273
d96f41e0
SR		 274 /*
275 * Adjust flash start and offset to detected values
276 */
277 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
278 gd->bd->bi_flashoffset = 0;
9d2a873b 279
d96f41e0 280 /*
45dee2e6 281 * Recalculate CS configuration if second FLASH bank is available
d96f41e0 282 */
45dee2e6
WG		 283 if (flash_info[0].size > 0) {
284 memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
6d0f6bcf 285 (CONFIG_SYS_OR1_PRELIM & 0x00007fff);
45dee2e6 286 memctl->br1 = gd->bd->bi_flashstart |
6d0f6bcf 287 (CONFIG_SYS_BR1_PRELIM & 0x00007fff);
f5c5ef4a 288 /*
45dee2e6 289 * Re-check to get correct base address for bank 1
f5c5ef4a 290 */
45dee2e6
WG		 291 flash_get_size (gd->bd->bi_flashstart, 0);
292 } else {
293 memctl->or1 = 0;
294 memctl->br1 = 0;
f5c5ef4a 295 }
f5c5ef4a 296
f5c5ef4a 297 /*
45dee2e6 298 * If bank 1 is equipped, bank 0 is mapped after bank 1
f5c5ef4a 299 */
45dee2e6 300 memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
6d0f6bcf 301 (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
45dee2e6 302 memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
6d0f6bcf 303 (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
45dee2e6
WG		 304 /*
305 * Re-check to get correct base address for bank 0
306 */
307 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
f5c5ef4a 308
45dee2e6
WG		 309 /*
310 * Re-do flash protection upon new addresses
311 */
312 flash_protect (FLAG_PROTECT_CLEAR,
313 gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf 314 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6
WG		 315
316 /* Monitor protection ON by default */
317 flash_protect (FLAG_PROTECT_SET,
6d0f6bcf
JCPV		 318 CONFIG_SYS_MONITOR_BASE,
319 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
320 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6
WG		 321
322 /* Environment protection ON by default */
323 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 324 CONFIG_ENV_ADDR,
325 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf 326 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6 327
0e8d1586 328#ifdef CONFIG_ENV_ADDR_REDUND
45dee2e6
WG		 329 /* Redundant environment protection ON by default */
330 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 331 CONFIG_ENV_ADDR_REDUND,
332 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
6d0f6bcf 333 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6 334#endif
f5c5ef4a 335
d96f41e0
SR		 336 return 0;
337}
f5c5ef4a 338
d9ee843d
WG		 339#ifdef CONFIG_CAN_DRIVER
340/*
341 * Initialize UPMC RAM
342 */
343static void upmc_write (u_char addr, uint val)
344{
6d0f6bcf 345 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
d9ee843d
WG		 346
347 out_be32 (&lbc->mdr, val);
348
349 clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
350 MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
351
352 /* dummy access to perform write */
6d0f6bcf 353 out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
d9ee843d
WG		 354
355 /* normal operation */
356 clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
357}
358#endif /* CONFIG_CAN_DRIVER */
359
1287e0c5
WG		 360uint get_lbc_clock (void)
361{
6d0f6bcf 362 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
1287e0c5
WG		 363 sys_info_t sys_info;
364 ulong clkdiv = lbc->lcrr & 0x0f;
365
366 get_sys_info (&sys_info);
367
368 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
369#ifdef CONFIG_MPC8548
370 /*
371 * Yes, the entire PQ38 family use the same
372 * bit-representation for twice the clock divider value.
373 */
374 clkdiv *= 2;
375#endif
376 return sys_info.freqSystemBus / clkdiv;
377 }
378
6d0f6bcf 379 puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
1287e0c5
WG		 380
381 return 0;
382}
383
f5c5ef4a
WD		 384/*
385 * Initialize Local Bus
386 */
f5c5ef4a
WD		 387void local_bus_init (void)
388{
6d0f6bcf
JCPV		 389 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
390 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
1287e0c5
WG		 391 uint lbc_mhz = get_lbc_clock () / 1000000;
392
393#ifdef CONFIG_MPC8548
394 uint svr = get_svr ();
395 uint lcrr;
396
397 /*
398 * MPC revision < 2.0
399 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
400 * Modify engineering use only register at address 0xE_0F20.
401 * "1. Read register at offset 0xE_0F20
402 * 2. And value with 0x0000_FFFF
403 * 3. OR result with 0x0000_0004
404 * 4. Write result back to offset 0xE_0F20."
405 *
406 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
407 * Modify engineering use only register at address 0xE_0F20.
408 * "1. Read register at offset 0xE_0F20
409 * 2. And value with 0xFFFF_FFDF
410 * 3. Write result back to offset 0xE_0F20."
411 *
412 * Since it is the same register, we do the modification in one step.
413 */
414 if (SVR_MAJ (svr) < 2) {
415 uint dummy = gur->lbiuiplldcr1;
416 dummy &= 0x0000FFDF;
417 dummy |= 0x00000004;
418 gur->lbiuiplldcr1 = dummy;
419 }
f5c5ef4a 420
6d0f6bcf 421 lcrr = CONFIG_SYS_LBC_LCRR;
1287e0c5
WG		 422
423 /*
424 * Local Bus Clock > 83.3 MHz. According to timing
425 * specifications set LCRR[EADC] to 2 delay cycles.
426 */
427 if (lbc_mhz > 83) {
428 lcrr &= ~LCRR_EADC;
429 lcrr |= LCRR_EADC_2;
430 }
431
432 /*
433 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
434 * disable PLL bypass for Local Bus Clock > 83 MHz.
435 */
436 if (lbc_mhz >= 66)
437 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
438
439 else
440 lcrr |= LCRR_DBYP; /* DLL Bypass */
441
442 lbc->lcrr = lcrr;
443 asm ("sync;isync;msync");
444
445 /*
446 * According to MPC8548ERMAD Rev.1.3 read back LCRR
447 * and terminate with isync
448 */
449 lcrr = lbc->lcrr;
450 asm ("isync;");
451
452 /* let DLL stabilize */
453 udelay (500);
454
455#else /* !CONFIG_MPC8548 */
f5c5ef4a
WD		 456
457 /*
458 * Errata LBC11.
459 * Fix Local Bus clock glitch when DLL is enabled.
460 *
461 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
462 * If localbus freq is > 133Mhz, DLL can be safely enabled.
463 * Between 66 and 133, the DLL is enabled with an override workaround.
464 */
465
1287e0c5 466 if (lbc_mhz < 66) {
6d0f6bcf 467 lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
f2302d44
SR		 468 lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
469 LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
f5c5ef4a 470
1287e0c5 471 } else if (lbc_mhz >= 133) {
6d0f6bcf 472 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 473
474 } else {
475 /*
476 * On REV1 boards, need to change CLKDIV before enable DLL.
477 * Default CLKDIV is 8, change it to 4 temporarily.
478 */
479 uint pvr = get_pvr ();
480 uint temp_lbcdll = 0;
481
482 if (pvr == PVR_85xx_REV1) {
483 /* FIXME: Justify the high bit here. */
484 lbc->lcrr = 0x10000004;
485 }
486
6d0f6bcf 487 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 488 udelay (200);
489
490 /*
491 * Sample LBC DLL ctrl reg, upshift it to set the
492 * override bits.
493 */
494 temp_lbcdll = gur->lbcdllcr;
495 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
496 asm ("sync;isync;msync");
497 }
1287e0c5 498#endif /* !CONFIG_MPC8548 */
d9ee843d
WG		 499
500#ifdef CONFIG_CAN_DRIVER
501 /*
502 * According to timing specifications EAD must be
503 * set if Local Bus Clock is > 83 MHz.
504 */
1287e0c5 505 if (lbc_mhz > 83)
6d0f6bcf 506 out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
d9ee843d 507 else
6d0f6bcf
JCPV		 508 out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
509 out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
d9ee843d
WG		 510
511 /* LGPL4 is UPWAIT */
512 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
513
514 /* Initialize UPMC for CAN: single read */
515 upmc_write (0x00, 0xFFFFED00);
516 upmc_write (0x01, 0xCCFFCC00);
517 upmc_write (0x02, 0x00FFCF00);
518 upmc_write (0x03, 0x00FFCF00);
519 upmc_write (0x04, 0x00FFDC00);
520 upmc_write (0x05, 0x00FFCF00);
521 upmc_write (0x06, 0x00FFED00);
522 upmc_write (0x07, 0x3FFFCC07);
523
524 /* Initialize UPMC for CAN: single write */
525 upmc_write (0x18, 0xFFFFED00);
526 upmc_write (0x19, 0xCCFFEC00);
527 upmc_write (0x1A, 0x00FFED80);
528 upmc_write (0x1B, 0x00FFED80);
529 upmc_write (0x1C, 0x00FFFC00);
530 upmc_write (0x1D, 0x0FFFEC00);
531 upmc_write (0x1E, 0x0FFFEF00);
532 upmc_write (0x1F, 0x3FFFEC05);
533#endif /* CONFIG_CAN_DRIVER */
f5c5ef4a
WD		 534}
535
f5c5ef4a
WD		 536/*
537 * Initialize PCI Devices, report devices found.
538 */
b9e8078b 539static int first_free_busno;
f5c5ef4a 540
b9e8078b
WG		 541#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
542static struct pci_controller pci1_hose;
543#endif /* CONFIG_PCI || CONFIG_PCI1 */
f5c5ef4a 544
b9e8078b
WG		 545#ifdef CONFIG_PCIE1
546static struct pci_controller pcie1_hose;
547#endif /* CONFIG_PCIE1 */
548
549static inline void init_pci1(void)
550{
6d0f6bcf 551 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
b9e8078b
WG		 552#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
553 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
6d0f6bcf 554 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
b9e8078b
WG		 555 extern void fsl_pci_init(struct pci_controller *hose);
556 struct pci_controller *hose = &pci1_hose;
557
558 /* PORDEVSR[15] */
559 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
560 /* PORDEVSR[14] */
561 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
562 /* PORPLLSR[16] */
563 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
564
565 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) ||
566 (host_agent == 6);
567
568 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
569
570 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
571 printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
572 (pci_32) ? 32 : 64,
573 (pci_speed == 33333333) ? "33" :
574 (pci_speed == 66666666) ? "66" : "unknown",
575 pci_clk_sel ? "sync" : "async",
576 pci_agent ? "agent" : "host",
577 pci_arb ? "arbiter" : "external-arbiter");
578
579
580 /* inbound */
581 pci_set_region (hose->regions + 0,
6d0f6bcf
JCPV		 582 CONFIG_SYS_PCI_MEMORY_BUS,
583 CONFIG_SYS_PCI_MEMORY_PHYS,
584 CONFIG_SYS_PCI_MEMORY_SIZE,
b9e8078b
WG		 585 PCI_REGION_MEM | PCI_REGION_MEMORY);
586
587
588 /* outbound memory */
589 pci_set_region (hose->regions + 1,
6d0f6bcf
JCPV		 590 CONFIG_SYS_PCI1_MEM_BASE,
591 CONFIG_SYS_PCI1_MEM_PHYS,
592 CONFIG_SYS_PCI1_MEM_SIZE,
b9e8078b
WG		 593 PCI_REGION_MEM);
594
595 /* outbound io */
596 pci_set_region (hose->regions + 2,
6d0f6bcf
JCPV		 597 CONFIG_SYS_PCI1_IO_BASE,
598 CONFIG_SYS_PCI1_IO_PHYS,
599 CONFIG_SYS_PCI1_IO_SIZE,
b9e8078b
WG		 600 PCI_REGION_IO);
601
602 hose->region_count = 3;
603
604 hose->first_busno = first_free_busno;
605 pci_setup_indirect (hose, (int)&pci->cfg_addr,
606 (int)&pci->cfg_data);
607
608 fsl_pci_init (hose);
609
610 printf (" PCI on bus %02x..%02x\n",
611 hose->first_busno, hose->last_busno);
612
613 first_free_busno = hose->last_busno + 1;
614#ifdef CONFIG_PCIX_CHECK
615 if (!(gur->pordevsr & PORDEVSR_PCI)) {
616 ushort reg16 =
617 PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
618 PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
619 uint dev = PCI_BDF(hose->first_busno, 0, 0);
620
621 /* PCI-X init */
622 if (CONFIG_SYS_CLK_FREQ < 66000000)
623 puts ("PCI-X will only work at 66 MHz\n");
624
625 pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
626 reg16);
627 }
f5c5ef4a 628#endif
b9e8078b
WG		 629 } else {
630 puts ("PCI1: disabled\n");
631 }
632#else /* !(CONFIG_PCI || CONFIG_PCI1) */
633 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
634#endif /* CONFIG_PCI || CONFIG_PCI1) */
635}
636
637static inline void init_pcie1(void)
638{
6d0f6bcf 639 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
b9e8078b
WG		 640#ifdef CONFIG_PCIE1
641 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
642 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
6d0f6bcf 643 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
b9e8078b
WG		 644 extern void fsl_pci_init(struct pci_controller *hose);
645 struct pci_controller *hose = &pcie1_hose;
646 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
647 (host_agent == 3);
648
649 int pcie_configured = io_sel >= 1;
650
651 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
652 printf ("PCIe: %s, base address %x",
653 pcie_ep ? "End point" : "Root complex", (uint)pci);
654
655 if (pci->pme_msg_det) {
656 pci->pme_msg_det = 0xffffffff;
657 debug (", with errors. Clearing. Now 0x%08x",
658 pci->pme_msg_det);
659 }
660 puts ("\n");
f5c5ef4a 661
b9e8078b
WG		 662 /* inbound */
663 pci_set_region (hose->regions + 0,
6d0f6bcf
JCPV		 664 CONFIG_SYS_PCI_MEMORY_BUS,
665 CONFIG_SYS_PCI_MEMORY_PHYS,
666 CONFIG_SYS_PCI_MEMORY_SIZE,
b9e8078b
WG		 667 PCI_REGION_MEM | PCI_REGION_MEMORY);
668
669 /* outbound memory */
670 pci_set_region (hose->regions + 1,
6d0f6bcf
JCPV		 671 CONFIG_SYS_PCIE1_MEM_BASE,
672 CONFIG_SYS_PCIE1_MEM_PHYS,
673 CONFIG_SYS_PCIE1_MEM_SIZE,
b9e8078b
WG		 674 PCI_REGION_MEM);
675
676 /* outbound io */
677 pci_set_region (hose->regions + 2,
6d0f6bcf
JCPV		 678 CONFIG_SYS_PCIE1_IO_BASE,
679 CONFIG_SYS_PCIE1_IO_PHYS,
680 CONFIG_SYS_PCIE1_IO_SIZE,
b9e8078b
WG		 681 PCI_REGION_IO);
682
683 hose->region_count = 3;
684
685 hose->first_busno = first_free_busno;
686 pci_setup_indirect(hose, (int)&pci->cfg_addr,
687 (int)&pci->cfg_data);
688
689 fsl_pci_init (hose);
690 printf (" PCIe on bus %02x..%02x\n",
691 hose->first_busno, hose->last_busno);
692
693 first_free_busno = hose->last_busno + 1;
694
695 } else {
696 printf ("PCIe: disabled\n");
697 }
698#else /* !CONFIG_PCIE1 */
699 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
700#endif /* CONFIG_PCIE1 */
701}
f5c5ef4a 702
f5c5ef4a
WD		 703void pci_init_board (void)
704{
b9e8078b
WG		 705 init_pci1();
706 init_pcie1();
f5c5ef4a 707}
bc8bb6d4 708
b9e8078b 709#ifdef CONFIG_OF_BOARD_SETUP
25991353
WG		 710void ft_board_setup (void *blob, bd_t *bd)
711{
712 int node, tmp[2];
713 const char *path;
714
715 ft_cpu_setup (blob, bd);
716
717 node = fdt_path_offset (blob, "/aliases");
718 tmp[0] = 0;
719 if (node >= 0) {
b9e8078b 720#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
25991353
WG		 721 path = fdt_getprop (blob, node, "pci0", NULL);
722 if (path) {
b9e8078b 723 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
25991353
WG		 724 do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
725 }
b9e8078b
WG		 726#endif /* CONFIG_PCI || CONFIG_PCI1 */
727#ifdef CONFIG_PCIE1
728 path = fdt_getprop (blob, node, "pci1", NULL);
729 if (path) {
730 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
731 do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
732 }
733#endif /* CONFIG_PCIE1 */
25991353
WG		 734 }
735}
b9e8078b 736#endif /* CONFIG_OF_BOARD_SETUP */
25991353 737
bc8bb6d4
WD		 738#ifdef CONFIG_BOARD_EARLY_INIT_R
739int board_early_init_r (void)
740{
741#ifdef CONFIG_PS2MULT
b99ba167 742 ps2mult_early_init ();
bc8bb6d4
WD		 743#endif /* CONFIG_PS2MULT */
744 return (0);
745}
746#endif /* CONFIG_BOARD_EARLY_INIT_R */
10efa024
BW		 747
748int board_eth_init(bd_t *bis)
749{
750 cpu_eth_init(bis); /* Intialize TSECs first */
751 return pci_eth_init(bis);
752}
"Das U-Boot" Source Tree