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ppc4xx: ML507: Environment in flash and MTD Support
[people/ms/u-boot.git] / board / tqc / tqm85xx / tqm85xx.c
CommitLineData
f5c5ef4a 1/*
1287e0c5
WG		 2 * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
3 *
4 * (C) Copyright 2006
5 * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
6 *
d96f41e0
SR		 7 * (C) Copyright 2005
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
f5c5ef4a
WD		 10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2002,2003, Motorola Inc.
12 * Xianghua Xiao, (X.Xiao@motorola.com)
13 *
14 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
f5c5ef4a
WD		 35#include <common.h>
36#include <pci.h>
37#include <asm/processor.h>
38#include <asm/immap_85xx.h>
b9e8078b 39#include <asm/immap_fsl_pci.h>
d9ee843d 40#include <asm/io.h>
f5c5ef4a 41#include <ioports.h>
d96f41e0 42#include <flash.h>
25991353
WG		 43#include <libfdt.h>
44#include <fdt_support.h>
f5c5ef4a 45
d87080b7
WD		 46DECLARE_GLOBAL_DATA_PTR;
47
d96f41e0 48extern flash_info_t flash_info[]; /* FLASH chips info */
f5c5ef4a
WD		 49
50void local_bus_init (void);
f18e874a 51ulong flash_get_size (ulong base, int banknum);
966083e9 52
bd3143f0 53#ifdef CONFIG_PS2MULT
b99ba167 54void ps2mult_early_init (void);
bd3143f0 55#endif
f5c5ef4a 56
d96f41e0 57#ifdef CONFIG_CPM2
f5c5ef4a
WD		 58/*
59 * I/O Port configuration table
60 *
61 * if conf is 1, then that port pin will be configured at boot time
62 * according to the five values podr/pdir/ppar/psor/pdat for that entry
63 */
64
65const iop_conf_t iop_conf_tab[4][32] = {
66
b99ba167
WG		 67 /* Port A: conf, ppar, psor, pdir, podr, pdat */
68 {
69 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
70 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
71 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
72 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
73 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
74 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
75 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
76 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
77 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
78 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
79 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
80 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
81 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
82 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
83 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
84 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
85 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
86 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
87 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
88 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
89 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
90 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
91 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
92 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
93 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
94 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
95 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
96 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
97 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
98 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
99 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
100 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
101 },
102
103 /* Port B: conf, ppar, psor, pdir, podr, pdat */
104 {
105 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
106 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
107 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
108 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
109 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
110 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
111 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
112 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
113 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
114 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
115 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
116 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
117 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
118 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
119 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
120 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
121 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
122 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
123 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
124 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
125 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
126 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
127 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
128 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
129 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
130 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
131 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
132 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
133 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
134 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
135 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
136 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
137 },
138
139 /* Port C: conf, ppar, psor, pdir, podr, pdat */
140 {
141 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
142 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
143 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
144 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
145 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
146 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
147 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
148 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
149 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
150 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
151 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
152 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
153 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
154 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
155 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
156 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
157 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
158 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
159 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
160 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
161 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
162 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
163 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
164 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
165 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
166 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
167 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
168 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
169 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
170 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
171 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
172 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
173 },
174
175 /* Port D: conf, ppar, psor, pdir, podr, pdat */
176 {
5d5bd838 177#ifdef CONFIG_TQM8560
b99ba167
WG		 178 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
179 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
180 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
5d5bd838
WG		 181#else /* !CONFIG_TQM8560 */
182 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
183 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
184 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
185#endif /* CONFIG_TQM8560 */
b99ba167
WG		 186 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
187 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
188 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
189 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
190 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
191 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
192 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
193 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
194 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
195 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
196 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
197 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
198 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
199 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
200 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
201 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
202 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
203 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
204 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
205 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
206 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
207 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
208 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
209 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
210 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
211 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
212 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
213 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
214 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
215 }
f5c5ef4a 216};
d96f41e0
SR		 217#endif /* CONFIG_CPM2 */
218
219#define CASL_STRING1 "casl=xx"
220#define CASL_STRING2 "casl="
f5c5ef4a 221
d96f41e0
SR		 222static const int casl_table[] = { 20, 25, 30 };
223#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
f5c5ef4a 224
b99ba167 225int cas_latency (void)
f5c5ef4a 226{
b99ba167 227 char *s = getenv ("serial#");
d96f41e0
SR		 228 int casl;
229 int val;
230 int i;
231
232 casl = CONFIG_DDR_DEFAULT_CL;
233
234 if (s != NULL) {
b99ba167
WG		 235 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
236 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
237 val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
d96f41e0 238
b99ba167 239 for (i = 0; i < N_CASL; ++i) {
d96f41e0
SR		 240 if (val == casl_table[i]) {
241 return val;
242 }
243 }
244 }
245 }
246
247 return casl;
f5c5ef4a
WD		 248}
249
250int checkboard (void)
251{
b99ba167 252 char *s = getenv ("serial#");
d96f41e0 253
b99ba167 254 printf ("Board: %s", CONFIG_BOARDNAME);
d96f41e0 255 if (s != NULL) {
b99ba167
WG		 256 puts (", serial# ");
257 puts (s);
d96f41e0 258 }
b99ba167 259 putc ('\n');
f5c5ef4a 260
f5c5ef4a
WD		 261 /*
262 * Initialize local bus.
263 */
264 local_bus_init ();
265
266 return 0;
267}
268
d96f41e0 269int misc_init_r (void)
f5c5ef4a 270{
04db4008 271 volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
f5c5ef4a 272
d96f41e0
SR		 273 /*
274 * Adjust flash start and offset to detected values
275 */
276 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
277 gd->bd->bi_flashoffset = 0;
9d2a873b 278
d96f41e0 279 /*
45dee2e6 280 * Recalculate CS configuration if second FLASH bank is available
d96f41e0 281 */
45dee2e6
WG		 282 if (flash_info[0].size > 0) {
283 memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
284 (CFG_OR1_PRELIM & 0x00007fff);
285 memctl->br1 = gd->bd->bi_flashstart |
286 (CFG_BR1_PRELIM & 0x00007fff);
f5c5ef4a 287 /*
45dee2e6 288 * Re-check to get correct base address for bank 1
f5c5ef4a 289 */
45dee2e6
WG		 290 flash_get_size (gd->bd->bi_flashstart, 0);
291 } else {
292 memctl->or1 = 0;
293 memctl->br1 = 0;
f5c5ef4a 294 }
f5c5ef4a 295
f5c5ef4a 296 /*
45dee2e6 297 * If bank 1 is equipped, bank 0 is mapped after bank 1
f5c5ef4a 298 */
45dee2e6
WG		 299 memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
300 (CFG_OR0_PRELIM & 0x00007fff);
301 memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
302 (CFG_BR0_PRELIM & 0x00007fff);
303 /*
304 * Re-check to get correct base address for bank 0
305 */
306 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
f5c5ef4a 307
45dee2e6
WG		 308 /*
309 * Re-do flash protection upon new addresses
310 */
311 flash_protect (FLAG_PROTECT_CLEAR,
312 gd->bd->bi_flashstart, 0xffffffff,
313 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
314
315 /* Monitor protection ON by default */
316 flash_protect (FLAG_PROTECT_SET,
317 CFG_MONITOR_BASE,
318 CFG_MONITOR_BASE + monitor_flash_len - 1,
319 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
320
321 /* Environment protection ON by default */
322 flash_protect (FLAG_PROTECT_SET,
323 CFG_ENV_ADDR,
324 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
325 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
326
327#ifdef CFG_ENV_ADDR_REDUND
328 /* Redundant environment protection ON by default */
329 flash_protect (FLAG_PROTECT_SET,
330 CFG_ENV_ADDR_REDUND,
331 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
332 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
333#endif
f5c5ef4a 334
d96f41e0
SR		 335 return 0;
336}
f5c5ef4a 337
d9ee843d
WG		 338#ifdef CONFIG_CAN_DRIVER
339/*
340 * Initialize UPMC RAM
341 */
342static void upmc_write (u_char addr, uint val)
343{
344 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
345
346 out_be32 (&lbc->mdr, val);
347
348 clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
349 MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
350
351 /* dummy access to perform write */
352 out_8 ((void __iomem *)CFG_CAN_BASE, 0);
353
354 /* normal operation */
355 clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
356}
357#endif /* CONFIG_CAN_DRIVER */
358
1287e0c5
WG		 359uint get_lbc_clock (void)
360{
361 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
362 sys_info_t sys_info;
363 ulong clkdiv = lbc->lcrr & 0x0f;
364
365 get_sys_info (&sys_info);
366
367 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
368#ifdef CONFIG_MPC8548
369 /*
370 * Yes, the entire PQ38 family use the same
371 * bit-representation for twice the clock divider value.
372 */
373 clkdiv *= 2;
374#endif
375 return sys_info.freqSystemBus / clkdiv;
376 }
377
378 puts("Invalid clock divider value in CFG_LBC_LCRR\n");
379
380 return 0;
381}
382
f5c5ef4a
WD		 383/*
384 * Initialize Local Bus
385 */
f5c5ef4a
WD		 386void local_bus_init (void)
387{
f59b55a5 388 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
04db4008 389 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
1287e0c5
WG		 390 uint lbc_mhz = get_lbc_clock () / 1000000;
391
392#ifdef CONFIG_MPC8548
393 uint svr = get_svr ();
394 uint lcrr;
395
396 /*
397 * MPC revision < 2.0
398 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
399 * Modify engineering use only register at address 0xE_0F20.
400 * "1. Read register at offset 0xE_0F20
401 * 2. And value with 0x0000_FFFF
402 * 3. OR result with 0x0000_0004
403 * 4. Write result back to offset 0xE_0F20."
404 *
405 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
406 * Modify engineering use only register at address 0xE_0F20.
407 * "1. Read register at offset 0xE_0F20
408 * 2. And value with 0xFFFF_FFDF
409 * 3. Write result back to offset 0xE_0F20."
410 *
411 * Since it is the same register, we do the modification in one step.
412 */
413 if (SVR_MAJ (svr) < 2) {
414 uint dummy = gur->lbiuiplldcr1;
415 dummy &= 0x0000FFDF;
416 dummy |= 0x00000004;
417 gur->lbiuiplldcr1 = dummy;
418 }
f5c5ef4a 419
1287e0c5
WG		 420 lcrr = CFG_LBC_LCRR;
421
422 /*
423 * Local Bus Clock > 83.3 MHz. According to timing
424 * specifications set LCRR[EADC] to 2 delay cycles.
425 */
426 if (lbc_mhz > 83) {
427 lcrr &= ~LCRR_EADC;
428 lcrr |= LCRR_EADC_2;
429 }
430
431 /*
432 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
433 * disable PLL bypass for Local Bus Clock > 83 MHz.
434 */
435 if (lbc_mhz >= 66)
436 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
437
438 else
439 lcrr |= LCRR_DBYP; /* DLL Bypass */
440
441 lbc->lcrr = lcrr;
442 asm ("sync;isync;msync");
443
444 /*
445 * According to MPC8548ERMAD Rev.1.3 read back LCRR
446 * and terminate with isync
447 */
448 lcrr = lbc->lcrr;
449 asm ("isync;");
450
451 /* let DLL stabilize */
452 udelay (500);
453
454#else /* !CONFIG_MPC8548 */
f5c5ef4a
WD		 455
456 /*
457 * Errata LBC11.
458 * Fix Local Bus clock glitch when DLL is enabled.
459 *
460 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
461 * If localbus freq is > 133Mhz, DLL can be safely enabled.
462 * Between 66 and 133, the DLL is enabled with an override workaround.
463 */
464
1287e0c5
WG		 465 if (lbc_mhz < 66) {
466 lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
f5c5ef4a
WD		 467 lbc->ltedr = 0xa4c80000; /* DK: !!! */
468
1287e0c5
WG		 469 } else if (lbc_mhz >= 133) {
470 lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 471
472 } else {
473 /*
474 * On REV1 boards, need to change CLKDIV before enable DLL.
475 * Default CLKDIV is 8, change it to 4 temporarily.
476 */
477 uint pvr = get_pvr ();
478 uint temp_lbcdll = 0;
479
480 if (pvr == PVR_85xx_REV1) {
481 /* FIXME: Justify the high bit here. */
482 lbc->lcrr = 0x10000004;
483 }
484
1287e0c5 485 lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 486 udelay (200);
487
488 /*
489 * Sample LBC DLL ctrl reg, upshift it to set the
490 * override bits.
491 */
492 temp_lbcdll = gur->lbcdllcr;
493 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
494 asm ("sync;isync;msync");
495 }
1287e0c5 496#endif /* !CONFIG_MPC8548 */
d9ee843d
WG		 497
498#ifdef CONFIG_CAN_DRIVER
499 /*
500 * According to timing specifications EAD must be
501 * set if Local Bus Clock is > 83 MHz.
502 */
1287e0c5 503 if (lbc_mhz > 83)
d9ee843d
WG		 504 out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
505 else
506 out_be32 (&lbc->or2, CFG_OR2_CAN);
507 out_be32 (&lbc->br2, CFG_BR2_CAN);
508
509 /* LGPL4 is UPWAIT */
510 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
511
512 /* Initialize UPMC for CAN: single read */
513 upmc_write (0x00, 0xFFFFED00);
514 upmc_write (0x01, 0xCCFFCC00);
515 upmc_write (0x02, 0x00FFCF00);
516 upmc_write (0x03, 0x00FFCF00);
517 upmc_write (0x04, 0x00FFDC00);
518 upmc_write (0x05, 0x00FFCF00);
519 upmc_write (0x06, 0x00FFED00);
520 upmc_write (0x07, 0x3FFFCC07);
521
522 /* Initialize UPMC for CAN: single write */
523 upmc_write (0x18, 0xFFFFED00);
524 upmc_write (0x19, 0xCCFFEC00);
525 upmc_write (0x1A, 0x00FFED80);
526 upmc_write (0x1B, 0x00FFED80);
527 upmc_write (0x1C, 0x00FFFC00);
528 upmc_write (0x1D, 0x0FFFEC00);
529 upmc_write (0x1E, 0x0FFFEF00);
530 upmc_write (0x1F, 0x3FFFEC05);
531#endif /* CONFIG_CAN_DRIVER */
f5c5ef4a
WD		 532}
533
f5c5ef4a
WD		 534/*
535 * Initialize PCI Devices, report devices found.
536 */
b9e8078b 537static int first_free_busno;
f5c5ef4a 538
b9e8078b
WG		 539#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
540static struct pci_controller pci1_hose;
541#endif /* CONFIG_PCI || CONFIG_PCI1 */
f5c5ef4a 542
b9e8078b
WG		 543#ifdef CONFIG_PCIE1
544static struct pci_controller pcie1_hose;
545#endif /* CONFIG_PCIE1 */
546
547static inline void init_pci1(void)
548{
549 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
550#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
551 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
552 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR;
553 extern void fsl_pci_init(struct pci_controller *hose);
554 struct pci_controller *hose = &pci1_hose;
555
556 /* PORDEVSR[15] */
557 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
558 /* PORDEVSR[14] */
559 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
560 /* PORPLLSR[16] */
561 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
562
563 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) ||
564 (host_agent == 6);
565
566 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
567
568 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
569 printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
570 (pci_32) ? 32 : 64,
571 (pci_speed == 33333333) ? "33" :
572 (pci_speed == 66666666) ? "66" : "unknown",
573 pci_clk_sel ? "sync" : "async",
574 pci_agent ? "agent" : "host",
575 pci_arb ? "arbiter" : "external-arbiter");
576
577
578 /* inbound */
579 pci_set_region (hose->regions + 0,
580 CFG_PCI_MEMORY_BUS,
581 CFG_PCI_MEMORY_PHYS,
582 CFG_PCI_MEMORY_SIZE,
583 PCI_REGION_MEM | PCI_REGION_MEMORY);
584
585
586 /* outbound memory */
587 pci_set_region (hose->regions + 1,
588 CFG_PCI1_MEM_BASE,
589 CFG_PCI1_MEM_PHYS,
590 CFG_PCI1_MEM_SIZE,
591 PCI_REGION_MEM);
592
593 /* outbound io */
594 pci_set_region (hose->regions + 2,
595 CFG_PCI1_IO_BASE,
596 CFG_PCI1_IO_PHYS,
597 CFG_PCI1_IO_SIZE,
598 PCI_REGION_IO);
599
600 hose->region_count = 3;
601
602 hose->first_busno = first_free_busno;
603 pci_setup_indirect (hose, (int)&pci->cfg_addr,
604 (int)&pci->cfg_data);
605
606 fsl_pci_init (hose);
607
608 printf (" PCI on bus %02x..%02x\n",
609 hose->first_busno, hose->last_busno);
610
611 first_free_busno = hose->last_busno + 1;
612#ifdef CONFIG_PCIX_CHECK
613 if (!(gur->pordevsr & PORDEVSR_PCI)) {
614 ushort reg16 =
615 PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
616 PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
617 uint dev = PCI_BDF(hose->first_busno, 0, 0);
618
619 /* PCI-X init */
620 if (CONFIG_SYS_CLK_FREQ < 66000000)
621 puts ("PCI-X will only work at 66 MHz\n");
622
623 pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
624 reg16);
625 }
f5c5ef4a 626#endif
b9e8078b
WG		 627 } else {
628 puts ("PCI1: disabled\n");
629 }
630#else /* !(CONFIG_PCI || CONFIG_PCI1) */
631 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
632#endif /* CONFIG_PCI || CONFIG_PCI1) */
633}
634
635static inline void init_pcie1(void)
636{
637 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
638#ifdef CONFIG_PCIE1
639 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
640 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
641 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR;
642 extern void fsl_pci_init(struct pci_controller *hose);
643 struct pci_controller *hose = &pcie1_hose;
644 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
645 (host_agent == 3);
646
647 int pcie_configured = io_sel >= 1;
648
649 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
650 printf ("PCIe: %s, base address %x",
651 pcie_ep ? "End point" : "Root complex", (uint)pci);
652
653 if (pci->pme_msg_det) {
654 pci->pme_msg_det = 0xffffffff;
655 debug (", with errors. Clearing. Now 0x%08x",
656 pci->pme_msg_det);
657 }
658 puts ("\n");
f5c5ef4a 659
b9e8078b
WG		 660 /* inbound */
661 pci_set_region (hose->regions + 0,
662 CFG_PCI_MEMORY_BUS,
663 CFG_PCI_MEMORY_PHYS,
664 CFG_PCI_MEMORY_SIZE,
665 PCI_REGION_MEM | PCI_REGION_MEMORY);
666
667 /* outbound memory */
668 pci_set_region (hose->regions + 1,
669 CFG_PCIE1_MEM_BASE,
670 CFG_PCIE1_MEM_PHYS,
671 CFG_PCIE1_MEM_SIZE,
672 PCI_REGION_MEM);
673
674 /* outbound io */
675 pci_set_region (hose->regions + 2,
676 CFG_PCIE1_IO_BASE,
677 CFG_PCIE1_IO_PHYS,
678 CFG_PCIE1_IO_SIZE,
679 PCI_REGION_IO);
680
681 hose->region_count = 3;
682
683 hose->first_busno = first_free_busno;
684 pci_setup_indirect(hose, (int)&pci->cfg_addr,
685 (int)&pci->cfg_data);
686
687 fsl_pci_init (hose);
688 printf (" PCIe on bus %02x..%02x\n",
689 hose->first_busno, hose->last_busno);
690
691 first_free_busno = hose->last_busno + 1;
692
693 } else {
694 printf ("PCIe: disabled\n");
695 }
696#else /* !CONFIG_PCIE1 */
697 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
698#endif /* CONFIG_PCIE1 */
699}
f5c5ef4a 700
f5c5ef4a
WD		 701void pci_init_board (void)
702{
b9e8078b
WG		 703 init_pci1();
704 init_pcie1();
f5c5ef4a 705}
bc8bb6d4 706
b9e8078b 707#ifdef CONFIG_OF_BOARD_SETUP
25991353
WG		 708void ft_board_setup (void *blob, bd_t *bd)
709{
710 int node, tmp[2];
711 const char *path;
712
713 ft_cpu_setup (blob, bd);
714
715 node = fdt_path_offset (blob, "/aliases");
716 tmp[0] = 0;
717 if (node >= 0) {
b9e8078b 718#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
25991353
WG		 719 path = fdt_getprop (blob, node, "pci0", NULL);
720 if (path) {
b9e8078b 721 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
25991353
WG		 722 do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
723 }
b9e8078b
WG		 724#endif /* CONFIG_PCI || CONFIG_PCI1 */
725#ifdef CONFIG_PCIE1
726 path = fdt_getprop (blob, node, "pci1", NULL);
727 if (path) {
728 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
729 do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
730 }
731#endif /* CONFIG_PCIE1 */
25991353
WG		 732 }
733}
b9e8078b 734#endif /* CONFIG_OF_BOARD_SETUP */
25991353 735
bc8bb6d4
WD		 736#ifdef CONFIG_BOARD_EARLY_INIT_R
737int board_early_init_r (void)
738{
739#ifdef CONFIG_PS2MULT
b99ba167 740 ps2mult_early_init ();
bc8bb6d4
WD		 741#endif /* CONFIG_PS2MULT */
742 return (0);
743}
744#endif /* CONFIG_BOARD_EARLY_INIT_R */
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