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Fix incorrect use of getenv() before relocation
[people/ms/u-boot.git] / board / tqc / tqm85xx / tqm85xx.c
CommitLineData
f5c5ef4a 1/*
1287e0c5
WG		 2 * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
3 *
4 * (C) Copyright 2006
5 * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
6 *
d96f41e0
SR		 7 * (C) Copyright 2005
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
f5c5ef4a
WD		 10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2002,2003, Motorola Inc.
12 * Xianghua Xiao, (X.Xiao@motorola.com)
13 *
14 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
3cbd8231 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
f5c5ef4a
WD		 27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
f5c5ef4a
WD		 35#include <common.h>
36#include <pci.h>
37#include <asm/processor.h>
38#include <asm/immap_85xx.h>
c8514622 39#include <asm/fsl_pci.h>
d9ee843d 40#include <asm/io.h>
5d27e02c 41#include <asm/fsl_serdes.h>
06412756 42#include <linux/compiler.h>
f5c5ef4a 43#include <ioports.h>
d96f41e0 44#include <flash.h>
25991353
WG		 45#include <libfdt.h>
46#include <fdt_support.h>
10efa024 47#include <netdev.h>
f5c5ef4a 48
d87080b7
WD		 49DECLARE_GLOBAL_DATA_PTR;
50
d96f41e0 51extern flash_info_t flash_info[]; /* FLASH chips info */
f5c5ef4a
WD		 52
53void local_bus_init (void);
f18e874a 54ulong flash_get_size (ulong base, int banknum);
966083e9 55
bd3143f0 56#ifdef CONFIG_PS2MULT
b99ba167 57void ps2mult_early_init (void);
bd3143f0 58#endif
f5c5ef4a 59
d96f41e0 60#ifdef CONFIG_CPM2
f5c5ef4a
WD		 61/*
62 * I/O Port configuration table
63 *
64 * if conf is 1, then that port pin will be configured at boot time
65 * according to the five values podr/pdir/ppar/psor/pdat for that entry
66 */
67
68const iop_conf_t iop_conf_tab[4][32] = {
69
b99ba167
WG		 70 /* Port A: conf, ppar, psor, pdir, podr, pdat */
71 {
72 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
73 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
74 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
75 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
76 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
77 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
78 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
79 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
80 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
81 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
82 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
83 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
84 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
85 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
86 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
87 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
88 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
89 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
90 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
91 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
92 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
93 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
94 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
95 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
96 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
97 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
98 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
99 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
100 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
101 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
102 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
103 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
104 },
105
106 /* Port B: conf, ppar, psor, pdir, podr, pdat */
107 {
108 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
109 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
110 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
111 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
112 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
113 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
114 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
115 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
116 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
117 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
118 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
119 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
120 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
121 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
122 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
123 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
124 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
125 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
126 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
127 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
128 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
129 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
130 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
131 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
132 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
133 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
134 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
135 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
136 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
137 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
138 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
139 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
140 },
141
142 /* Port C: conf, ppar, psor, pdir, podr, pdat */
143 {
144 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
145 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
146 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
147 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
148 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
149 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
150 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
151 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
152 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
153 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
154 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
155 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
156 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
157 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
158 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
159 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
160 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
161 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
162 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
163 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
164 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
165 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
166 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
167 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
168 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
169 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
170 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
171 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
172 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
173 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
174 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
175 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
176 },
177
178 /* Port D: conf, ppar, psor, pdir, podr, pdat */
179 {
5d5bd838 180#ifdef CONFIG_TQM8560
b99ba167
WG		 181 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
182 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
183 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
5d5bd838
WG		 184#else /* !CONFIG_TQM8560 */
185 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
186 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
187 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
188#endif /* CONFIG_TQM8560 */
b99ba167
WG		 189 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
190 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
191 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
192 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
193 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
194 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
195 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
196 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
197 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
198 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
199 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
200 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
201 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
202 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
203 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
204 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
205 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
206 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
207 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
208 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
209 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
210 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
211 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
212 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
213 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
214 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
215 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
216 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
217 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
218 }
f5c5ef4a 219};
d96f41e0
SR		 220#endif /* CONFIG_CPM2 */
221
222#define CASL_STRING1 "casl=xx"
223#define CASL_STRING2 "casl="
f5c5ef4a 224
d96f41e0
SR		 225static const int casl_table[] = { 20, 25, 30 };
226#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
f5c5ef4a 227
b99ba167 228int cas_latency (void)
f5c5ef4a 229{
f0c0b3a9 230 char buf[128];
d96f41e0
SR		 231 int casl;
232 int val;
233 int i;
234
235 casl = CONFIG_DDR_DEFAULT_CL;
236
f0c0b3a9
WD		 237 i = getenv_f("serial#", buf, sizeof(buf));
238
239 if (i >0) {
240 if (strncmp(buf + strlen (buf) - strlen (CASL_STRING1),
b99ba167 241 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
f0c0b3a9 242 val = simple_strtoul (buf + strlen (buf) - 2, NULL, 10);
d96f41e0 243
b99ba167 244 for (i = 0; i < N_CASL; ++i) {
d96f41e0
SR		 245 if (val == casl_table[i]) {
246 return val;
247 }
248 }
249 }
250 }
251
252 return casl;
f5c5ef4a
WD		 253}
254
255int checkboard (void)
256{
f0c0b3a9
WD		 257 char buf[64];
258 int i = getenv_f("serial#", buf, sizeof(buf));
d96f41e0 259
b99ba167 260 printf ("Board: %s", CONFIG_BOARDNAME);
f0c0b3a9
WD		 261 if (i > 0) {
262 puts(", serial# ");
263 puts(buf);
d96f41e0 264 }
b99ba167 265 putc ('\n');
f5c5ef4a 266
f5c5ef4a
WD		 267 /*
268 * Initialize local bus.
269 */
270 local_bus_init ();
271
272 return 0;
273}
274
d96f41e0 275int misc_init_r (void)
f5c5ef4a 276{
d96f41e0
SR		 277 /*
278 * Adjust flash start and offset to detected values
279 */
280 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
281 gd->bd->bi_flashoffset = 0;
9d2a873b 282
d96f41e0 283 /*
45dee2e6 284 * Recalculate CS configuration if second FLASH bank is available
d96f41e0 285 */
45dee2e6 286 if (flash_info[0].size > 0) {
f51cdaf1
BB		 287 set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
288 (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
289 set_lbc_br(1, gd->bd->bi_flashstart |
290 (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
f5c5ef4a 291 /*
45dee2e6 292 * Re-check to get correct base address for bank 1
f5c5ef4a 293 */
45dee2e6
WG		 294 flash_get_size (gd->bd->bi_flashstart, 0);
295 } else {
f51cdaf1
BB		 296 set_lbc_or(1, 0);
297 set_lbc_br(1, 0);
f5c5ef4a 298 }
f5c5ef4a 299
f5c5ef4a 300 /*
45dee2e6 301 * If bank 1 is equipped, bank 0 is mapped after bank 1
f5c5ef4a 302 */
f51cdaf1
BB		 303 set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
304 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
b1b76464 305 set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
f51cdaf1
BB		 306 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
307
45dee2e6
WG		 308 /*
309 * Re-check to get correct base address for bank 0
310 */
311 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
f5c5ef4a 312
45dee2e6
WG		 313 /*
314 * Re-do flash protection upon new addresses
315 */
316 flash_protect (FLAG_PROTECT_CLEAR,
317 gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf 318 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6
WG		 319
320 /* Monitor protection ON by default */
321 flash_protect (FLAG_PROTECT_SET,
31ca9119 322 CONFIG_SYS_MONITOR_BASE, 0xffffffff,
6d0f6bcf 323 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6
WG		 324
325 /* Environment protection ON by default */
326 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 327 CONFIG_ENV_ADDR,
328 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf 329 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6 330
0e8d1586 331#ifdef CONFIG_ENV_ADDR_REDUND
45dee2e6
WG		 332 /* Redundant environment protection ON by default */
333 flash_protect (FLAG_PROTECT_SET,
0e8d1586 334 CONFIG_ENV_ADDR_REDUND,
dfcd7f21 335 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf 336 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6 337#endif
f5c5ef4a 338
d96f41e0
SR		 339 return 0;
340}
f5c5ef4a 341
d9ee843d
WG		 342#ifdef CONFIG_CAN_DRIVER
343/*
344 * Initialize UPMC RAM
345 */
346static void upmc_write (u_char addr, uint val)
347{
f51cdaf1 348 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
d9ee843d
WG		 349
350 out_be32 (&lbc->mdr, val);
351
352 clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
353 MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
354
355 /* dummy access to perform write */
6d0f6bcf 356 out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
d9ee843d
WG		 357
358 /* normal operation */
359 clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
360}
361#endif /* CONFIG_CAN_DRIVER */
362
1287e0c5
WG		 363uint get_lbc_clock (void)
364{
f51cdaf1 365 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
1287e0c5 366 sys_info_t sys_info;
a5d212a2 367 ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
1287e0c5
WG		 368
369 get_sys_info (&sys_info);
370
371 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
372#ifdef CONFIG_MPC8548
373 /*
374 * Yes, the entire PQ38 family use the same
375 * bit-representation for twice the clock divider value.
376 */
377 clkdiv *= 2;
378#endif
379 return sys_info.freqSystemBus / clkdiv;
380 }
381
6d0f6bcf 382 puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
1287e0c5
WG		 383
384 return 0;
385}
386
f5c5ef4a
WD		 387/*
388 * Initialize Local Bus
389 */
f5c5ef4a
WD		 390void local_bus_init (void)
391{
6d0f6bcf 392 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1 393 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
1287e0c5
WG		 394 uint lbc_mhz = get_lbc_clock () / 1000000;
395
396#ifdef CONFIG_MPC8548
397 uint svr = get_svr ();
398 uint lcrr;
399
400 /*
401 * MPC revision < 2.0
402 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
403 * Modify engineering use only register at address 0xE_0F20.
404 * "1. Read register at offset 0xE_0F20
405 * 2. And value with 0x0000_FFFF
406 * 3. OR result with 0x0000_0004
407 * 4. Write result back to offset 0xE_0F20."
408 *
409 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
410 * Modify engineering use only register at address 0xE_0F20.
411 * "1. Read register at offset 0xE_0F20
412 * 2. And value with 0xFFFF_FFDF
413 * 3. Write result back to offset 0xE_0F20."
414 *
415 * Since it is the same register, we do the modification in one step.
416 */
417 if (SVR_MAJ (svr) < 2) {
418 uint dummy = gur->lbiuiplldcr1;
419 dummy &= 0x0000FFDF;
420 dummy |= 0x00000004;
421 gur->lbiuiplldcr1 = dummy;
422 }
f5c5ef4a 423
6d0f6bcf 424 lcrr = CONFIG_SYS_LBC_LCRR;
1287e0c5
WG		 425
426 /*
427 * Local Bus Clock > 83.3 MHz. According to timing
428 * specifications set LCRR[EADC] to 2 delay cycles.
429 */
430 if (lbc_mhz > 83) {
431 lcrr &= ~LCRR_EADC;
432 lcrr |= LCRR_EADC_2;
433 }
434
435 /*
436 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
437 * disable PLL bypass for Local Bus Clock > 83 MHz.
438 */
439 if (lbc_mhz >= 66)
440 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
441
442 else
443 lcrr |= LCRR_DBYP; /* DLL Bypass */
444
445 lbc->lcrr = lcrr;
446 asm ("sync;isync;msync");
447
448 /*
449 * According to MPC8548ERMAD Rev.1.3 read back LCRR
450 * and terminate with isync
451 */
452 lcrr = lbc->lcrr;
453 asm ("isync;");
454
455 /* let DLL stabilize */
456 udelay (500);
457
458#else /* !CONFIG_MPC8548 */
f5c5ef4a
WD		 459
460 /*
461 * Errata LBC11.
462 * Fix Local Bus clock glitch when DLL is enabled.
463 *
8ed44d91
WD		 464 * If localbus freq is < 66MHz, DLL bypass mode must be used.
465 * If localbus freq is > 133MHz, DLL can be safely enabled.
f5c5ef4a
WD		 466 * Between 66 and 133, the DLL is enabled with an override workaround.
467 */
468
1287e0c5 469 if (lbc_mhz < 66) {
6d0f6bcf 470 lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
f2302d44
SR		 471 lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
472 LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
f5c5ef4a 473
1287e0c5 474 } else if (lbc_mhz >= 133) {
6d0f6bcf 475 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 476
477 } else {
478 /*
479 * On REV1 boards, need to change CLKDIV before enable DLL.
480 * Default CLKDIV is 8, change it to 4 temporarily.
481 */
482 uint pvr = get_pvr ();
483 uint temp_lbcdll = 0;
484
485 if (pvr == PVR_85xx_REV1) {
486 /* FIXME: Justify the high bit here. */
487 lbc->lcrr = 0x10000004;
488 }
489
6d0f6bcf 490 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 491 udelay (200);
492
493 /*
494 * Sample LBC DLL ctrl reg, upshift it to set the
495 * override bits.
496 */
497 temp_lbcdll = gur->lbcdllcr;
498 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
499 asm ("sync;isync;msync");
500 }
1287e0c5 501#endif /* !CONFIG_MPC8548 */
d9ee843d
WG		 502
503#ifdef CONFIG_CAN_DRIVER
504 /*
505 * According to timing specifications EAD must be
506 * set if Local Bus Clock is > 83 MHz.
507 */
1287e0c5 508 if (lbc_mhz > 83)
f51cdaf1 509 set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
d9ee843d 510 else
f51cdaf1
BB		 511 set_lbc_or(2, CONFIG_SYS_OR2_CAN);
512 set_lbc_br(2, CONFIG_SYS_BR2_CAN);
d9ee843d
WG		 513
514 /* LGPL4 is UPWAIT */
515 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
516
517 /* Initialize UPMC for CAN: single read */
518 upmc_write (0x00, 0xFFFFED00);
519 upmc_write (0x01, 0xCCFFCC00);
520 upmc_write (0x02, 0x00FFCF00);
521 upmc_write (0x03, 0x00FFCF00);
522 upmc_write (0x04, 0x00FFDC00);
523 upmc_write (0x05, 0x00FFCF00);
524 upmc_write (0x06, 0x00FFED00);
525 upmc_write (0x07, 0x3FFFCC07);
526
527 /* Initialize UPMC for CAN: single write */
528 upmc_write (0x18, 0xFFFFED00);
529 upmc_write (0x19, 0xCCFFEC00);
530 upmc_write (0x1A, 0x00FFED80);
531 upmc_write (0x1B, 0x00FFED80);
532 upmc_write (0x1C, 0x00FFFC00);
533 upmc_write (0x1D, 0x0FFFEC00);
534 upmc_write (0x1E, 0x0FFFEF00);
535 upmc_write (0x1F, 0x3FFFEC05);
536#endif /* CONFIG_CAN_DRIVER */
f5c5ef4a
WD		 537}
538
f5c5ef4a
WD		 539/*
540 * Initialize PCI Devices, report devices found.
541 */
542
a3182348 543#ifdef CONFIG_PCI1
b9e8078b 544static struct pci_controller pci1_hose;
a3182348 545#endif /* CONFIG_PCI1 */
f5c5ef4a 546
06412756 547void pci_init_board (void)
b9e8078b 548{
48f27919 549 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
06412756 550 int first_free_busno = 0;
48f27919
KG		 551#ifdef CONFIG_PCI1
552 struct fsl_pci_info pci_info;
06412756 553 int pcie_ep;
b9e8078b 554
06412756 555 u32 devdisr = in_be32(&gur->devdisr);
b9e8078b 556
06412756
PT		 557 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
558 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
b9e8078b 559 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
06412756 560 uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
b9e8078b 561
06412756 562 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
48f27919
KG		 563 SET_STD_PCI_INFO(pci_info, 1);
564 set_next_law(pci_info.mem_phys,
565 law_size_bits(pci_info.mem_size), pci_info.law);
566 set_next_law(pci_info.io_phys,
567 law_size_bits(pci_info.io_size), pci_info.law);
568
569 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c 570 printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
b9e8078b
WG		 571 (pci_32) ? 32 : 64,
572 (pci_speed == 33333333) ? "33" :
573 (pci_speed == 66666666) ? "66" : "unknown",
574 pci_clk_sel ? "sync" : "async",
06412756 575 pcie_ep ? "agent" : "host",
b9e8078b 576 pci_arb ? "arbiter" : "external-arbiter");
48f27919 577 first_free_busno = fsl_pci_init_port(&pci_info,
06412756 578 &pci1_hose, first_free_busno);
b9e8078b 579#ifdef CONFIG_PCIX_CHECK
06412756 580 if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
b9e8078b
WG		 581 ushort reg16 =
582 PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
583 PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
06412756 584 uint dev = PCI_BDF(0, 0, 0);
b9e8078b
WG		 585
586 /* PCI-X init */
587 if (CONFIG_SYS_CLK_FREQ < 66000000)
588 puts ("PCI-X will only work at 66 MHz\n");
589
06412756 590 pci_write_config_word(dev, PCIX_COMMAND, reg16);
b9e8078b 591 }
f5c5ef4a 592#endif
b9e8078b 593 } else {
8ca78f2c 594 printf("PCI1: disabled\n");
b9e8078b 595 }
06412756
PT		 596#else
597 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
598#endif
b9e8078b 599
48f27919 600 fsl_pcie_init_board(first_free_busno);
b9e8078b 601}
f5c5ef4a 602
b9e8078b 603#ifdef CONFIG_OF_BOARD_SETUP
25991353
WG		 604void ft_board_setup (void *blob, bd_t *bd)
605{
25991353
WG		 606 ft_cpu_setup (blob, bd);
607
6525d51f 608 FT_FSL_PCI_SETUP;
25991353 609}
b9e8078b 610#endif /* CONFIG_OF_BOARD_SETUP */
25991353 611
bc8bb6d4
WD		 612#ifdef CONFIG_BOARD_EARLY_INIT_R
613int board_early_init_r (void)
614{
615#ifdef CONFIG_PS2MULT
b99ba167 616 ps2mult_early_init ();
bc8bb6d4
WD		 617#endif /* CONFIG_PS2MULT */
618 return (0);
619}
620#endif /* CONFIG_BOARD_EARLY_INIT_R */
10efa024
BW		 621
622int board_eth_init(bd_t *bis)
623{
624 cpu_eth_init(bis); /* Intialize TSECs first */
625 return pci_eth_init(bis);
626}
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