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[people/ms/u-boot.git] / board / tqc / tqma6 / tqma6_wru4.c
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452308c0
SR		 1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 * Author: Fabio Estevam <fabio.estevam@freescale.com>
4 *
5 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
6 * Author: Markus Niebel <markus.niebel@tq-group.com>
7 *
8 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/iomux.h>
18#include <asm/arch/sys_proto.h>
1221ce45 19#include <linux/errno.h>
452308c0
SR		 20#include <asm/gpio.h>
21#include <asm/imx-common/boot_mode.h>
22#include <asm/imx-common/mxc_i2c.h>
23
24#include <common.h>
25#include <fsl_esdhc.h>
26#include <libfdt.h>
27#include <malloc.h>
28#include <i2c.h>
29#include <micrel.h>
30#include <miiphy.h>
31#include <mmc.h>
32#include <netdev.h>
33
34#include "tqma6_bb.h"
35
36/* UART */
37#define UART4_PAD_CTRL ( \
38 PAD_CTL_HYS | \
39 PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_PUE | \
41 PAD_CTL_PKE | \
42 PAD_CTL_SPEED_MED | \
43 PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_SLOW \
45 )
46
47static iomux_v3_cfg_t const uart4_pads[] = {
48 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
49 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
50 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
51 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
52};
53
54static void setup_iomuxc_uart4(void)
55{
56 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
57}
58
59/* MMC */
60#define USDHC2_PAD_CTRL ( \
61 PAD_CTL_HYS | \
62 PAD_CTL_PUS_47K_UP | \
63 PAD_CTL_SPEED_LOW | \
64 PAD_CTL_DSE_80ohm | \
65 PAD_CTL_SRE_FAST \
66 )
67
68#define USDHC2_CLK_PAD_CTRL ( \
69 PAD_CTL_HYS | \
70 PAD_CTL_PUS_47K_UP | \
71 PAD_CTL_SPEED_LOW | \
72 PAD_CTL_DSE_40ohm | \
73 PAD_CTL_SRE_FAST \
74 )
75
76static iomux_v3_cfg_t const usdhc2_pads[] = {
77 NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
78 NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
79 NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
80 NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
81 NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
82 NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
83
84 NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
85 NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
86};
87
88#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
89#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
90
91static struct fsl_esdhc_cfg usdhc2_cfg = {
92 .esdhc_base = USDHC2_BASE_ADDR,
93 .max_bus_width = 4,
94};
95
96int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
97{
98 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
99 int ret = 0;
100
101 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
102 ret = !gpio_get_value(USDHC2_CD_GPIO);
103
104 return ret;
105}
106
107int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
108{
109 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
110 int ret = 0;
111
112 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
113 ret = gpio_get_value(USDHC2_WP_GPIO);
114
115 return ret;
116}
117
118int tqma6_bb_board_mmc_init(bd_t *bis)
119{
120 int ret;
121
122 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
123
124 ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
125 if (!ret)
126 gpio_direction_input(USDHC2_CD_GPIO);
127 ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
128 if (!ret)
129 gpio_direction_input(USDHC2_WP_GPIO);
130
131 usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
132 if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
133 puts("WARNING: failed to initialize SD\n");
134
135 return 0;
136}
137
138/* Ethernet */
139#define ENET_PAD_CTRL ( \
140 PAD_CTL_HYS | \
141 PAD_CTL_PUS_100K_UP | \
142 PAD_CTL_PUE | \
143 PAD_CTL_PKE | \
144 PAD_CTL_SPEED_MED | \
145 PAD_CTL_DSE_40ohm | \
146 PAD_CTL_SRE_SLOW \
147 )
148
149static iomux_v3_cfg_t const enet_pads[] = {
150 NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
151 NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
152 NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
153 NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
154 NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
155 NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
156 NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
157 NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
158 NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
159 NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
160 NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
161
162 /* ENET1 reset */
163 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
164 /* ENET1 interrupt */
165 NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
166};
167
168#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
169
170static void setup_iomuxc_enet(void)
171{
172 int ret;
173
174 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
175
176 /* Reset LAN8720 PHY */
177 ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
178 if (!ret)
179 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
755a116e 180 udelay(25000);
452308c0
SR		 181 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
182}
183
184int board_eth_init(bd_t *bis)
185{
186 return cpu_eth_init(bis);
187}
188
189/* GPIO */
190#define GPIO_PAD_CTRL ( \
191 PAD_CTL_HYS | \
192 PAD_CTL_PUS_100K_UP | \
193 PAD_CTL_PUE | \
194 PAD_CTL_SPEED_MED | \
195 PAD_CTL_DSE_40ohm | \
196 PAD_CTL_SRE_SLOW \
197 )
198
199#define GPIO_OD_PAD_CTRL ( \
200 PAD_CTL_HYS | \
201 PAD_CTL_PUS_100K_UP | \
202 PAD_CTL_PUE | \
203 PAD_CTL_ODE | \
204 PAD_CTL_SPEED_MED | \
205 PAD_CTL_DSE_40ohm | \
206 PAD_CTL_SRE_SLOW \
207 )
208
209static iomux_v3_cfg_t const gpio_pads[] = {
210 /* USB_H_PWR */
211 NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
212 /* USB_OTG_PWR */
213 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
214 /* PCIE_RST */
215 NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
216 /* UART1_PWRON */
217 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
218 /* UART2_PWRON */
219 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
220 /* UART3_PWRON */
221 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
222};
223
224#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
225#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
226#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
227#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
228#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
229#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
230
231static void gpio_init(void)
232{
233 int ret;
234
235 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
236
237 ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
238 if (!ret)
239 gpio_direction_output(GPIO_USB_H_PWR, 1);
240 ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
241 if (!ret)
242 gpio_direction_output(GPIO_USB_OTG_PWR, 1);
243 ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
244 if (!ret)
245 gpio_direction_output(GPIO_PCIE_RST, 1);
246 ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
247 if (!ret)
248 gpio_direction_output(GPIO_UART1_PWRON, 0);
249 ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
250 if (!ret)
251 gpio_direction_output(GPIO_UART2_PWRON, 0);
252 ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
253 if (!ret)
254 gpio_direction_output(GPIO_UART3_PWRON, 0);
255}
256
257void tqma6_iomuxc_spi(void)
258{
259 /* No SPI on this baseboard */
260}
261
262int tqma6_bb_board_early_init_f(void)
263{
264 setup_iomuxc_uart4();
265
266 return 0;
267}
268
269int tqma6_bb_board_init(void)
270{
271 setup_iomuxc_enet();
272
273 gpio_init();
274
275 /* Turn the UART-couplers on one-after-another */
276 gpio_set_value(GPIO_UART1_PWRON, 1);
277 mdelay(10);
278 gpio_set_value(GPIO_UART2_PWRON, 1);
279 mdelay(10);
280 gpio_set_value(GPIO_UART3_PWRON, 1);
281
282 return 0;
283}
284
285int tqma6_bb_board_late_init(void)
286{
287 return 0;
288}
289
290const char *tqma6_bb_get_boardname(void)
291{
292 return "WRU-IV";
293}
294
295static const struct boot_mode board_boot_modes[] = {
296 /* 4 bit bus width */
297 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
298 /* 8 bit bus width */
299 {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
300 { NULL, 0 },
301};
302
303int misc_init_r(void)
304{
305 add_board_boot_modes(board_boot_modes);
306
307 return 0;
308}
309
310#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
311#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
312
313int board_ehci_hcd_init(int port)
314{
315 int ret;
316
317 ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
318 if (!ret)
319 gpio_direction_output(WRU4_USB_H1_PWR, 1);
320
321 ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
322 if (!ret)
323 gpio_direction_output(WRU4_USB_OTG_PWR, 1);
324
325 return 0;
326}
327
328int board_ehci_power(int port, int on)
329{
330 if (port)
331 gpio_set_value(WRU4_USB_OTG_PWR, on);
332 else
333 gpio_set_value(WRU4_USB_H1_PWR, on);
334
335 return 0;
336}
337
338/*
339 * Device Tree Support
340 */
341#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
342void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
343{
344 /* TBD */
345}
346#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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