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[PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH
[people/ms/u-boot.git] / board / tqm5200 / tqm5200.c
CommitLineData
56523f12 1/*
45a212c4 2 * (C) Copyright 2003-2006
56523f12
WD		 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
45a212c4 8 * (C) Copyright 2004-2006
56523f12
WD		 9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
81050926 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56523f12
WD		 22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
31#include <mpc5xxx.h>
32#include <pci.h>
45a212c4 33#include <asm/processor.h>
56523f12 34
8f0b7cbe
WD		 35#ifdef CONFIG_VIDEO_SM501
36#include <sm501.h>
37#endif
38
56523f12
WD		 39#if defined(CONFIG_MPC5200_DDR)
40#include "mt46v16m16-75.h"
41#else
42#include "mt48lc16m16a2-75.h"
43#endif
8f0b7cbe 44
7e6bf358
WD		 45#ifdef CONFIG_PS2MULT
46void ps2mult_early_init(void);
47#endif
56523f12
WD		 48
49#ifndef CFG_RAMBOOT
50static void sdram_start (int hi_addr)
51{
52 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
53
54 /* unlock mode register */
55 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
56 hi_addr_bit;
57 __asm__ volatile ("sync");
58
59 /* precharge all banks */
60 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
61 hi_addr_bit;
62 __asm__ volatile ("sync");
63
64#if SDRAM_DDR
65 /* set mode register: extended mode */
66 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
67 __asm__ volatile ("sync");
68
69 /* set mode register: reset DLL */
70 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
71 __asm__ volatile ("sync");
72#endif
73
74 /* precharge all banks */
75 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
76 hi_addr_bit;
77 __asm__ volatile ("sync");
78
79 /* auto refresh */
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
81 hi_addr_bit;
82 __asm__ volatile ("sync");
83
84 /* set mode register */
85 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
86 __asm__ volatile ("sync");
87
88 /* normal operation */
89 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
90 __asm__ volatile ("sync");
91}
92#endif
93
94/*
95 * ATTENTION: Although partially referenced initdram does NOT make real use
81050926
WD		 96 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
97 * is something else than 0x00000000.
56523f12
WD		 98 */
99
100#if defined(CONFIG_MPC5200)
101long int initdram (int board_type)
102{
103 ulong dramsize = 0;
104 ulong dramsize2 = 0;
45a212c4
WD		 105 uint svr, pvr;
106
56523f12
WD		 107#ifndef CFG_RAMBOOT
108 ulong test1, test2;
109
110 /* setup SDRAM chip selects */
111 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
112 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
113 __asm__ volatile ("sync");
114
115 /* setup config registers */
116 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
117 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
118 __asm__ volatile ("sync");
119
120#if SDRAM_DDR
121 /* set tap delay */
122 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
123 __asm__ volatile ("sync");
124#endif
125
126 /* find RAM size using SDRAM CS0 only */
127 sdram_start(0);
77ddac94 128 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
56523f12 129 sdram_start(1);
77ddac94 130 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
56523f12
WD		 131 if (test1 > test2) {
132 sdram_start(0);
133 dramsize = test1;
134 } else {
135 dramsize = test2;
136 }
137
138 /* memory smaller than 1MB is impossible */
139 if (dramsize < (1 << 20)) {
140 dramsize = 0;
141 }
142
143 /* set SDRAM CS0 size according to the amount of RAM found */
144 if (dramsize > 0) {
145 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
146 __builtin_ffs(dramsize >> 20) - 1;
147 } else {
148 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
149 }
150
151 /* let SDRAM CS1 start right after CS0 */
152 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
153
154 /* find RAM size using SDRAM CS1 only */
155 sdram_start(0);
77ddac94 156 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
56523f12 157 sdram_start(1);
77ddac94 158 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
56523f12
WD		 159 if (test1 > test2) {
160 sdram_start(0);
161 dramsize2 = test1;
162 } else {
163 dramsize2 = test2;
164 }
165
166 /* memory smaller than 1MB is impossible */
167 if (dramsize2 < (1 << 20)) {
168 dramsize2 = 0;
169 }
170
171 /* set SDRAM CS1 size according to the amount of RAM found */
172 if (dramsize2 > 0) {
173 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
174 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
175 } else {
176 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
177 }
178
179#else /* CFG_RAMBOOT */
180
181 /* retrieve size of memory connected to SDRAM CS0 */
182 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
183 if (dramsize >= 0x13) {
184 dramsize = (1 << (dramsize - 0x13)) << 20;
185 } else {
186 dramsize = 0;
187 }
188
189 /* retrieve size of memory connected to SDRAM CS1 */
190 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
191 if (dramsize2 >= 0x13) {
192 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
193 } else {
194 dramsize2 = 0;
195 }
56523f12
WD		 196#endif /* CFG_RAMBOOT */
197
45a212c4
WD		 198 /*
199 * On MPC5200B we need to set the special configuration delay in the
200 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
201 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
202 *
203 * "The SDelay should be written to a value of 0x00000004. It is
204 * required to account for changes caused by normal wafer processing
205 * parameters."
206 */
207 svr = get_svr();
208 pvr = get_pvr();
209 if ((SVR_MJREV(svr) >= 2) &&
210 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
211
212 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
213 __asm__ volatile ("sync");
214 }
215
216#if defined(CONFIG_TQM5200_B)
217 return dramsize + dramsize2;
218#else
56523f12 219 return dramsize;
45a212c4 220#endif /* CONFIG_TQM5200_B */
56523f12
WD		 221}
222
223#elif defined(CONFIG_MGT5100)
224
225long int initdram (int board_type)
226{
227 ulong dramsize = 0;
228#ifndef CFG_RAMBOOT
229 ulong test1, test2;
230
231 /* setup and enable SDRAM chip selects */
232 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
233 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
234 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
235 __asm__ volatile ("sync");
236
237 /* setup config registers */
238 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
239 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
240
241 /* address select register */
242 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
243 __asm__ volatile ("sync");
244
245 /* find RAM size */
246 sdram_start(0);
247 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
248 sdram_start(1);
249 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
250 if (test1 > test2) {
251 sdram_start(0);
252 dramsize = test1;
253 } else {
254 dramsize = test2;
255 }
256
257 /* set SDRAM end address according to size */
258 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
259
260#else /* CFG_RAMBOOT */
261
262 /* Retrieve amount of SDRAM available */
263 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
264
265#endif /* CFG_RAMBOOT */
266
267 return dramsize;
268}
269
270#else
271#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
272#endif
273
274int checkboard (void)
275{
5078cce8 276#if defined(CONFIG_AEVFIFO)
8f79e4c2
WD		 277 puts ("Board: AEVFIFO\n");
278 return 0;
279#endif
5078cce8
WD		 280
281#if defined(CONFIG_TQM5200S)
282# define MODULE_NAME "TQM5200S"
45a212c4 283#else
5078cce8 284# define MODULE_NAME "TQM5200"
7e6bf358 285#endif
5078cce8
WD		 286
287#if defined(CONFIG_STK52XX)
288# define CARRIER_NAME "STK52xx"
289#elif defined(CONFIG_TB5200)
290# define CARRIER_NAME "TB5200"
135ae006
WD		 291#elif defined(CONFIG_CAM5200)
292# define CARRIER_NAME "Cam5200"
6d3bc9b8
MB		 293#elif defined(CONFIG_FO300)
294# define CARRIER_NAME "FO300"
5078cce8 295#else
5196a7a0 296# error "UNKNOWN"
b87dfd28 297#endif
7e6bf358 298
5078cce8
WD		 299 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
300 " on a " CARRIER_NAME " carrier board\n");
301
56523f12
WD		 302 return 0;
303}
304
5078cce8
WD		 305#undef MODULE_NAME
306#undef CARRIER_NAME
307
56523f12
WD		 308void flash_preinit(void)
309{
310 /*
311 * Now, when we are in RAM, enable flash write
312 * access for detection process.
313 * Note that CS_BOOT cannot be cleared when
314 * executing in flash.
315 */
316#if defined(CONFIG_MGT5100)
317 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
318 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
319#endif
320 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
321}
322
323
324#ifdef CONFIG_PCI
325static struct pci_controller hose;
326
327extern void pci_mpc5xxx_init(struct pci_controller *);
328
329void pci_init_board(void)
330{
331 pci_mpc5xxx_init(&hose);
332}
333#endif
334
335#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
336
337#if defined (CONFIG_MINIFAP)
338#define SM501_POWER_MODE0_GATE 0x00000040UL
339#define SM501_POWER_MODE1_GATE 0x00000048UL
340#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
341#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
342#define SM501_GPIO_DATA_HIGH 0x00010004UL
343#define SM501_GPIO_51 0x00080000UL
dae80f3c 344#endif /* CONFIG MINIFAP */
56523f12
WD		 345
346void init_ide_reset (void)
347{
348 debug ("init_ide_reset\n");
349
350#if defined (CONFIG_MINIFAP)
351 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
352
353 /* enable GPIO control (in both power modes) */
354 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
355 POWER_MODE_GATE_GPIO_PWM_I2C;
356 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
357 POWER_MODE_GATE_GPIO_PWM_I2C;
358 /* configure GPIO51 as output */
359 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
360 SM501_GPIO_51;
361#else
362 /* Configure PSC1_4 as GPIO output for ATA reset */
363 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
364 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
365#endif
366}
367
368void ide_set_reset (int idereset)
369{
370 debug ("ide_reset(%d)\n", idereset);
371
372#if defined (CONFIG_MINIFAP)
373 if (idereset) {
374 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
375 ~SM501_GPIO_51;
376 } else {
377 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
378 SM501_GPIO_51;
379 }
380#else
381 if (idereset) {
dae80f3c 382 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
56523f12 383 } else {
dae80f3c 384 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
56523f12
WD		 385 }
386#endif
387}
388#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
389
390#ifdef CONFIG_POST
391/*
392 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
393 * is left open, no keypress is detected.
394 */
395int post_hotkeys_pressed(void)
396{
1d92b2e5 397#ifdef CONFIG_STK52XX
56523f12
WD		 398 struct mpc5xxx_gpio *gpio;
399
400 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
401
402 /*
403 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
404 * CODEC or UART mode. Consumer IrDA should still be possible.
81050926 405 */
56523f12
WD		 406 gpio->port_config &= ~(0x07000000);
407 gpio->port_config |= 0x03000000;
408
409 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
410 gpio->simple_gpioe |= 0x20000000;
411
412 /* Configure GPIO_IRDA_1 as input */
413 gpio->simple_ddr &= ~(0x20000000);
414
415 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
1d92b2e5
WD		 416#else
417 return 0;
418#endif
56523f12
WD		 419}
420#endif
421
422#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
423
424void post_word_store (ulong a)
425{
426 volatile ulong *save_addr =
427 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
428
429 *save_addr = a;
430}
431
432ulong post_word_load (void)
433{
434 volatile ulong *save_addr =
435 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
436
437 return *save_addr;
438}
56523f12 439#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
7e6bf358
WD		 440
441#ifdef CONFIG_PS2MULT
442#ifdef CONFIG_BOARD_EARLY_INIT_R
443int board_early_init_r (void)
444{
445 ps2mult_early_init();
446 return (0);
447}
448#endif
449#endif /* CONFIG_PS2MULT */
450
aeec782b
WD		 451#ifdef CONFIG_FO300
452int silent_boot (void)
453{
454 vu_long timer3_status;
455
456 /* Configure GPT3 as GPIO input */
457 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
458
459 /* Read in TIMER_3 pin status */
460 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
461
462#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
463 /* Force silent console mode if S1 switch
464 * is in closed position (TIMER_3 pin status is LOW). */
465 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
466 return 1;
467#else
468 /* Force silent console mode if S1 switch
469 * is in open position (TIMER_3 pin status is HIGH). */
470 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
471 return 1;
472#endif
473
474 return 0;
475}
476
477int board_early_init_f (void)
478{
479 DECLARE_GLOBAL_DATA_PTR;
480
481 if (silent_boot())
482 gd->flags |= GD_FLG_SILENT;
483
484 return 0;
485}
486#endif /* CONFIG_FO300 */
487
7e6bf358
WD		 488int last_stage_init (void)
489{
490 /*
491 * auto scan for really existing devices and re-set chip select
492 * configuration.
493 */
494 u16 save, tmp;
495 int restore;
496
497 /*
498 * Check for SRAM and SRAM size
499 */
500
e8aa824e 501 /* save original SRAM content */
7e6bf358
WD		 502 save = *(volatile u16 *)CFG_CS2_START;
503 restore = 1;
efe2a4d5 504
7e6bf358
WD		 505 /* write test pattern to SRAM */
506 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
507 __asm__ volatile ("sync");
508 /*
509 * Put a different pattern on the data lines: otherwise they may float
510 * long enough to read back what we wrote.
511 */
512 tmp = *(volatile u16 *)CFG_FLASH_BASE;
513 if (tmp == 0xA5A5)
514 puts ("!! possible error in SRAM detection\n");
efe2a4d5 515
7e6bf358
WD		 516 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
517 /* no SRAM at all, disable cs */
518 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
519 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
520 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
521 restore = 0;
522 __asm__ volatile ("sync");
e8aa824e 523 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
7e6bf358
WD		 524 /* make sure that we access a mirrored address */
525 *(volatile u16 *)CFG_CS2_START = 0x1111;
526 __asm__ volatile ("sync");
527 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
528 /* SRAM size = 512 kByte */
efe2a4d5 529 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
7e6bf358
WD		 530 0x80000);
531 __asm__ volatile ("sync");
532 puts ("SRAM: 512 kB\n");
533 }
534 else
efe2a4d5 535 puts ("!! possible error in SRAM detection\n");
e8aa824e 536 } else {
efe2a4d5 537 puts ("SRAM: 1 MB\n");
7e6bf358
WD		 538 }
539 /* restore origianl SRAM content */
540 if (restore) {
541 *(volatile u16 *)CFG_CS2_START = save;
542 __asm__ volatile ("sync");
543 }
efe2a4d5
WD		 544
545 /*
7e6bf358
WD		 546 * Check for Grafic Controller
547 */
548
549 /* save origianl FB content */
550 save = *(volatile u16 *)CFG_CS1_START;
551 restore = 1;
efe2a4d5 552
7e6bf358
WD		 553 /* write test pattern to FB memory */
554 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
555 __asm__ volatile ("sync");
556 /*
557 * Put a different pattern on the data lines: otherwise they may float
558 * long enough to read back what we wrote.
559 */
560 tmp = *(volatile u16 *)CFG_FLASH_BASE;
561 if (tmp == 0xA5A5)
562 puts ("!! possible error in grafic controller detection\n");
efe2a4d5 563
7e6bf358
WD		 564 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
565 /* no grafic controller at all, disable cs */
566 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
567 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
568 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
569 restore = 0;
570 __asm__ volatile ("sync");
e8aa824e 571 } else {
efe2a4d5 572 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
7e6bf358
WD		 573 }
574 /* restore origianl FB content */
575 if (restore) {
576 *(volatile u16 *)CFG_CS1_START = save;
577 __asm__ volatile ("sync");
578 }
efe2a4d5 579
aeec782b
WD		 580#ifdef CONFIG_FO300
581 if (silent_boot()) {
582 setenv("bootdelay", "0");
583 disable_ctrlc(1);
584 }
585#endif
586
7e6bf358
WD		 587 return 0;
588}
8f0b7cbe
WD		 589
590#ifdef CONFIG_VIDEO_SM501
591
6d3bc9b8
MB		 592#ifdef CONFIG_FO300
593#define DISPLAY_WIDTH 800
594#else
8f0b7cbe 595#define DISPLAY_WIDTH 640
6d3bc9b8 596#endif
8f0b7cbe
WD		 597#define DISPLAY_HEIGHT 480
598
599#ifdef CONFIG_VIDEO_SM501_8BPP
600#error CONFIG_VIDEO_SM501_8BPP not supported.
601#endif /* CONFIG_VIDEO_SM501_8BPP */
602
603#ifdef CONFIG_VIDEO_SM501_16BPP
604#error CONFIG_VIDEO_SM501_16BPP not supported.
605#endif /* CONFIG_VIDEO_SM501_16BPP */
606#ifdef CONFIG_VIDEO_SM501_32BPP
607static const SMI_REGS init_regs [] =
608{
609#if 0 /* CRT only */
610 {0x00004, 0x0},
611 {0x00048, 0x00021807},
612 {0x0004C, 0x10090a01},
613 {0x00054, 0x1},
614 {0x00040, 0x00021807},
615 {0x00044, 0x10090a01},
616 {0x00054, 0x0},
617 {0x80200, 0x00010000},
618 {0x80204, 0x0},
619 {0x80208, 0x0A000A00},
620 {0x8020C, 0x02fa027f},
621 {0x80210, 0x004a028b},
622 {0x80214, 0x020c01df},
623 {0x80218, 0x000201e9},
624 {0x80200, 0x00013306},
625#else /* panel + CRT */
6d3bc9b8
MB		 626#ifdef CONFIG_FO300
627 {0x00004, 0x0},
628 {0x00048, 0x00021807},
629 {0x0004C, 0x301a0a01},
630 {0x00054, 0x1},
631 {0x00040, 0x00021807},
632 {0x00044, 0x091a0a01},
633 {0x00054, 0x0},
634 {0x80000, 0x0f013106},
635 {0x80004, 0xc428bb17},
636 {0x8000C, 0x00000000},
637 {0x80010, 0x0C800C80},
638 {0x80014, 0x03200000},
639 {0x80018, 0x01e00000},
640 {0x8001C, 0x00000000},
641 {0x80020, 0x01e00320},
642 {0x80024, 0x042a031f},
643 {0x80028, 0x0086034a},
644 {0x8002C, 0x020c01df},
645 {0x80030, 0x000201ea},
646 {0x80200, 0x00010000},
647#else
8f0b7cbe
WD		 648 {0x00004, 0x0},
649 {0x00048, 0x00021807},
650 {0x0004C, 0x091a0a01},
651 {0x00054, 0x1},
652 {0x00040, 0x00021807},
653 {0x00044, 0x091a0a01},
654 {0x00054, 0x0},
655 {0x80000, 0x0f013106},
656 {0x80004, 0xc428bb17},
657 {0x8000C, 0x00000000},
658 {0x80010, 0x0a000a00},
659 {0x80014, 0x02800000},
660 {0x80018, 0x01e00000},
661 {0x8001C, 0x00000000},
662 {0x80020, 0x01e00280},
663 {0x80024, 0x02fa027f},
664 {0x80028, 0x004a028b},
665 {0x8002C, 0x020c01df},
666 {0x80030, 0x000201e9},
667 {0x80200, 0x00010000},
6d3bc9b8 668#endif /* #ifdef CONFIG_FO300 */
8f0b7cbe
WD		 669#endif
670 {0, 0}
671};
672#endif /* CONFIG_VIDEO_SM501_32BPP */
673
674#ifdef CONFIG_CONSOLE_EXTRA_INFO
675/*
676 * Return text to be printed besides the logo.
677 */
678void video_get_info_str (int line_number, char *info)
679{
680 if (line_number == 1) {
cd65a3dc 681 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
6d3bc9b8 682#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
8f0b7cbe 683 } else if (line_number == 2) {
b87dfd28 684#if defined (CONFIG_STK52XX)
5078cce8 685 strcpy (info, " on a STK52xx carrier board");
b87dfd28
WD		 686#endif
687#if defined (CONFIG_TB5200)
5078cce8 688 strcpy (info, " on a TB5200 carrier board");
b87dfd28 689#endif
6d3bc9b8
MB		 690#if defined (CONFIG_FO300)
691 strcpy (info, " on a FO300 carrier board");
692#endif
8f0b7cbe
WD		 693#endif
694 }
695 else {
696 info [0] = '\0';
697 }
698}
699#endif
700
701/*
e8aa824e
WD		 702 * Returns SM501 register base address. First thing called in the
703 * driver. Checks if SM501 is physically present.
8f0b7cbe
WD		 704 */
705unsigned int board_video_init (void)
706{
e8aa824e
WD		 707 u16 save, tmp;
708 int restore, ret;
709
710 /*
711 * Check for Grafic Controller
712 */
713
714 /* save origianl FB content */
715 save = *(volatile u16 *)CFG_CS1_START;
716 restore = 1;
717
718 /* write test pattern to FB memory */
719 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
720 __asm__ volatile ("sync");
721 /*
722 * Put a different pattern on the data lines: otherwise they may float
723 * long enough to read back what we wrote.
724 */
725 tmp = *(volatile u16 *)CFG_FLASH_BASE;
726 if (tmp == 0xA5A5)
727 puts ("!! possible error in grafic controller detection\n");
728
729 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
730 /* no grafic controller found */
731 restore = 0;
732 ret = 0;
733 } else {
734 ret = SM501_MMIO_BASE;
735 }
736
737 if (restore) {
738 *(volatile u16 *)CFG_CS1_START = save;
739 __asm__ volatile ("sync");
740 }
741 return ret;
8f0b7cbe
WD		 742}
743
744/*
745 * Returns SM501 framebuffer address
746 */
747unsigned int board_video_get_fb (void)
748{
749 return SM501_FB_BASE;
750}
751
752/*
753 * Called after initializing the SM501 and before clearing the screen.
754 */
755void board_validate_screen (unsigned int base)
756{
757}
758
759/*
760 * Return a pointer to the initialization sequence.
761 */
762const SMI_REGS *board_get_regs (void)
763{
764 return init_regs;
765}
766
767int board_get_width (void)
768{
769 return DISPLAY_WIDTH;
770}
771
772int board_get_height (void)
773{
774 return DISPLAY_HEIGHT;
775}
776
777#endif /* CONFIG_VIDEO_SM501 */
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