[u-boot.git] / board / tqm5200 / tqm5200.c

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif

#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
		hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
		hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
		hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
		hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
			__builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */

	/* find RAM size using SDRAM CS1 only */
	sdram_start(0);
	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CFG_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CFG_RAMBOOT */

/*	return dramsize + dramsize2; */
	return dramsize;
}

#elif defined(CONFIG_MGT5100)

long int initdram (int board_type)
{
	ulong dramsize = 0;
#ifndef CFG_RAMBOOT
	ulong test1, test2;

	/* setup and enable SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;

	/* address select register */
	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	__asm__ volatile ("sync");

	/* find RAM size */
	sdram_start(0);
	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* set SDRAM end address according to size */
	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);

#else /* CFG_RAMBOOT */

	/* Retrieve amount of SDRAM available */
	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);

#endif /* CFG_RAMBOOT */

	return dramsize;
}

#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

int checkboard (void)
{
#if defined (CONFIG_TQM5200_AA)
	puts ("Board: TQM5200-AA (TQ-Systems GmbH)\n");
#elif defined (CONFIG_TQM5200_AB)
	puts ("Board: TQM5200-AB (TQ-Systems GmbH)\n");
#elif defined (CONFIG_TQM5200_AC)
	puts ("Board: TQM5200-AC (TQ-Systems GmbH)\n");
#elif defined (CONFIG_TQM5200)
	puts ("Board: TQM5200 (TQ-Systems GmbH)\n");
#endif
#if defined (CONFIG_STK52XX)
	puts ("       on a STK52XX baseboard\n");
#endif

	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
#if defined(CONFIG_MGT5100)
	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
#endif
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}


#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)

#if defined (CONFIG_MINIFAP)
#define SM501_POWER_MODE0_GATE		0x00000040UL
#define SM501_POWER_MODE1_GATE		0x00000048UL
#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
#define SM501_GPIO_DATA_HIGH		0x00010004UL
#define SM501_GPIO_51			0x00080000UL
#else
#define GPIO_PSC1_4	0x01000000UL
#endif

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

#if defined (CONFIG_MINIFAP)
	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */

	/* enable GPIO control (in both power modes) */
	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
		POWER_MODE_GATE_GPIO_PWM_I2C;
	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
		POWER_MODE_GATE_GPIO_PWM_I2C;
	/* configure GPIO51 as output */
	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
		SM501_GPIO_51;
#else
	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
#endif
}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

#if defined (CONFIG_MINIFAP)
	if (idereset) {
		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
			~SM501_GPIO_51;
	} else {
		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
			SM501_GPIO_51;
	}
#else
	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
	}
#endif
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */

#ifdef CONFIG_POST
/*
 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
 * is left open, no keypress is detected.
 */
int post_hotkeys_pressed(void)
{
	struct mpc5xxx_gpio *gpio;

	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;

	/*
	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
	 * CODEC or UART mode. Consumer IrDA should still be possible.
	 */
	gpio->port_config &= ~(0x07000000);
	gpio->port_config |=   0x03000000;

	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
	gpio->simple_gpioe |= 0x20000000;

	/* Configure GPIO_IRDA_1 as input */
	gpio->simple_ddr &= ~(0x20000000);

	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
}
#endif

#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)

void post_word_store (ulong a)
{
	volatile ulong *save_addr =
		(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);

	*save_addr = a;
}

ulong post_word_load (void)
{
	volatile ulong *save_addr =
		(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);

	return *save_addr;
}
#endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/

#ifdef CONFIG_PS2MULT
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
	ps2mult_early_init();
	return (0);
}
#endif
#endif /* CONFIG_PS2MULT */

#if defined(CONFIG_CS_AUTOCONF)
int last_stage_init (void)
{
	/*
	 * auto scan for really existing devices and re-set chip select
	 * configuration.
	 */
	u16 save, tmp;
	int restore;

	/*
	 * Check for SRAM and SRAM size
	 */

	/* save origianl SRAM content  */
	save = *(volatile u16 *)CFG_CS2_START;
	restore = 1;

	/* write test pattern to SRAM */
	*(volatile u16 *)CFG_CS2_START = 0xA5A5;
	__asm__ volatile ("sync");
	/*
	 * Put a different pattern on the data lines: otherwise they may float
	 * long enough to read back what we wrote.
	 */
	tmp = *(volatile u16 *)CFG_FLASH_BASE;
	if (tmp == 0xA5A5)
		puts ("!! possible error in SRAM detection\n");

	if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
		/* no SRAM at all, disable cs */
		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
		restore = 0;
		__asm__ volatile ("sync");
	}
	else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
		/* make sure that we access a mirrored address */
		*(volatile u16 *)CFG_CS2_START = 0x1111;
		__asm__ volatile ("sync");
		if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
			/* SRAM size = 512 kByte */
			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
								0x80000);
			__asm__ volatile ("sync");
			puts ("SRAM:  512 kB\n");
		}
		else
			puts ("!! possible error in SRAM detection\n");
	}
	else {
		puts ("SRAM:  1 MB\n");
	}
	/* restore origianl SRAM content  */
	if (restore) {
		*(volatile u16 *)CFG_CS2_START = save;
		__asm__ volatile ("sync");
	}

	/*
	 * Check for Grafic Controller
	 */

	/* save origianl FB content  */
	save = *(volatile u16 *)CFG_CS1_START;
	restore = 1;

	/* write test pattern to FB memory */
	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
	__asm__ volatile ("sync");
	/*
	 * Put a different pattern on the data lines: otherwise they may float
	 * long enough to read back what we wrote.
	 */
	tmp = *(volatile u16 *)CFG_FLASH_BASE;
	if (tmp == 0xA5A5)
		puts ("!! possible error in grafic controller detection\n");

	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
		/* no grafic controller at all, disable cs */
		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
		restore = 0;
		__asm__ volatile ("sync");
	}
	else {
		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
	}
	/* restore origianl FB content  */
	if (restore) {
		*(volatile u16 *)CFG_CS1_START = save;
		__asm__ volatile ("sync");
	}

	return 0;
}
#endif /* CONFIG_CS_AUTOCONF */
Commit	Line	Data
56523f12 WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* (C) Copyright 2004
	9	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
81050926	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56523f12 WD	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#include <common.h>
	31	#include <mpc5xxx.h>
	32	#include <pci.h>
	33
	34	#if defined(CONFIG_MPC5200_DDR)
	35	#include "mt46v16m16-75.h"
	36	#else
	37	#include "mt48lc16m16a2-75.h"
	38	#endif
7e6bf358 WD	39	#ifdef CONFIG_PS2MULT
	40	void ps2mult_early_init(void);
	41	#endif
56523f12 WD	42
	43	#ifndef CFG_RAMBOOT
	44	static void sdram_start (int hi_addr)
	45	{
	46	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	47
	48	/* unlock mode register */
	49	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \|
	50	hi_addr_bit;
	51	__asm__ volatile ("sync");
	52
	53	/* precharge all banks */
	54	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
	55	hi_addr_bit;
	56	__asm__ volatile ("sync");
	57
	58	#if SDRAM_DDR
	59	/* set mode register: extended mode */
	60	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	61	__asm__ volatile ("sync");
	62
	63	/* set mode register: reset DLL */
	64	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	65	__asm__ volatile ("sync");
	66	#endif
	67
	68	/* precharge all banks */
	69	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
	70	hi_addr_bit;
	71	__asm__ volatile ("sync");
	72
	73	/* auto refresh */
	74	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \|
	75	hi_addr_bit;
	76	__asm__ volatile ("sync");
	77
	78	/* set mode register */
	79	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	80	__asm__ volatile ("sync");
	81
	82	/* normal operation */
	83	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	84	__asm__ volatile ("sync");
	85	}
	86	#endif
	87
	88	/*
	89	* ATTENTION: Although partially referenced initdram does NOT make real use
81050926 WD	90	* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
81050926 WD	91	* is something else than 0x00000000.
56523f12 WD	92	*/
	93
	94	#if defined(CONFIG_MPC5200)
	95	long int initdram (int board_type)
	96	{
	97	ulong dramsize = 0;
	98	ulong dramsize2 = 0;
	99	#ifndef CFG_RAMBOOT
	100	ulong test1, test2;
	101
	102	/* setup SDRAM chip selects */
	103	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
	104	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
	105	__asm__ volatile ("sync");
	106
	107	/* setup config registers */
	108	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	109	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	110	__asm__ volatile ("sync");
	111
	112	#if SDRAM_DDR
	113	/* set tap delay */
	114	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	115	__asm__ volatile ("sync");
	116	#endif
	117
	118	/* find RAM size using SDRAM CS0 only */
	119	sdram_start(0);
	120	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	121	sdram_start(1);
	122	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	123	if (test1 > test2) {
	124	sdram_start(0);
	125	dramsize = test1;
	126	} else {
	127	dramsize = test2;
	128	}
	129
	130	/* memory smaller than 1MB is impossible */
	131	if (dramsize < (1 << 20)) {
	132	dramsize = 0;
	133	}
	134
	135	/* set SDRAM CS0 size according to the amount of RAM found */
	136	if (dramsize > 0) {
	137	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 +
	138	__builtin_ffs(dramsize >> 20) - 1;
	139	} else {
	140	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	141	}
	142
	143	/* let SDRAM CS1 start right after CS0 */
	144	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
	145
	146	/* find RAM size using SDRAM CS1 only */
	147	sdram_start(0);
	148	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
	149	sdram_start(1);
	150	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
	151	if (test1 > test2) {
	152	sdram_start(0);
	153	dramsize2 = test1;
	154	} else {
	155	dramsize2 = test2;
156	}
157
158	/* memory smaller than 1MB is impossible */
159	if (dramsize2 < (1 << 20)) {
160	dramsize2 = 0;
161	}
162
163	/* set SDRAM CS1 size according to the amount of RAM found */
164	if (dramsize2 > 0) {
165	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
166	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
167	} else {
168	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
169	}
170
171	#else /* CFG_RAMBOOT */
172
173	/* retrieve size of memory connected to SDRAM CS0 */
174	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
175	if (dramsize >= 0x13) {
176	dramsize = (1 << (dramsize - 0x13)) << 20;
177	} else {
178	dramsize = 0;
179	}
180
181	/* retrieve size of memory connected to SDRAM CS1 */
182	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
183	if (dramsize2 >= 0x13) {
184	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
185	} else {
186	dramsize2 = 0;
187	}
188
189	#endif /* CFG_RAMBOOT */
190
191	/* return dramsize + dramsize2; */
192	return dramsize;
193	}
194
195	#elif defined(CONFIG_MGT5100)
196
197	long int initdram (int board_type)
198	{
199	ulong dramsize = 0;
200	#ifndef CFG_RAMBOOT
201	ulong test1, test2;
202
203	/* setup and enable SDRAM chip selects */
204	(vu_long )MPC5XXX_SDRAM_START = 0x00000000;
205	(vu_long )MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
206	(vu_long )MPC5XXX_ADDECR \|= (1 << 22); /* Enable SDRAM */
207	__asm__ volatile ("sync");
208
209	/* setup config registers */
210	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
211	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
212
213	/* address select register */
214	(vu_long )MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
215	__asm__ volatile ("sync");
216
217	/* find RAM size */
218	sdram_start(0);
219	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
220	sdram_start(1);
221	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
222	if (test1 > test2) {
223	sdram_start(0);
224	dramsize = test1;
225	} else {
226	dramsize = test2;
227	}
228
229	/* set SDRAM end address according to size */
230	(vu_long )MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
231
232	#else /* CFG_RAMBOOT */
233
234	/* Retrieve amount of SDRAM available */
235	dramsize = (((vu_long )MPC5XXX_SDRAM_STOP + 1) << 15);
236
237	#endif /* CFG_RAMBOOT */
238
239	return dramsize;
240	}
241
242	#else
243	#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
244	#endif
245
246	int checkboard (void)
247	{
248	#if defined (CONFIG_TQM5200_AA)
249	puts ("Board: TQM5200-AA (TQ-Systems GmbH)\n");
7e6bf358	250	#elif defined (CONFIG_TQM5200_AB)
56523f12	251	puts ("Board: TQM5200-AB (TQ-Systems GmbH)\n");
7e6bf358	252	#elif defined (CONFIG_TQM5200_AC)
56523f12	253	puts ("Board: TQM5200-AC (TQ-Systems GmbH)\n");
7e6bf358 WD	254	#elif defined (CONFIG_TQM5200)
7e6bf358 WD	255	puts ("Board: TQM5200 (TQ-Systems GmbH)\n");
56523f12	256	#endif
7e6bf358 WD	257	#if defined (CONFIG_STK52XX)
	258	puts (" on a STK52XX baseboard\n");
	259	#endif
	260
56523f12 WD	261	return 0;
	262	}
	263
	264	void flash_preinit(void)
	265	{
	266	/*
	267	* Now, when we are in RAM, enable flash write
	268	* access for detection process.
	269	* Note that CS_BOOT cannot be cleared when
	270	* executing in flash.
	271	*/
	272	#if defined(CONFIG_MGT5100)
	273	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	274	(vu_long )MPC5XXX_ADDECR \|= (1 << 16); /* enable CS0 */
	275	#endif
	276	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	277	}
	278
	279
	280	#ifdef CONFIG_PCI
	281	static struct pci_controller hose;
	282
	283	extern void pci_mpc5xxx_init(struct pci_controller *);
	284
	285	void pci_init_board(void)
	286	{
	287	pci_mpc5xxx_init(&hose);
	288	}
	289	#endif
	290
	291	#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
	292
	293	#if defined (CONFIG_MINIFAP)
	294	#define SM501_POWER_MODE0_GATE 0x00000040UL
	295	#define SM501_POWER_MODE1_GATE 0x00000048UL
	296	#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
	297	#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
	298	#define SM501_GPIO_DATA_HIGH 0x00010004UL
	299	#define SM501_GPIO_51 0x00080000UL
	300	#else
	301	#define GPIO_PSC1_4 0x01000000UL
	302	#endif
	303
	304	void init_ide_reset (void)
	305	{
	306	debug ("init_ide_reset\n");
	307
	308	#if defined (CONFIG_MINIFAP)
	309	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
	310
	311	/* enable GPIO control (in both power modes) */
	312	(vu_long ) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) \|=
	313	POWER_MODE_GATE_GPIO_PWM_I2C;
	314	(vu_long ) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) \|=
	315	POWER_MODE_GATE_GPIO_PWM_I2C;
	316	/* configure GPIO51 as output */
	317	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) \|=
	318	SM501_GPIO_51;
	319	#else
	320	/* Configure PSC1_4 as GPIO output for ATA reset */
	321	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	322	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	323	#endif
	324	}
325
326	void ide_set_reset (int idereset)
327	{
328	debug ("ide_reset(%d)\n", idereset);
329
330	#if defined (CONFIG_MINIFAP)
331	if (idereset) {
332	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
333	~SM501_GPIO_51;
334	} else {
335	(vu_long ) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) \|=
336	SM501_GPIO_51;
337	}
338	#else
339	if (idereset) {
340	(vu_long ) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
341	} else {
342	(vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
343	}
344	#endif
345	}
346	#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
347
348	#ifdef CONFIG_POST
349	/*
350	* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
351	* is left open, no keypress is detected.
352	*/
353	int post_hotkeys_pressed(void)
354	{
355	struct mpc5xxx_gpio *gpio;
356
357	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
358
359	/*
360	* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
361	* CODEC or UART mode. Consumer IrDA should still be possible.
81050926	362	*/
56523f12 WD	363	gpio->port_config &= ~(0x07000000);
	364	gpio->port_config \|= 0x03000000;
	365
	366	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
	367	gpio->simple_gpioe \|= 0x20000000;
	368
	369	/* Configure GPIO_IRDA_1 as input */
	370	gpio->simple_ddr &= ~(0x20000000);
	371
	372	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
	373	}
	374	#endif
	375
	376	#if defined(CONFIG_POST) \|\| defined(CONFIG_LOGBUFFER)
	377
	378	void post_word_store (ulong a)
	379	{
	380	volatile ulong *save_addr =
	381	(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
	382
	383	*save_addr = a;
	384	}
	385
	386	ulong post_word_load (void)
	387	{
	388	volatile ulong *save_addr =
	389	(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
	390
	391	return *save_addr;
	392	}
56523f12	393	#endif /* CONFIG_POST \|\| CONFIG_LOGBUFFER*/
7e6bf358 WD	394
	395	#ifdef CONFIG_PS2MULT
	396	#ifdef CONFIG_BOARD_EARLY_INIT_R
	397	int board_early_init_r (void)
	398	{
	399	ps2mult_early_init();
	400	return (0);
	401	}
	402	#endif
	403	#endif /* CONFIG_PS2MULT */
	404
	405	#if defined(CONFIG_CS_AUTOCONF)
	406	int last_stage_init (void)
	407	{
	408	/*
	409	* auto scan for really existing devices and re-set chip select
	410	* configuration.
	411	*/
	412	u16 save, tmp;
	413	int restore;
	414
	415	/*
	416	* Check for SRAM and SRAM size
	417	*/
	418
	419	/* save origianl SRAM content */
	420	save = (volatile u16 )CFG_CS2_START;
	421	restore = 1;
efe2a4d5	422
7e6bf358 WD	423	/* write test pattern to SRAM */
	424	(volatile u16 )CFG_CS2_START = 0xA5A5;
	425	__asm__ volatile ("sync");
	426	/*
	427	* Put a different pattern on the data lines: otherwise they may float
	428	* long enough to read back what we wrote.
	429	*/
	430	tmp = (volatile u16 )CFG_FLASH_BASE;
	431	if (tmp == 0xA5A5)
	432	puts ("!! possible error in SRAM detection\n");
efe2a4d5	433
7e6bf358 WD	434	if ((volatile u16 )CFG_CS2_START != 0xA5A5) {
	435	/* no SRAM at all, disable cs */
	436	(vu_long )MPC5XXX_ADDECR &= ~(1 << 18);
	437	(vu_long )MPC5XXX_CS2_START = 0x0000FFFF;
	438	(vu_long )MPC5XXX_CS2_STOP = 0x0000FFFF;
	439	restore = 0;
	440	__asm__ volatile ("sync");
	441	}
	442	else if ((volatile u16 )(CFG_CS2_START + (1<<19)) == 0xA5A5) {
	443	/* make sure that we access a mirrored address */
	444	(volatile u16 )CFG_CS2_START = 0x1111;
	445	__asm__ volatile ("sync");
	446	if ((volatile u16 )(CFG_CS2_START + (1<<19)) == 0x1111) {
	447	/* SRAM size = 512 kByte */
efe2a4d5	448	(vu_long )MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
7e6bf358 WD	449	0x80000);
	450	__asm__ volatile ("sync");
	451	puts ("SRAM: 512 kB\n");
	452	}
	453	else
efe2a4d5	454	puts ("!! possible error in SRAM detection\n");
7e6bf358 WD	455	}
7e6bf358 WD	456	else {
efe2a4d5	457	puts ("SRAM: 1 MB\n");
7e6bf358 WD	458	}
	459	/* restore origianl SRAM content */
	460	if (restore) {
	461	(volatile u16 )CFG_CS2_START = save;
	462	__asm__ volatile ("sync");
	463	}
efe2a4d5 WD	464
efe2a4d5 WD	465	/*
7e6bf358 WD	466	* Check for Grafic Controller
	467	*/
	468
	469	/* save origianl FB content */
	470	save = (volatile u16 )CFG_CS1_START;
	471	restore = 1;
efe2a4d5	472
7e6bf358 WD	473	/* write test pattern to FB memory */
	474	(volatile u16 )CFG_CS1_START = 0xA5A5;
	475	__asm__ volatile ("sync");
	476	/*
	477	* Put a different pattern on the data lines: otherwise they may float
	478	* long enough to read back what we wrote.
	479	*/
	480	tmp = (volatile u16 )CFG_FLASH_BASE;
	481	if (tmp == 0xA5A5)
	482	puts ("!! possible error in grafic controller detection\n");
efe2a4d5	483
7e6bf358 WD	484	if ((volatile u16 )CFG_CS1_START != 0xA5A5) {
	485	/* no grafic controller at all, disable cs */
	486	(vu_long )MPC5XXX_ADDECR &= ~(1 << 17);
	487	(vu_long )MPC5XXX_CS1_START = 0x0000FFFF;
	488	(vu_long )MPC5XXX_CS1_STOP = 0x0000FFFF;
	489	restore = 0;
	490	__asm__ volatile ("sync");
	491	}
	492	else {
efe2a4d5	493	puts ("VGA: SMI501 (Voyager) with 8 MB\n");
7e6bf358 WD	494	}
	495	/* restore origianl FB content */
	496	if (restore) {
	497	(volatile u16 )CFG_CS1_START = save;
	498	__asm__ volatile ("sync");
	499	}
efe2a4d5	500
7e6bf358 WD	501	return 0;
	502	}
	503	#endif /* CONFIG_CS_AUTOCONF */