[people/ms/u-boot.git] / board / tqm85xx / tqm85xx.c

/*
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
#include <flash.h>

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[];	/* FLASH chips info */

void local_bus_init (void);
long int fixed_sdram (void);
ulong flash_get_size (ulong base, int banknum);

#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif

#ifdef CONFIG_CPM2
/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*            conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* PC17 */
	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   1,   0,   0,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*            conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};
#endif /*  CONFIG_CPM2 */

#define CASL_STRING1	"casl=xx"
#define CASL_STRING2	"casl="

static const int casl_table[] = { 20, 25, 30 };
#define	N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))

int cas_latency(void)
{
	char *s = getenv("serial#");
	int casl;
	int val;
	int i;

	casl = CONFIG_DDR_DEFAULT_CL;

	if (s != NULL) {
		if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
			    strlen(CASL_STRING2)) == 0) {
			val = simple_strtoul(s + strlen(s) - 2, NULL, 10);

			for (i=0; i<N_CASL; ++i) {
				if (val == casl_table[i]) {
					return val;
				}
			}
		}
	}

	return casl;
}

int checkboard (void)
{
	char *s = getenv("serial#");

	printf("Board: %s", CONFIG_BOARDNAME);
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

#ifdef CONFIG_PCI
	printf ("PCI1:  32 bit, %d MHz (compiled)\n",
		CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf ("PCI1:  disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	return 0;
}

int misc_init_r (void)
{
	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);

	/*
	 * Adjust flash start and offset to detected values
	 */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Check if boot FLASH isn't max size
	 */
	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
		memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
		memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);

		/*
		 * Re-check to get correct base address
		 */
		flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
	}

	/*
	 * Check if only one FLASH bank is available
	 */
	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
		memctl->or1 = 0;
		memctl->br1 = 0;

		/*
		 * Re-do flash protection upon new addresses
		 */
		flash_protect (FLAG_PROTECT_CLEAR,
			       gd->bd->bi_flashstart, 0xffffffff,
			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);

		/* Monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);

		/* Environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CFG_ENV_ADDR,
			       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);

		/* Redundant environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CFG_ENV_ADDR_REDUND,
			       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
	}

	return 0;
}

/*
 * Initialize Local Bus
 */
void local_bus_init (void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info (&sysinfo);
	clkdiv = lbc->lcrr & 0x0f;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
		lbc->ltedr = 0xa4c80000;	/* DK: !!! */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);	/* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr ();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);	/* DLL Enabled */
		udelay (200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm ("sync;isync;msync");
	}
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY |
				     PCI_COMMAND_MASTER}},
	{}
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc85xxads_config_table,
#endif
};

#endif /* CONFIG_PCI */


void pci_init_board (void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
	ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
	return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
Commit	Line	Data
f5c5ef4a	1	/*
d96f41e0 SR	2	* (C) Copyright 2005
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
f5c5ef4a WD	5	* Copyright 2004 Freescale Semiconductor.
	6	* (C) Copyright 2002,2003, Motorola Inc.
	7	* Xianghua Xiao, (X.Xiao@motorola.com)
	8	*
	9	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
f5c5ef4a WD	30	#include <common.h>
	31	#include <pci.h>
	32	#include <asm/processor.h>
	33	#include <asm/immap_85xx.h>
	34	#include <ioports.h>
	35	#include <spd.h>
d96f41e0	36	#include <flash.h>
f5c5ef4a	37
d87080b7 WD	38	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	39
d96f41e0	40	extern flash_info_t flash_info[]; /* FLASH chips info */
f5c5ef4a WD	41
	42	void local_bus_init (void);
	43	long int fixed_sdram (void);
f18e874a	44	ulong flash_get_size (ulong base, int banknum);
966083e9	45
bd3143f0 WD	46	#ifdef CONFIG_PS2MULT
	47	void ps2mult_early_init(void);
	48	#endif
f5c5ef4a	49
d96f41e0	50	#ifdef CONFIG_CPM2
f5c5ef4a WD	51	/*
	52	* I/O Port configuration table
	53	*
	54	* if conf is 1, then that port pin will be configured at boot time
	55	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	56	*/
	57
	58	const iop_conf_t iop_conf_tab[4][32] = {
	59
	60	/* Port A configuration */
	61	{ /* conf ppar psor pdir podr pdat */
d96f41e0 SR	62	/* PA31 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII COL */
	63	/* PA30 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII CRS */
	64	/* PA29 / { 1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_ER */
	65	/* PA28 / { 1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_EN */
	66	/* PA27 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_DV */
	67	/* PA26 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_ER */
f5c5ef4a WD	68	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	69	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	70	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
	71	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
d96f41e0 SR	72	/* PA21 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[3] */
	73	/* PA20 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[2] */
	74	/* PA19 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[1] */
	75	/* PA18 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[0] */
	76	/* PA17 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[0] */
	77	/* PA16 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[1] */
	78	/* PA15 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[2] */
	79	/* PA14 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[3] */
f5c5ef4a WD	80	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
	81	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
	82	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
	83	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
	84	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
	85	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
	86	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	87	/* PA6 / { 0, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
	88	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	89	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	90	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	91	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	92	/* PA1 / { 0, 0, 0, 0, 0, 0 }, / FREERUN */
	93	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	94	},
	95
	96	/* Port B configuration */
	97	{ /* conf ppar psor pdir podr pdat */
d96f41e0 SR	98	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	99	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	100	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	101	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	102	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	103	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	104	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	105	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	106	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	107	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	108	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	109	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	110	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	111	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
f5c5ef4a WD	112	/* PB17 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
	113	/* PB16 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
	114	/* PB15 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
	115	/* PB14 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
	116	/* PB13 / { 1, 1, 0, 0, 0, 0 }, / FCC3:COL */
	117	/* PB12 / { 1, 1, 0, 0, 0, 0 }, / FCC3:CRS */
	118	/* PB11 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	119	/* PB10 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	120	/* PB9 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	121	/* PB8 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	122	/* PB7 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
	123	/* PB6 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
	124	/* PB5 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
	125	/* PB4 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
	126	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	127	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	128	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	129	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
	130	},
	131
	132	/* Port C */
	133	{ /* conf ppar psor pdir podr pdat */
	134	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
	135	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
	136	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
	137	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
	138	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
	139	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
	140	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
	141	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
	142	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
	143	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
d96f41e0 SR	144	/* PC21 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
	145	/* PC20 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
	146	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
f5c5ef4a WD	147	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
f5c5ef4a WD	148	/* PC17 / { 1, 1, 0, 0, 0, 0 }, / PC17 */
d96f41e0	149	/* PC16 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
f5c5ef4a WD	150	/* PC15 / { 0, 1, 0, 0, 0, 0 }, / PC15 */
	151	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
	152	/* PC13 / { 0, 1, 0, 0, 0, 0 }, / PC13 */
	153	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
	154	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
	155	/* PC10 / { 0, 0, 0, 1, 0, 0 }, / FETHMDC */
	156	/* PC9 / { 0, 0, 0, 0, 0, 0 }, / FETHMDIO */
	157	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
	158	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
	159	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
	160	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
	161	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
	162	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
	163	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
	164	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
	165	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
	166	},
	167
	168	/* Port D */
	169	{ /* conf ppar psor pdir podr pdat */
	170	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
	171	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
	172	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
	173	/* PD28 / { 1, 1, 0, 0, 0, 0 }, / PD28 */
	174	/* PD27 / { 1, 1, 0, 1, 0, 0 }, / PD27 */
	175	/* PD26 / { 1, 1, 0, 1, 0, 0 }, / PD26 */
	176	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
	177	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
	178	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
	179	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
	180	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
	181	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
	182	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
	183	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
	184	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
	185	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
	186	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
	187	/* PD14 / { 0, 0, 0, 1, 0, 0 }, / LED */
	188	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
	189	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
	190	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
	191	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
	192	/* PD9 / { 0, 1, 0, 1, 0, 0 }, / SMC1 TXD */
	193	/* PD8 / { 0, 1, 0, 0, 0, 0 }, / SMC1 RXD */
	194	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
	195	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
	196	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
	197	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
	198	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	199	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	200	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	201	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
	202	}
	203	};
d96f41e0 SR	204	#endif /* CONFIG_CPM2 */
	205
	206	#define CASL_STRING1 "casl=xx"
	207	#define CASL_STRING2 "casl="
f5c5ef4a	208
d96f41e0 SR	209	static const int casl_table[] = { 20, 25, 30 };
d96f41e0 SR	210	#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
f5c5ef4a	211
d96f41e0	212	int cas_latency(void)
f5c5ef4a	213	{
d96f41e0 SR	214	char *s = getenv("serial#");
	215	int casl;
	216	int val;
	217	int i;
	218
	219	casl = CONFIG_DDR_DEFAULT_CL;
	220
	221	if (s != NULL) {
	222	if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
	223	strlen(CASL_STRING2)) == 0) {
	224	val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
	225
	226	for (i=0; i<N_CASL; ++i) {
	227	if (val == casl_table[i]) {
	228	return val;
	229	}
	230	}
	231	}
	232	}
	233
	234	return casl;
f5c5ef4a WD	235	}
	236
	237	int checkboard (void)
	238	{
d96f41e0 SR	239	char *s = getenv("serial#");
	240
	241	printf("Board: %s", CONFIG_BOARDNAME);
	242	if (s != NULL) {
	243	puts(", serial# ");
	244	puts(s);
	245	}
	246	putc('\n');
f5c5ef4a WD	247
	248	#ifdef CONFIG_PCI
	249	printf ("PCI1: 32 bit, %d MHz (compiled)\n",
	250	CONFIG_SYS_CLK_FREQ / 1000000);
	251	#else
	252	printf ("PCI1: disabled\n");
	253	#endif
d96f41e0	254
f5c5ef4a WD	255	/*
	256	* Initialize local bus.
	257	*/
	258	local_bus_init ();
	259
	260	return 0;
	261	}
	262
d96f41e0	263	int misc_init_r (void)
f5c5ef4a	264	{
04db4008	265	volatile ccsr_lbc_t memctl = (void )(CFG_MPC85xx_LBC_ADDR);
f5c5ef4a	266
d96f41e0 SR	267	/*
	268	* Adjust flash start and offset to detected values
	269	*/
	270	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	271	gd->bd->bi_flashoffset = 0;
9d2a873b	272
d96f41e0 SR	273	/*
	274	* Check if boot FLASH isn't max size
	275	*/
	276	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
	277	memctl->or0 = gd->bd->bi_flashstart \| (CFG_OR0_PRELIM & 0x00007fff);
	278	memctl->br0 = gd->bd->bi_flashstart \| (CFG_BR0_PRELIM & 0x00007fff);
f5c5ef4a WD	279
f5c5ef4a WD	280	/*
d96f41e0	281	* Re-check to get correct base address
f5c5ef4a	282	*/
d96f41e0	283	flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
f5c5ef4a	284	}
f5c5ef4a	285
f5c5ef4a	286	/*
d96f41e0	287	* Check if only one FLASH bank is available
f5c5ef4a	288	*/
d96f41e0 SR	289	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
	290	memctl->or1 = 0;
	291	memctl->br1 = 0;
f5c5ef4a	292
d96f41e0 SR	293	/*
	294	* Re-do flash protection upon new addresses
	295	*/
	296	flash_protect (FLAG_PROTECT_CLEAR,
	297	gd->bd->bi_flashstart, 0xffffffff,
	298	&flash_info[CFG_MAX_FLASH_BANKS - 1]);
	299
	300	/* Monitor protection ON by default */
	301	flash_protect (FLAG_PROTECT_SET,
79b4cda0	302	CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
d96f41e0 SR	303	&flash_info[CFG_MAX_FLASH_BANKS - 1]);
	304
	305	/* Environment protection ON by default */
	306	flash_protect (FLAG_PROTECT_SET,
	307	CFG_ENV_ADDR,
	308	CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
	309	&flash_info[CFG_MAX_FLASH_BANKS - 1]);
	310
	311	/* Redundant environment protection ON by default */
	312	flash_protect (FLAG_PROTECT_SET,
	313	CFG_ENV_ADDR_REDUND,
	314	CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
	315	&flash_info[CFG_MAX_FLASH_BANKS - 1]);
	316	}
f5c5ef4a	317
d96f41e0 SR	318	return 0;
d96f41e0 SR	319	}
f5c5ef4a WD	320
	321	/*
	322	* Initialize Local Bus
	323	*/
f5c5ef4a WD	324	void local_bus_init (void)
f5c5ef4a WD	325	{
f59b55a5	326	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
04db4008	327	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
f5c5ef4a WD	328
	329	uint clkdiv;
	330	uint lbc_hz;
	331	sys_info_t sysinfo;
	332
	333	/*
	334	* Errata LBC11.
	335	* Fix Local Bus clock glitch when DLL is enabled.
	336	*
	337	* If localbus freq is < 66Mhz, DLL bypass mode must be used.
	338	* If localbus freq is > 133Mhz, DLL can be safely enabled.
	339	* Between 66 and 133, the DLL is enabled with an override workaround.
	340	*/
	341
	342	get_sys_info (&sysinfo);
	343	clkdiv = lbc->lcrr & 0x0f;
	344	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	345
	346	if (lbc_hz < 66) {
	347	lbc->lcrr = CFG_LBC_LCRR \| 0x80000000; /* DLL Bypass */
	348	lbc->ltedr = 0xa4c80000; /* DK: !!! */
	349
	350	} else if (lbc_hz >= 133) {
	351	lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
	352
	353	} else {
	354	/*
	355	* On REV1 boards, need to change CLKDIV before enable DLL.
	356	* Default CLKDIV is 8, change it to 4 temporarily.
	357	*/
	358	uint pvr = get_pvr ();
	359	uint temp_lbcdll = 0;
	360
	361	if (pvr == PVR_85xx_REV1) {
	362	/* FIXME: Justify the high bit here. */
	363	lbc->lcrr = 0x10000004;
	364	}
	365
	366	lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
	367	udelay (200);
	368
	369	/*
	370	* Sample LBC DLL ctrl reg, upshift it to set the
	371	* override bits.
	372	*/
	373	temp_lbcdll = gur->lbcdllcr;
	374	gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) \| 0x80000000);
	375	asm ("sync;isync;msync");
	376	}
	377	}
	378
f5c5ef4a WD	379	#if defined(CONFIG_PCI)
	380	/*
	381	* Initialize PCI Devices, report devices found.
	382	*/
	383
	384	#ifndef CONFIG_PCI_PNP
	385	static struct pci_config_table pci_mpc85xxads_config_table[] = {
	386	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	387	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	388	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	389	PCI_ENET0_MEMADDR,
	390	PCI_COMMAND_MEMORY \|
	391	PCI_COMMAND_MASTER}},
	392	{}
	393	};
	394	#endif
	395
	396
	397	static struct pci_controller hose = {
	398	#ifndef CONFIG_PCI_PNP
	399	config_table:pci_mpc85xxads_config_table,
	400	#endif
	401	};
	402
	403	#endif /* CONFIG_PCI */
	404
	405
	406	void pci_init_board (void)
	407	{
	408	#ifdef CONFIG_PCI
f5c5ef4a WD	409	pci_mpc85xx_init (&hose);
	410	#endif /* CONFIG_PCI */
	411	}
bc8bb6d4 WD	412
	413	#ifdef CONFIG_BOARD_EARLY_INIT_R
	414	int board_early_init_r (void)
	415	{
	416	#ifdef CONFIG_PS2MULT
	417	ps2mult_early_init();
	418	#endif /* CONFIG_PS2MULT */
	419	return (0);
	420	}
	421	#endif /* CONFIG_BOARD_EARLY_INIT_R */