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Commit | Line | Data |
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5e5803e1 SB |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefano Babic, DENX Gmbh, sbabic@denx.de | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
10 | * | |
11 | * (C) Copyright 2002 | |
12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
13 | * Marius Groeger <mgroeger@sysgo.de> | |
14 | * | |
15 | * See file CREDITS for list of people who contributed to this | |
16 | * project. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License as | |
20 | * published by the Free Software Foundation; either version 2 of | |
21 | * the License, or (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
31 | * MA 02111-1307 USA | |
32 | */ | |
33 | ||
34 | #include <common.h> | |
35 | #include <asm/arch/pxa-regs.h> | |
4438a45f | 36 | #include <asm/arch/pxa.h> |
60f61e6d | 37 | #include <netdev.h> |
3ba8bf7c | 38 | #include <asm/io.h> |
5e5803e1 SB |
39 | |
40 | DECLARE_GLOBAL_DATA_PTR; | |
41 | ||
42 | #define RH_A_PSM (1 << 8) /* power switching mode */ | |
43 | #define RH_A_NPS (1 << 9) /* no power switching */ | |
44 | ||
45 | extern struct serial_device serial_ffuart_device; | |
46 | extern struct serial_device serial_btuart_device; | |
47 | extern struct serial_device serial_stuart_device; | |
48 | ||
7c957c0e | 49 | #if CONFIG_MK_POLARIS |
040f8f63 SB |
50 | #define BOOT_CONSOLE "serial_stuart" |
51 | #else | |
52 | #define BOOT_CONSOLE "serial_ffuart" | |
53 | #endif | |
5e5803e1 SB |
54 | /* ------------------------------------------------------------------------- */ |
55 | ||
56 | /* | |
57 | * Miscelaneous platform dependent initialisations | |
58 | */ | |
59 | ||
88bd9750 | 60 | int usb_board_init(void) |
5e5803e1 | 61 | { |
3ba8bf7c MV |
62 | writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & |
63 | ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), | |
64 | UHCHR); | |
5e5803e1 | 65 | |
3ba8bf7c | 66 | writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
5e5803e1 | 67 | |
3ba8bf7c MV |
68 | while (readl(UHCHR) & UHCHR_FSBIR) |
69 | ; | |
5e5803e1 | 70 | |
3ba8bf7c MV |
71 | writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); |
72 | writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); | |
5e5803e1 SB |
73 | |
74 | /* Clear any OTG Pin Hold */ | |
3ba8bf7c MV |
75 | if (readl(PSSR) & PSSR_OTGPH) |
76 | writel(readl(PSSR) | PSSR_OTGPH, PSSR); | |
5e5803e1 | 77 | |
3ba8bf7c MV |
78 | writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA); |
79 | writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA); | |
5e5803e1 SB |
80 | |
81 | /* Set port power control mask bits, only 3 ports. */ | |
3ba8bf7c | 82 | writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); |
88bd9750 SB |
83 | |
84 | return 0; | |
5e5803e1 SB |
85 | } |
86 | ||
87 | void usb_board_init_fail(void) | |
88 | { | |
89 | return; | |
90 | } | |
91 | ||
92 | void usb_board_stop(void) | |
93 | { | |
3ba8bf7c | 94 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
5e5803e1 | 95 | udelay(11); |
3ba8bf7c | 96 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
5e5803e1 | 97 | |
3ba8bf7c | 98 | writel(readl(UHCCOMS) | 1, UHCCOMS); |
5e5803e1 SB |
99 | udelay(10); |
100 | ||
3ba8bf7c | 101 | writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
5e5803e1 | 102 | |
5e5803e1 SB |
103 | return; |
104 | } | |
105 | ||
106 | int board_init (void) | |
107 | { | |
cc72ac66 MV |
108 | /* We have RAM, disable cache */ |
109 | dcache_disable(); | |
110 | icache_disable(); | |
5e5803e1 SB |
111 | |
112 | /* arch number of ConXS Board */ | |
113 | gd->bd->bi_arch_number = 776; | |
114 | ||
115 | /* adress of boot parameters */ | |
116 | gd->bd->bi_boot_params = 0xa000003c; | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | int board_late_init(void) | |
122 | { | |
123 | #if defined(CONFIG_SERIAL_MULTI) | |
124 | char *console=getenv("boot_console"); | |
125 | ||
040f8f63 SB |
126 | if ((console == NULL) || (strcmp(console,"serial_btuart") && |
127 | strcmp(console,"serial_stuart") && | |
128 | strcmp(console,"serial_ffuart"))) { | |
129 | console = BOOT_CONSOLE; | |
5e5803e1 | 130 | } |
040f8f63 SB |
131 | setenv("stdout",console); |
132 | setenv("stdin", console); | |
133 | setenv("stderr",console); | |
5e5803e1 SB |
134 | #endif |
135 | return 0; | |
136 | } | |
137 | ||
cc72ac66 MV |
138 | int dram_init(void) |
139 | { | |
f68d2a22 | 140 | pxa2xx_dram_init(); |
cc72ac66 MV |
141 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
142 | return 0; | |
143 | } | |
144 | ||
145 | void dram_init_banksize(void) | |
5e5803e1 SB |
146 | { |
147 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
148 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
5e5803e1 | 149 | } |
60f61e6d RB |
150 | |
151 | #ifdef CONFIG_DRIVER_DM9000 | |
152 | int board_eth_init(bd_t *bis) | |
153 | { | |
154 | return dm9000_initialize(bis); | |
155 | } | |
156 | #endif |