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71a988aa TK |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Stefano Babic DENX Software Engineering sbabic@denx.de. | |
4 | * | |
5 | * (C) Copyright 2010 | |
6 | * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
71a988aa | 9 | * |
b1e6c4c3 | 10 | * Refer doc/README.imximage for more details about how-to configure |
71a988aa TK |
11 | * and create imximage boot image |
12 | * | |
13 | * The syntax is taken as close as possible with the kwbimage | |
14 | */ | |
15 | ||
16 | /* | |
17 | * Boot Device : one of | |
18 | * spi, nand, onenand, sd | |
19 | */ | |
f8f8acd7 SB |
20 | BOOT_FROM spi |
21 | ||
71a988aa TK |
22 | /* |
23 | * Device Configuration Data (DCD) | |
24 | * | |
25 | * Each entry must have the format: | |
26 | * Addr-type Address Value | |
27 | * | |
28 | * where: | |
29 | * Addr-type register length (1,2 or 4 bytes) | |
30 | * Address absolute address of the register | |
31 | * value value to be stored in the register | |
32 | */ | |
33 | ||
34 | /* | |
35 | * ####################### | |
36 | * ### Disable WDOG ### | |
37 | * ####################### | |
38 | */ | |
f8f8acd7 SB |
39 | DATA 2 0x73f98000 0x30 |
40 | ||
71a988aa TK |
41 | /* |
42 | * ####################### | |
43 | * ### SET DDR Clk ### | |
44 | * ####################### | |
45 | */ | |
46 | /* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */ | |
f8f8acd7 SB |
47 | DATA 4 0x73FD4018 0x000024C0 |
48 | ||
71a988aa | 49 | /* DOUBLE SPI CLK (13MHz->26 MHz Clock) */ |
f8f8acd7 SB |
50 | DATA 4 0x73FD4038 0x2010241 |
51 | ||
71a988aa | 52 | /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */ |
f8f8acd7 | 53 | DATA 4 0x73fa8600 0x00000107 |
71a988aa | 54 | /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */ |
f8f8acd7 | 55 | DATA 4 0x73fa8604 0x00000107 |
71a988aa | 56 | /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ |
f8f8acd7 | 57 | DATA 4 0x73fa8608 0x00000187 |
71a988aa | 58 | /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ |
f8f8acd7 | 59 | DATA 4 0x73fa860c 0x00000187 |
71a988aa | 60 | /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */ |
f8f8acd7 | 61 | DATA 4 0x73fa8614 0x00000107 |
71a988aa | 62 | /* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */ |
f8f8acd7 SB |
63 | DATA 4 0x73fa86a8 0x00000187 |
64 | ||
71a988aa TK |
65 | /* |
66 | * ####################### | |
67 | * ### Settings IOMUXC ### | |
68 | * ####################### | |
69 | */ | |
70 | /* | |
71 | * DDR IOMUX configuration | |
72 | * Control, Data, Address pads are in their default state: HIGH DS, FAST SR. | |
73 | * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS | |
74 | */ | |
f8f8acd7 | 75 | DATA 4 0x73fa84b8 0x000000e7 |
71a988aa TK |
76 | /* PVTC MAX (at GPC, PGR reg) */ |
77 | /* DATA 4 0x73FD8004 0x1fc00000 */ | |
f8f8acd7 | 78 | |
71a988aa | 79 | /* DQM0 DS high slew rate slow */ |
f8f8acd7 | 80 | DATA 4 0x73fa84d4 0x000000e4 |
71a988aa | 81 | /* DQM1 DS high slew rate slow */ |
f8f8acd7 | 82 | DATA 4 0x73fa84d8 0x000000e4 |
71a988aa | 83 | /* DQM2 DS high slew rate slow */ |
f8f8acd7 | 84 | DATA 4 0x73fa84dc 0x000000e4 |
71a988aa | 85 | /* DQM3 DS high slew rate slow */ |
f8f8acd7 SB |
86 | DATA 4 0x73fa84e0 0x000000e4 |
87 | ||
71a988aa | 88 | /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */ |
f8f8acd7 | 89 | DATA 4 0x73fa84bc 0x000000c4 |
71a988aa | 90 | /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */ |
f8f8acd7 | 91 | DATA 4 0x73fa84c0 0x000000c4 |
71a988aa | 92 | /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */ |
f8f8acd7 | 93 | DATA 4 0x73fa84c4 0x000000c4 |
71a988aa | 94 | /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */ |
f8f8acd7 SB |
95 | DATA 4 0x73fa84c8 0x000000c4 |
96 | ||
71a988aa | 97 | /* DRAM_DATA B0 */ |
f8f8acd7 | 98 | DATA 4 0x73fa88a4 0x00000004 |
71a988aa | 99 | /* DRAM_DATA B1 */ |
f8f8acd7 | 100 | DATA 4 0x73fa88ac 0x00000004 |
71a988aa | 101 | /* DRAM_DATA B2 */ |
f8f8acd7 | 102 | DATA 4 0x73fa88b8 0x00000004 |
71a988aa | 103 | /* DRAM_DATA B3 */ |
f8f8acd7 SB |
104 | DATA 4 0x73fa882c 0x00000004 |
105 | ||
71a988aa | 106 | /* DRAM_DATA B0 slew rate */ |
f8f8acd7 | 107 | DATA 4 0x73fa8878 0x00000000 |
71a988aa | 108 | /* DRAM_DATA B1 slew rate */ |
f8f8acd7 | 109 | DATA 4 0x73fa8880 0x00000000 |
71a988aa | 110 | /* DRAM_DATA B2 slew rate */ |
f8f8acd7 | 111 | DATA 4 0x73fa888c 0x00000000 |
71a988aa | 112 | /* DRAM_DATA B3 slew rate */ |
f8f8acd7 SB |
113 | DATA 4 0x73fa889c 0x00000000 |
114 | ||
71a988aa TK |
115 | /* |
116 | * ####################### | |
117 | * ### Configure SDRAM ### | |
118 | * ####################### | |
119 | */ | |
f8f8acd7 | 120 | |
71a988aa TK |
121 | /* Configure CS0 */ |
122 | /* ####################### */ | |
f8f8acd7 | 123 | |
71a988aa | 124 | /* ESDCTL0: Enable controller */ |
f8f8acd7 SB |
125 | DATA 4 0x83fd9000 0x83220000 |
126 | ||
c84f9e0d | 127 | /* Init DRAM on CS0 */ |
71a988aa | 128 | /* ESDSCR: Precharge command */ |
f8f8acd7 | 129 | DATA 4 0x83fd9014 0x04008008 |
71a988aa | 130 | /* ESDSCR: Refresh command */ |
f8f8acd7 | 131 | DATA 4 0x83fd9014 0x00008010 |
71a988aa | 132 | /* ESDSCR: Refresh command */ |
f8f8acd7 | 133 | DATA 4 0x83fd9014 0x00008010 |
71a988aa | 134 | /* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ |
f8f8acd7 | 135 | DATA 4 0x83fd9014 0x00338018 |
71a988aa | 136 | /* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ |
f8f8acd7 | 137 | DATA 4 0x83fd9014 0x0020801a |
71a988aa | 138 | /* ESDSCR */ |
f8f8acd7 SB |
139 | DATA 4 0x83fd9014 0x00008000 |
140 | ||
71a988aa TK |
141 | /* ESDSCR: EMR with full Drive strength */ |
142 | /* DATA 4 0x83fd9014 0x0000801a */ | |
f8f8acd7 | 143 | |
71a988aa | 144 | /* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */ |
f8f8acd7 SB |
145 | DATA 4 0x83fd9000 0xC3220000 |
146 | ||
71a988aa TK |
147 | /* |
148 | * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks | |
149 | * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks | |
150 | * DATA 4 0x83fd9004 0xC33574AA | |
151 | */ | |
152 | /* | |
153 | * micron mDDR | |
154 | * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks | |
155 | * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks | |
156 | * DATA 4 0x83FD9004 0x101564a8 | |
157 | */ | |
158 | /* | |
159 | * hynix mDDR | |
160 | * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks | |
161 | * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks | |
162 | */ | |
f8f8acd7 SB |
163 | DATA 4 0x83FD9004 0x704564a8 |
164 | ||
71a988aa | 165 | /* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */ |
f8f8acd7 SB |
166 | DATA 4 0x83fd9010 0x000a1700 |
167 | ||
71a988aa TK |
168 | /* Configure CS1 */ |
169 | /* ####################### */ | |
f8f8acd7 | 170 | |
71a988aa | 171 | /* ESDCTL1: Enable controller */ |
f8f8acd7 SB |
172 | DATA 4 0x83fd9008 0x83220000 |
173 | ||
71a988aa TK |
174 | /* Init DRAM on CS1 */ |
175 | /* ESDSCR: Precharge command */ | |
f8f8acd7 | 176 | DATA 4 0x83fd9014 0x0400800c |
71a988aa | 177 | /* ESDSCR: Refresh command */ |
f8f8acd7 | 178 | DATA 4 0x83fd9014 0x00008014 |
71a988aa | 179 | /* ESDSCR: Refresh command */ |
f8f8acd7 | 180 | DATA 4 0x83fd9014 0x00008014 |
71a988aa | 181 | /* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ |
f8f8acd7 | 182 | DATA 4 0x83fd9014 0x0033801c |
71a988aa | 183 | /* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ |
f8f8acd7 | 184 | DATA 4 0x83fd9014 0x0020801e |
71a988aa | 185 | /* ESDSCR */ |
f8f8acd7 SB |
186 | DATA 4 0x83fd9014 0x00008004 |
187 | ||
71a988aa | 188 | /* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */ |
f8f8acd7 | 189 | DATA 4 0x83fd9008 0xC3220000 |
71a988aa TK |
190 | /* |
191 | * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks | |
192 | * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks | |
193 | * DATA 4 0x83fd900c 0xC33574AA | |
194 | */ | |
195 | /* | |
196 | * micron mDDR | |
197 | * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks | |
198 | * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks | |
199 | * DATA 4 0x83FD900C 0x101564a8 | |
200 | */ | |
201 | /* | |
202 | * hynix mDDR | |
203 | * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks | |
204 | * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks | |
205 | */ | |
f8f8acd7 SB |
206 | DATA 4 0x83FD900C 0x704564a8 |
207 | ||
71a988aa | 208 | /* ESDSCR (mDRAM configuration finished) */ |
f8f8acd7 SB |
209 | DATA 4 0x83FD9014 0x00000004 |
210 | ||
71a988aa | 211 | /* ESDSCR - clear "configuration request" bit */ |
f8f8acd7 | 212 | DATA 4 0x83fd9014 0x00000000 |