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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Gregory E. Allen, gallen@arlut.utexas.edu | |
7 | * Matthew E. Karger, karger@arlut.utexas.edu | |
8 | * Applied Research Laboratories, The University of Texas at Austin | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
30 | #include <mpc824x.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/io.h> | |
7a8e9bed | 33 | #include <asm/mmu.h> |
c609719b WD |
34 | #include <pci.h> |
35 | ||
36 | #define SAVE_SZ 32 | |
37 | ||
38 | ||
39 | int checkboard(void) | |
40 | { | |
41 | ulong busfreq = get_bus_freq(0); | |
42 | char buf[32]; | |
43 | ||
44 | printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq)); | |
45 | return 0; | |
46 | } | |
47 | ||
48 | ||
49 | long int initdram(int board_type) | |
50 | { | |
51 | #if 1 | |
52 | int i, cnt; | |
53 | volatile uchar *base = CFG_SDRAM_BASE; | |
54 | volatile ulong *addr; | |
55 | ulong save[SAVE_SZ]; | |
56 | ulong val, ret = 0; | |
7a8e9bed WD |
57 | /* |
58 | write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP), | |
59 | ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE)); | |
60 | ||
61 | write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP), | |
62 | ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE)); | |
63 | */ | |
64 | for (i=0; i<SAVE_SZ; i++) { | |
65 | save[i] = 0; /* clear table */ | |
66 | } | |
c609719b | 67 | |
7a8e9bed | 68 | for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { |
c609719b WD |
69 | addr = (volatile ulong *)base + cnt; |
70 | save[i++] = *addr; | |
71 | *addr = ~cnt; | |
72 | } | |
73 | ||
74 | addr = (volatile ulong *)base; | |
75 | save[i] = *addr; | |
76 | *addr = 0; | |
77 | ||
7a8e9bed | 78 | if (*addr != 0) { |
c609719b WD |
79 | *addr = save[i]; |
80 | goto Done; | |
81 | } | |
82 | ||
7a8e9bed | 83 | for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) { |
c609719b WD |
84 | addr = (volatile ulong *)base + cnt; |
85 | val = *addr; | |
86 | *addr = save[--i]; | |
7a8e9bed | 87 | if (val != ~cnt) { |
c609719b WD |
88 | ulong new_bank0_end = cnt * sizeof(long) - 1; |
89 | ulong mear1 = mpc824x_mpc107_getreg(MEAR1); | |
90 | ulong emear1 = mpc824x_mpc107_getreg(EMEAR1); | |
91 | mear1 = (mear1 & 0xFFFFFF00) | | |
92 | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); | |
93 | emear1 = (emear1 & 0xFFFFFF00) | | |
94 | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); | |
95 | mpc824x_mpc107_setreg(MEAR1, mear1); | |
96 | mpc824x_mpc107_setreg(EMEAR1, emear1); | |
97 | ||
98 | ret = cnt * sizeof(long); | |
99 | goto Done; | |
100 | } | |
101 | } | |
102 | ||
103 | ret = CFG_MAX_RAM_SIZE; | |
104 | Done: | |
105 | return ret; | |
106 | #else | |
107 | return (CFG_MAX_RAM_SIZE); | |
108 | #endif | |
109 | ||
110 | } | |
111 | ||
112 | ||
113 | /* | |
114 | * Initialize PCI Devices, report devices found. | |
115 | */ | |
116 | ||
117 | static struct pci_config_table pci_utx8245_config_table[] = { | |
118 | #ifndef CONFIG_PCI_PNP | |
7a8e9bed | 119 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, |
c609719b WD |
120 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
121 | PCI_ENET0_MEMADDR, | |
122 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, | |
7a8e9bed | 123 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, |
c609719b WD |
124 | pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, |
125 | PCI_FIREWIRE_MEMADDR, | |
126 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, | |
127 | #endif /*CONFIG_PCI_PNP*/ | |
128 | { } | |
129 | }; | |
130 | ||
131 | ||
132 | static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev) | |
133 | { | |
134 | if (PCI_DEV(dev) == 11) | |
135 | /* assign serial interrupt line 9 (int25) to FireWire */ | |
136 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25); | |
137 | ||
138 | else if (PCI_DEV(dev) == 12) | |
139 | /* assign serial interrupt line 8 (int24) to Ethernet */ | |
140 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); | |
7a8e9bed WD |
141 | |
142 | else if (PCI_DEV(dev) == 14) | |
143 | /* assign serial interrupt line 0 (int16) to PMC slot 0 */ | |
144 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); | |
145 | ||
146 | else if (PCI_DEV(dev) == 15) | |
147 | /* assign serial interrupt line 1 (int17) to PMC slot 1 */ | |
148 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); | |
c609719b WD |
149 | } |
150 | ||
151 | static struct pci_controller utx8245_hose = { | |
152 | #ifndef CONFIG_PCI_PNP | |
153 | config_table: pci_utx8245_config_table, | |
154 | fixup_irq: pci_utx8245_fixup_irq, | |
155 | write_byte: pci_hose_write_config_byte | |
156 | #endif /*CONFIG_PCI_PNP*/ | |
157 | }; | |
158 | ||
ad10dd9a | 159 | void pci_init_board (void) |
c609719b WD |
160 | { |
161 | pci_mpc824x_init(&utx8245_hose); | |
162 | ||
163 | icache_enable(); | |
164 | } |