[people/ms/u-boot.git] / board / v38b / v38b.c

/*
 * (C) Copyright 2003-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <net.h>
#include <asm/processor.h>


#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif /* SDRAM_DDR */

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif /* !CONFIG_SYS_RAMBOOT */


phys_size_t initdram(int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;

#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif /* SDRAM_DDR */

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else
		dramsize = test2;

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20))
		dramsize = 0;

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0)
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	else
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else
		dramsize2 = test2;

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20))
		dramsize2 = 0;

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0)
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	else
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13)
		dramsize = (1 << (dramsize - 0x13)) << 20;
	else
		dramsize = 0;

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13)
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	else
		dramsize2 = 0;

#endif /* CONFIG_SYS_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) &&
		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {

		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
		__asm__ volatile ("sync");
	}

	return dramsize + dramsize2;
}


int checkboard (void)
{
	puts("Board: MarelV38B\n");
	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_HW_WATCHDOG
	/*
	 * Enable and configure the direction (output) of PSC3_9 - watchdog
	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
	 * Manual.
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
#endif /* CONFIG_HW_WATCHDOG */
	return 0;
}

int board_early_init_r(void)
{
	/*
	 * Now, when we are in RAM, enable flash write access for the
	 * detection process.  Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */

	/*
	 * Enable GPIO_WKUP_7 to "read the status of the actual power
	 * situation". Default direction is input, so no need to set it
	 * explicitly.
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
	return 0;
}

extern void board_get_enetaddr(uchar *enetaddr);
int misc_init_r(void)
{
	uchar enetaddr[6];

	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
		board_get_enetaddr(enetaddr);
		eth_setenv_enetaddr("ethaddr", enetaddr);
	}

	return 0;
}

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset(void)
{
	debug("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
	/* Deassert reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}


void ide_set_reset(int idereset)
{
	debug("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
		/* Make a delay. MPC5200 spec says 25 usec min */
		udelay(500000);
	} else
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
}
#endif


#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
	/*
	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
}
#endif /* CONFIG_HW_WATCHDOG */
Commit	Line	Data
4707fb50 BS	1	/*
	2	* (C) Copyright 2003-2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
76756e41	29	#include <net.h>
4707fb50 BS	30	#include <asm/processor.h>
4707fb50 BS	31
25721b5c	32
6d0f6bcf	33	#ifndef CONFIG_SYS_RAMBOOT
4707fb50 BS	34	static void sdram_start(int hi_addr)
	35	{
	36	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	37
	38	/* unlock mode register */
25721b5c	39	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
4707fb50 BS	40	__asm__ volatile ("sync");
	41
	42	/* precharge all banks */
25721b5c	43	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
4707fb50 BS	44	__asm__ volatile ("sync");
	45
	46	#if SDRAM_DDR
	47	/* set mode register: extended mode */
25721b5c	48	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
4707fb50 BS	49	__asm__ volatile ("sync");
	50
	51	/* set mode register: reset DLL */
25721b5c	52	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
4707fb50 BS	53	__asm__ volatile ("sync");
	54	#endif /* SDRAM_DDR */
	55
	56	/* precharge all banks */
25721b5c	57	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
4707fb50 BS	58	__asm__ volatile ("sync");
	59
	60	/* auto refresh */
25721b5c	61	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
4707fb50 BS	62	__asm__ volatile ("sync");
	63
	64	/* set mode register */
25721b5c	65	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
4707fb50 BS	66	__asm__ volatile ("sync");
	67
	68	/* normal operation */
25721b5c	69	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
4707fb50 BS	70	__asm__ volatile ("sync");
4707fb50 BS	71	}
6d0f6bcf	72	#endif /* !CONFIG_SYS_RAMBOOT */
4707fb50 BS	73
4707fb50 BS	74
9973e3c6	75	phys_size_t initdram(int board_type)
4707fb50 BS	76	{
	77	ulong dramsize = 0;
	78	ulong dramsize2 = 0;
	79	uint svr, pvr;
	80
6d0f6bcf	81	#ifndef CONFIG_SYS_RAMBOOT
4707fb50 BS	82	ulong test1, test2;
	83
	84	/* setup SDRAM chip selects */
25721b5c BS	85	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
25721b5c BS	86	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
4707fb50 BS	87	__asm__ volatile ("sync");
	88
	89	/* setup config registers */
25721b5c BS	90	(vu_long ) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
25721b5c BS	91	(vu_long ) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
4707fb50 BS	92	__asm__ volatile ("sync");
	93
	94	#if SDRAM_DDR
	95	/* set tap delay */
25721b5c	96	(vu_long ) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
4707fb50 BS	97	__asm__ volatile ("sync");
	98	#endif /* SDRAM_DDR */
	99
	100	/* find RAM size using SDRAM CS0 only */
	101	sdram_start(0);
6d0f6bcf	102	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
4707fb50	103	sdram_start(1);
6d0f6bcf	104	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
4707fb50 BS	105	if (test1 > test2) {
	106	sdram_start(0);
	107	dramsize = test1;
	108	} else
	109	dramsize = test2;
	110
	111	/* memory smaller than 1MB is impossible */
	112	if (dramsize < (1 << 20))
	113	dramsize = 0;
	114
	115	/* set SDRAM CS0 size according to the amount of RAM found */
	116	if (dramsize > 0)
25721b5c	117	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
4707fb50	118	else
25721b5c	119	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
4707fb50 BS	120
4707fb50 BS	121	/* let SDRAM CS1 start right after CS0 */
25721b5c	122	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
4707fb50 BS	123
	124	/* find RAM size using SDRAM CS1 only */
	125	if (!dramsize)
	126	sdram_start(0);
6d0f6bcf	127	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
4707fb50 BS	128	if (!dramsize) {
4707fb50 BS	129	sdram_start(1);
6d0f6bcf	130	test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
4707fb50 BS	131	}
	132	if (test1 > test2) {
	133	sdram_start(0);
	134	dramsize2 = test1;
	135	} else
	136	dramsize2 = test2;
	137
	138	/* memory smaller than 1MB is impossible */
	139	if (dramsize2 < (1 << 20))
	140	dramsize2 = 0;
	141
	142	/* set SDRAM CS1 size according to the amount of RAM found */
	143	if (dramsize2 > 0)
25721b5c	144	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize
4707fb50 BS	145	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
4707fb50 BS	146	else
25721b5c	147	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
4707fb50	148
6d0f6bcf	149	#else /* CONFIG_SYS_RAMBOOT */
4707fb50 BS	150
4707fb50 BS	151	/* retrieve size of memory connected to SDRAM CS0 */
25721b5c	152	dramsize = (vu_long ) MPC5XXX_SDRAM_CS0CFG & 0xFF;
4707fb50 BS	153	if (dramsize >= 0x13)
	154	dramsize = (1 << (dramsize - 0x13)) << 20;
	155	else
	156	dramsize = 0;
	157
	158	/* retrieve size of memory connected to SDRAM CS1 */
25721b5c	159	dramsize2 = (vu_long ) MPC5XXX_SDRAM_CS1CFG & 0xFF;
4707fb50 BS	160	if (dramsize2 >= 0x13)
	161	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	162	else
	163	dramsize2 = 0;
	164
6d0f6bcf	165	#endif /* CONFIG_SYS_RAMBOOT */
4707fb50 BS	166
	167	/*
	168	* On MPC5200B we need to set the special configuration delay in the
	169	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	170	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	171	*
	172	* "The SDelay should be written to a value of 0x00000004. It is
	173	* required to account for changes caused by normal wafer processing
	174	* parameters."
	175	*/
	176	svr = get_svr();
	177	pvr = get_pvr();
	178	if ((SVR_MJREV(svr) >= 2) &&
	179	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
	180
25721b5c	181	(vu_long ) MPC5XXX_SDRAM_SDELAY = 0x04;
4707fb50 BS	182	__asm__ volatile ("sync");
	183	}
	184
	185	return dramsize + dramsize2;
	186	}
	187
	188
	189	int checkboard (void)
	190	{
	191	puts("Board: MarelV38B\n");
	192	return 0;
	193	}
	194
cce4acbb	195	int board_early_init_f(void)
4707fb50	196	{
25721b5c BS	197	#ifdef CONFIG_HW_WATCHDOG
	198	/*
	199	* Enable and configure the direction (output) of PSC3_9 - watchdog
	200	* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
	201	* Manual.
	202	*/
	203	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC3_9;
	204	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC3_9;
	205	#endif /* CONFIG_HW_WATCHDOG */
cce4acbb BS	206	return 0;
	207	}
	208
	209	int board_early_init_r(void)
	210	{
	211	/*
	212	* Now, when we are in RAM, enable flash write access for the
	213	* detection process. Note that CS_BOOT cannot be cleared when
	214	* executing in flash.
	215	*/
	216	(vu_long ) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
25721b5c BS	217
	218	/*
	219	* Enable GPIO_WKUP_7 to "read the status of the actual power
	220	* situation". Default direction is input, so no need to set it
	221	* explicitly.
4707fb50	222	*/
25721b5c	223	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_WKUP_7;
4707fb50 BS	224	return 0;
	225	}
	226
d8d21e69 MF	227	extern void board_get_enetaddr(uchar *enetaddr);
	228	int misc_init_r(void)
	229	{
	230	uchar enetaddr[6];
	231
	232	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
	233	board_get_enetaddr(enetaddr);
76756e41	234	eth_setenv_enetaddr("ethaddr", enetaddr);
d8d21e69 MF	235	}
	236
	237	return 0;
	238	}
4707fb50	239
d39b5741	240	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
4707fb50 BS	241	void init_ide_reset(void)
	242	{
	243	debug("init_ide_reset\n");
	244
	245	/* Configure PSC1_4 as GPIO output for ATA reset */
	246	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
25721b5c	247	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
4707fb50	248	/* Deassert reset */
25721b5c	249	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
4707fb50 BS	250	}
	251
	252
	253	void ide_set_reset(int idereset)
	254	{
	255	debug("ide_reset(%d)\n", idereset);
	256
	257	if (idereset) {
25721b5c	258	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
4707fb50 BS	259	/* Make a delay. MPC5200 spec says 25 usec min */
	260	udelay(500000);
	261	} else
25721b5c	262	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
4707fb50	263	}
d39b5741	264	#endif
4707fb50 BS	265
4707fb50 BS	266
25721b5c	267	#ifdef CONFIG_HW_WATCHDOG
4707fb50 BS	268	void hw_watchdog_reset(void)
4707fb50 BS	269	{
25721b5c BS	270	/*
	271	* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
	272	* we need a positive or negative transition on WDI i.e., our PSC3_9.
	273	*/
	274	(vu_long ) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
4707fb50	275	}
25721b5c	276	#endif /* CONFIG_HW_WATCHDOG */