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1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 | |
3 | * | |
4 | * Author: Scott Wood <scottwood@freescale.com> | |
5 | * | |
6 | * (C) Copyright 2010 | |
7 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <libfdt.h> | |
30 | #include <pci.h> | |
31 | #include <mpc83xx.h> | |
32 | #include <ns16550.h> | |
33 | #include <nand.h> | |
34 | ||
35 | #include <asm/bitops.h> | |
36 | #include <asm/io.h> | |
37 | ||
38 | DECLARE_GLOBAL_DATA_PTR; | |
39 | ||
40 | extern void disable_addr_trans (void); | |
41 | extern void enable_addr_trans (void); | |
42 | ||
43 | int checkboard(void) | |
44 | { | |
45 | puts("Board: ve8313\n"); | |
46 | return 0; | |
47 | } | |
48 | ||
49 | static long fixed_sdram(void) | |
50 | { | |
51 | u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; | |
52 | ||
53 | #ifndef CONFIG_SYS_RAMBOOT | |
54 | volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; | |
55 | u32 msize_log2 = __ilog2(msize); | |
56 | ||
57 | out_be32(&im->sysconf.ddrlaw[0].bar, | |
58 | (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); | |
59 | out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); | |
60 | out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); | |
61 | ||
62 | /* | |
63 | * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], | |
64 | * or the DDR2 controller may fail to initialize correctly. | |
65 | */ | |
66 | __udelay(50000); | |
67 | ||
68 | out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); | |
69 | out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG); | |
70 | ||
71 | /* Currently we use only one CS, so disable the other bank. */ | |
72 | out_be32(&im->ddr.cs_config[1], 0); | |
73 | ||
74 | out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); | |
75 | out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); | |
76 | out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); | |
77 | out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); | |
78 | out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); | |
79 | ||
80 | out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); | |
81 | ||
82 | out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); | |
83 | out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); | |
84 | out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); | |
85 | ||
86 | out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); | |
87 | sync(); | |
88 | ||
89 | /* enable DDR controller */ | |
90 | setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); | |
91 | ||
92 | /* now check the real size */ | |
93 | disable_addr_trans (); | |
94 | msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); | |
95 | enable_addr_trans (); | |
96 | #endif | |
97 | ||
98 | return msize; | |
99 | } | |
100 | ||
101 | phys_size_t initdram(int board_type) | |
102 | { | |
103 | volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; | |
a2243b84 | 104 | volatile fsl_lbc_t *lbc = &im->im_lbc; |
4e43b2e8 HS |
105 | u32 msize; |
106 | ||
107 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) | |
108 | return -1; | |
109 | ||
110 | /* DDR SDRAM - Main SODIMM */ | |
111 | msize = fixed_sdram(); | |
112 | ||
113 | /* Local Bus setup lbcr and mrtpr */ | |
114 | out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); | |
115 | out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); | |
116 | sync(); | |
117 | ||
118 | /* return total bus SDRAM size(bytes) -- DDR */ | |
119 | return msize; | |
120 | } | |
121 | ||
122 | #define VE8313_WDT_EN 0x00020000 | |
123 | #define VE8313_WDT_TRIG 0x00040000 | |
124 | ||
125 | int board_early_init_f (void) | |
126 | { | |
127 | volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; | |
128 | volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; | |
129 | ||
130 | #if defined(CONFIG_HW_WATCHDOG) | |
131 | /* enable WDT */ | |
132 | clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); | |
133 | #else | |
134 | /* disable WDT */ | |
135 | setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); | |
136 | #endif | |
137 | /* set WDT pins as output */ | |
138 | setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG); | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | #if defined(CONFIG_HW_WATCHDOG) | |
144 | void hw_watchdog_reset(void) | |
145 | { | |
146 | volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; | |
147 | volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; | |
148 | unsigned long reg; | |
149 | ||
150 | reg = in_be32(&gpio->dat); | |
151 | if (reg & VE8313_WDT_TRIG) | |
152 | clrbits_be32(&gpio->dat, VE8313_WDT_TRIG); | |
153 | else | |
154 | setbits_be32(&gpio->dat, VE8313_WDT_TRIG); | |
155 | } | |
156 | #endif | |
157 | ||
158 | ||
159 | #if defined(CONFIG_PCI) | |
160 | static struct pci_region pci_regions[] = { | |
161 | { | |
162 | bus_start: CONFIG_SYS_PCI1_MEM_BASE, | |
163 | phys_start: CONFIG_SYS_PCI1_MEM_PHYS, | |
164 | size: CONFIG_SYS_PCI1_MEM_SIZE, | |
165 | flags: PCI_REGION_MEM | PCI_REGION_PREFETCH | |
166 | }, | |
167 | { | |
168 | bus_start: CONFIG_SYS_PCI1_MMIO_BASE, | |
169 | phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, | |
170 | size: CONFIG_SYS_PCI1_MMIO_SIZE, | |
171 | flags: PCI_REGION_MEM | |
172 | }, | |
173 | { | |
174 | bus_start: CONFIG_SYS_PCI1_IO_BASE, | |
175 | phys_start: CONFIG_SYS_PCI1_IO_PHYS, | |
176 | size: CONFIG_SYS_PCI1_IO_SIZE, | |
177 | flags: PCI_REGION_IO | |
178 | } | |
179 | }; | |
180 | ||
181 | void pci_init_board(void) | |
182 | { | |
183 | volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; | |
184 | volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; | |
185 | volatile law83xx_t *pci_law = immr->sysconf.pcilaw; | |
186 | struct pci_region *reg[] = { pci_regions }; | |
4e43b2e8 HS |
187 | |
188 | /* Enable all 3 PCI_CLK_OUTPUTs. */ | |
189 | setbits_be32(&clk->occr, 0xe0000000); | |
190 | ||
191 | /* | |
192 | * Configure PCI Local Access Windows | |
193 | */ | |
194 | out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR); | |
195 | out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); | |
196 | ||
197 | out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); | |
198 | out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB); | |
199 | ||
6aa3d3bf | 200 | mpc83xx_pci_init(1, reg); |
4e43b2e8 HS |
201 | } |
202 | #endif | |
203 | ||
204 | #if defined(CONFIG_OF_BOARD_SETUP) | |
205 | void ft_board_setup(void *blob, bd_t *bd) | |
206 | { | |
207 | ft_cpu_setup(blob, bd); | |
208 | #ifdef CONFIG_PCI | |
209 | ft_pci_setup(blob, bd); | |
210 | #endif | |
211 | } | |
212 | #endif |