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Commit | Line | Data |
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18a00dfd | 1 | /* |
f905432c | 2 | * Voipac PXA270 Support |
18a00dfd | 3 | * |
f905432c | 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
18a00dfd | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
18a00dfd MV |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/arch/hardware.h> | |
5d877f42 | 11 | #include <asm/arch/regs-mmc.h> |
4438a45f | 12 | #include <asm/arch/pxa.h> |
c7e61334 | 13 | #include <netdev.h> |
3ba8bf7c MV |
14 | #include <serial.h> |
15 | #include <asm/io.h> | |
18a00dfd MV |
16 | |
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
18a00dfd MV |
19 | /* |
20 | * Miscelaneous platform dependent initialisations | |
21 | */ | |
f905432c | 22 | int board_init(void) |
18a00dfd | 23 | { |
720a650c MV |
24 | /* We have RAM, disable cache */ |
25 | dcache_disable(); | |
26 | icache_disable(); | |
27 | ||
18a00dfd MV |
28 | /* memory and cpu-speed are setup before relocation */ |
29 | /* so we do _nothing_ here */ | |
30 | ||
f905432c | 31 | /* Arch number of vpac270 */ |
18a00dfd MV |
32 | gd->bd->bi_arch_number = MACH_TYPE_VPAC270; |
33 | ||
34 | /* adress of boot parameters */ | |
35 | gd->bd->bi_boot_params = 0xa0000100; | |
36 | ||
37 | return 0; | |
38 | } | |
39 | ||
f905432c | 40 | int dram_init(void) |
6ef6eb91 | 41 | { |
411b9eaf | 42 | #ifndef CONFIG_ONENAND |
f68d2a22 | 43 | pxa2xx_dram_init(); |
411b9eaf | 44 | #endif |
6ef6eb91 | 45 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
6ef6eb91 MV |
46 | return 0; |
47 | } | |
48 | ||
49 | void dram_init_banksize(void) | |
f905432c MV |
50 | { |
51 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
18a00dfd | 52 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
18a00dfd | 53 | |
f97e9c65 | 54 | #ifdef CONFIG_RAM_256M |
f905432c MV |
55 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
56 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
57 | #endif | |
18a00dfd MV |
58 | } |
59 | ||
5d877f42 MV |
60 | #ifdef CONFIG_CMD_MMC |
61 | int board_mmc_init(bd_t *bis) | |
62 | { | |
63 | pxa_mmc_register(0); | |
64 | return 0; | |
65 | } | |
66 | #endif | |
67 | ||
f905432c | 68 | #ifdef CONFIG_CMD_USB |
18a00dfd MV |
69 | int usb_board_init(void) |
70 | { | |
3ba8bf7c MV |
71 | writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
72 | ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), | |
73 | UHCHR); | |
18a00dfd | 74 | |
3ba8bf7c | 75 | writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
18a00dfd | 76 | |
3ba8bf7c MV |
77 | while (readl(UHCHR) & UHCHR_FSBIR) |
78 | ; | |
18a00dfd | 79 | |
3ba8bf7c MV |
80 | writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); |
81 | writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); | |
18a00dfd MV |
82 | |
83 | /* Clear any OTG Pin Hold */ | |
3ba8bf7c MV |
84 | if (readl(PSSR) & PSSR_OTGPH) |
85 | writel(readl(PSSR) | PSSR_OTGPH, PSSR); | |
18a00dfd | 86 | |
3ba8bf7c MV |
87 | writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); |
88 | writel(readl(UHCRHDA) | 0x100, UHCRHDA); | |
18a00dfd MV |
89 | |
90 | /* Set port power control mask bits, only 3 ports. */ | |
3ba8bf7c | 91 | writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); |
18a00dfd MV |
92 | |
93 | /* enable port 2 */ | |
3ba8bf7c MV |
94 | writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | |
95 | UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); | |
18a00dfd MV |
96 | |
97 | return 0; | |
98 | } | |
99 | ||
100 | void usb_board_init_fail(void) | |
101 | { | |
102 | return; | |
103 | } | |
104 | ||
105 | void usb_board_stop(void) | |
106 | { | |
3ba8bf7c | 107 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
18a00dfd | 108 | udelay(11); |
3ba8bf7c | 109 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
18a00dfd | 110 | |
3ba8bf7c | 111 | writel(readl(UHCCOMS) | 1, UHCCOMS); |
18a00dfd MV |
112 | udelay(10); |
113 | ||
3ba8bf7c | 114 | writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
18a00dfd MV |
115 | |
116 | return; | |
117 | } | |
f905432c | 118 | #endif |
18a00dfd MV |
119 | |
120 | #ifdef CONFIG_DRIVER_DM9000 | |
121 | int board_eth_init(bd_t *bis) | |
122 | { | |
123 | return dm9000_initialize(bis); | |
124 | } | |
125 | #endif |