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e54dc965 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
e54dc965 WD |
6 | */ |
7 | #ifndef _ERRORS_H_ | |
8 | #define _ERRORS_H_ | |
9 | ||
10 | #define ERR_FF -1 /* led test value(2) */ | |
11 | #define ERR_00 0x0000 /* led test value(2) */ | |
12 | #define ERR_LED 0x01 /* led test failed (1)(3)(4) */ | |
13 | #define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */ | |
14 | #define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */ | |
15 | #define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */ | |
16 | #define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */ | |
17 | #define ERR_ADDG 0x08 /* start Address ghosting test (13) */ | |
18 | #define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */ | |
19 | #define ERR_POST1 0x0a /* post1 tests complete */ | |
20 | #define ERR_TMP1 0x0b /* */ | |
21 | #define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */ | |
22 | #define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */ | |
23 | #define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */ | |
24 | #define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */ | |
25 | #define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */ | |
26 | #define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */ | |
27 | #define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */ | |
28 | #define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */ | |
29 | #define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */ | |
30 | #define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */ | |
31 | #define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */ | |
32 | #define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */ | |
33 | #define ERR_RTCG 0x18 /* start RTC test */ | |
34 | #define ERR_RTCBAT 0x19 /* RTC battery failure */ | |
35 | #define ERR_RTCTIM 0x1A /* RTC invalid time/date values */ | |
36 | #define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */ | |
37 | #define ERR_FPGAG 0x20 /* fault during FPGA programming */ | |
38 | #define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */ | |
39 | #define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */ | |
40 | #define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */ | |
41 | #define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */ | |
42 | #define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */ | |
43 | #define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */ | |
44 | #define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */ | |
45 | #define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */ | |
46 | #define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */ | |
47 | #define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */ | |
48 | #define ERR_TempG 0x2b /* start temp sensor tests */ | |
49 | #define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */ | |
50 | #define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */ | |
51 | #define ERR_Ttest0 0x2E /* temp sensor 0 failed test */ | |
52 | #define ERR_Ttest1 0x2F /* temp sensor 1 failed test */ | |
53 | #define ERR_lm75r 0x30 /* temp sensor read failure */ | |
54 | #define ERR_lm75w 0x31 /* temp sensor write failure */ | |
55 | ||
56 | ||
57 | #define ERR_POSTOK 0x55 /* PANIC: psych... OK */ | |
58 | ||
59 | #if !defined(__ASSEMBLY__) | |
60 | extern void log_stat(int errcode); | |
61 | extern void log_warn(int errcode); | |
62 | extern void log_err(int errcode); | |
63 | #endif | |
64 | ||
65 | /* | |
66 | Debugging suggestions: | |
67 | (1) periferal data bus shorted or crossed | |
68 | (2) general processor halt, check reset, watch dog, power supply ripple, processor clock. | |
69 | (3) check p_we, p_r/w, p_oe, p_rdy lines. | |
70 | (4) check LED buffers | |
71 | (5) check SDRAM data bus bits 16-31, check LSW SDRAM chip. | |
72 | (6) check SDRAM data bus bits 0-15, check MSW SDRAM chip. | |
73 | (7) check SDRAM control lines and clocks | |
74 | (8) check decoupling caps, replace LSW SDRAM | |
75 | (9) check decoupling caps, replace MSW SDRAM | |
76 | (10) | |
77 | (11) | |
78 | (12) | |
79 | (13) SDRAM address shorted or unconnected, check sdram caps | |
80 | */ | |
81 | #endif /* _ERRORS_H_ */ |