[people/ms/u-boot.git] / board / w7o / init.S

/*
 * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
 */
#include <config.h>
#include <asm/ppc4xx.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

/******************************************************************************
 * Function:	ext_bus_cntlr_init
 *
 * Description:	Configures EBC Controller and a few basic chip selects.
 *
 *		CS0 is setup to get the Boot Flash out of the addresss range
 *		so that we may setup a stack.  CS7 is setup so that we can
 *		access and reset the hardware watchdog.
 *
 *		IMPORTANT: For pass1 this code must run from
 *		cache since you can not reliably change a peripheral banks
 *		timing register (pbxap) while running code from that bank.
 *		For ex., since we are running from ROM on bank 0, we can NOT
 *		execute the code that modifies bank 0 timings from ROM, so
 *		we run it from cache.
 *
 * Notes:	Does NOT use the stack.
 *****************************************************************************/
	.section ".text"
	.align	2
	.globl	ext_bus_cntlr_init
	.type	ext_bus_cntlr_init, @function
ext_bus_cntlr_init:
	mflr	r0
	/********************************************************************
	 * Prefetch entire ext_bus_cntrl_init function into the icache.
	 * This is necessary because we are going to change the same CS we
	 * are executing from.  Otherwise a CPU lockup may occur.
	 *******************************************************************/
	bl	..getAddr
..getAddr:
	mflr	r3			/* get address of ..getAddr */

	/* Calculate number of cache lines for this function */
	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
	mtctr	r4
..ebcloop:
	icbt	r0, r3			/* prefetch cache line for addr in r3*/
	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
	bdnz	..ebcloop		/* continue for $CTR cache lines */

	/********************************************************************
	 * Delay to ensure all accesses to ROM are complete before changing
	 * bank 0 timings. 200usec should be enough.
	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
	 *******************************************************************/
	addis	r3, 0, 0x0
	ori	r3, r3, 0xA000		/* wait 200us from reset */
	mtctr	r3
..spinlp:
	bdnz	..spinlp		/* spin loop */

	/********************************************************************
	 * Setup External Bus Controller (EBC).
	 *******************************************************************/
	addi	r3, 0, EBC0_CFG
	mtdcr	EBC0_CFGADDR, r3
	addis	r4, 0, 0xb040		/* Device base timeout = 1024 cycles */
	ori	r4, r4, 0x0		/* Drive CS with external master */
	mtdcr	EBC0_CFGDATA, r4

	/********************************************************************
	 * Change PCIINT signal to PerWE
	 *******************************************************************/
	mfdcr	r4, CPC0_CR1
	ori	r4, r4, 0x4000
	mtdcr	CPC0_CR1, r4

	/********************************************************************
	 * Memory Bank 0 (Flash Bank 0) initialization
	 *******************************************************************/
	addi	r3, 0, PB1AP
	mtdcr	EBC0_CFGADDR, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
	mtdcr	EBC0_CFGDATA, r4

	addi	r3, 0, PB0CR
	mtdcr	EBC0_CFGADDR, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
	mtdcr	EBC0_CFGDATA, r4

	/********************************************************************
	 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
	 *******************************************************************/
	addi	r3, 0, PB7AP
	mtdcr	EBC0_CFGADDR, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
	mtdcr	EBC0_CFGDATA, r4

	addi	r3, 0, PB7CR
	mtdcr	EBC0_CFGADDR, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
	mtdcr	EBC0_CFGDATA, r4

	/* We are all done */
	mtlr	r0			/* Restore link register */
	blr				/* Return to calling function */
.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
/* end ext_bus_cntlr_init() */

/******************************************************************************
 * Function:	sdram_init
 *
 * Description:	Configures SDRAM memory banks.
 *
 *		Serial Presence Detect, "SPD," reads the SDRAM EEPROM
 *		via the IIC bus and then configures the SDRAM memory
 *		banks appropriately. If Auto Memory Configuration is
 *		is not used, it is assumed that a 4MB 11x8x2, non-ECC,
 *		SDRAM is soldered down.
 *
 * Notes:	Expects that the stack is already setup.
 *****************************************************************************/
	.section ".text"
	.align	2
	.globl	sdram_init
	.type	sdram_init, @function
sdram_init:
	/* save the return info on stack */
	mflr	r0			/* Get link register */
	stwu	r1, -8(r1)		/* Save back chain and move SP */
	stw	r0, +12(r1)		/* Save link register */

	/*
	 * First call spd_sdram to try to init SDRAM according to the
	 * contents of the SPD EEPROM.  If the SPD EEPROM is blank or
	 * erronious, spd_sdram returns 0 in R3.
	 */
	li	r3,0
	bl	spd_sdram
	addic.	r3, r3, 0		/* Check for error, save dram size */
	bne	..sdri_done		/* If it worked, we're done... */

	/********************************************************************
	 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
	 * is the SMALLEST SDRAM size the 405 supports.  We can do this
	 * because W7O boards have soldered on RAM, and there will always
	 * be some amount present.  If we were using DIMMs, we should hang
	 * the board instead, since it doesn't have any RAM to continue
	 * running with.
	 *******************************************************************/

	/*
	 * Disable memory controller to allow
	 * values to be changed.
	 */
	addi    r3, 0, SDRAM0_CFG
	mtdcr   SDRAM0_CFGADDR, r3
	addis   r4, 0, 0x0
	ori     r4, r4, 0x0
	mtdcr   SDRAM0_CFGDATA, r4

	/*
	 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
	 * All other banks are disabled.
	 */
	addi	r3, 0, SDRAM0_B0CR
	mtdcr	SDRAM0_CFGADDR, r3
	addis	r4, 0, 0x0000		/* BA=0x0, SZ=4MB */
	ori	r4, r4, 0x8001		/* Mode is 5, 11x8x2or4, BE=Enabled */
	mtdcr	SDRAM0_CFGDATA, r4

	/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
	addi	r4, 0, 0		/* Zero the data reg */

	addi	r3, r3, 4		/* Point to MB1CF reg */
	mtdcr	SDRAM0_CFGADDR, r3		/* Set the address */
	mtdcr	SDRAM0_CFGDATA, r4		/* Zero the reg */

	addi	r3, r3, 4		/* Point to MB2CF reg */
	mtdcr	SDRAM0_CFGADDR, r3		/* Set the address */
	mtdcr	SDRAM0_CFGDATA, r4		/* Zero the reg */

	addi	r3, r3, 4		/* Point to MB3CF reg */
	mtdcr	SDRAM0_CFGADDR, r3		/* Set the address */
	mtdcr	SDRAM0_CFGDATA, r4		/* Zero the reg */

	/********************************************************************
	 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
	 * To set the appropriate timings, we assume sdram is
	 * 100MHz (pc100 compliant).
	 *******************************************************************/

	/*
	 * Set up SDTR1
	 */
	addi    r3, 0, SDRAM0_TR
	mtdcr   SDRAM0_CFGADDR, r3
	addis   r4, 0, 0x0086		/* SDTR1 value for 100Mhz */
	ori     r4, r4, 0x400D
	mtdcr   SDRAM0_CFGDATA, r4

	/*
	 * Set RTR
	 */
	addi    r3, 0, SDRAM0_RTR
	mtdcr   SDRAM0_CFGADDR, r3
	addis   r4, 0, 0x05F0		/* RTR refresh val = 15.625ms@100Mhz */
	mtdcr   SDRAM0_CFGDATA, r4

	/********************************************************************
	 * Delay to ensure 200usec have elapsed since reset. Assume worst
	 * case that the core is running 200Mhz:
	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	 *******************************************************************/
	addis   r3, 0, 0x0000
	ori     r3, r3, 0xA000		/* Wait 200us from reset */
	mtctr   r3
..spinlp2:
	bdnz    ..spinlp2		/* spin loop */

	/********************************************************************
	 * Set memory controller options reg, MCOPT1.
	 *******************************************************************/
	addi    r3, 0, SDRAM0_CFG
	mtdcr   SDRAM0_CFGADDR, r3
	addis   r4, 0, 0x80E0		/* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
	ori     r4, r4, 0x0000		/* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
	mtdcr   SDRAM0_CFGDATA, r4		/* EMDULR=1 */

..sdri_done:
	/* restore and return */
	lwz	r0, +12(r1)		/* Get saved link register */
	addi	r1, r1, +8		/* Remove frame from stack */
	mtlr	r0			/* Restore link register */
	blr				/* Return to calling function */
.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
/* end sdram_init() */
Commit	Line	Data
46263f2d	1	/*
1b387ef5	2	* SPDX-License-Identifier: GPL-2.0 IBM-pibs
46263f2d	3	*/
c609719b	4	#include <config.h>
b36df561	5	#include <asm/ppc4xx.h>
c609719b WD	6
	7	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	8
	9	#include <ppc_asm.tmpl>
	10	#include <ppc_defs.h>
	11
	12	#include <asm/cache.h>
	13	#include <asm/mmu.h>
	14
	15	/******************************************************************************
	16	* Function: ext_bus_cntlr_init
	17	*
	18	* Description: Configures EBC Controller and a few basic chip selects.
	19	*
	20	* CS0 is setup to get the Boot Flash out of the addresss range
	21	* so that we may setup a stack. CS7 is setup so that we can
	22	* access and reset the hardware watchdog.
	23	*
	24	* IMPORTANT: For pass1 this code must run from
	25	* cache since you can not reliably change a peripheral banks
	26	* timing register (pbxap) while running code from that bank.
	27	* For ex., since we are running from ROM on bank 0, we can NOT
	28	* execute the code that modifies bank 0 timings from ROM, so
	29	* we run it from cache.
	30	*
	31	* Notes: Does NOT use the stack.
	32	*****************************************************************************/
	33	.section ".text"
	34	.align 2
	35	.globl ext_bus_cntlr_init
	36	.type ext_bus_cntlr_init, @function
	37	ext_bus_cntlr_init:
	38	mflr r0
	39	/********************************************************************
	40	* Prefetch entire ext_bus_cntrl_init function into the icache.
	41	* This is necessary because we are going to change the same CS we
	42	* are executing from. Otherwise a CPU lockup may occur.
	43	*******************************************************************/
	44	bl ..getAddr
	45	..getAddr:
	46	mflr r3 /* get address of ..getAddr */
	47
	48	/* Calculate number of cache lines for this function */
6d0f6bcf	49	addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
c609719b WD	50	mtctr r4
	51	..ebcloop:
	52	icbt r0, r3 /* prefetch cache line for addr in r3*/
6d0f6bcf	53	addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
c609719b WD	54	bdnz ..ebcloop /* continue for $CTR cache lines */
	55
	56	/********************************************************************
	57	* Delay to ensure all accesses to ROM are complete before changing
	58	* bank 0 timings. 200usec should be enough.
	59	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
	60	*******************************************************************/
	61	addis r3, 0, 0x0
	62	ori r3, r3, 0xA000 /* wait 200us from reset */
	63	mtctr r3
	64	..spinlp:
	65	bdnz ..spinlp /* spin loop */
	66
	67	/********************************************************************
	68	* Setup External Bus Controller (EBC).
	69	*******************************************************************/
d1c3b275 SR	70	addi r3, 0, EBC0_CFG
d1c3b275 SR	71	mtdcr EBC0_CFGADDR, r3
c609719b WD	72	addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
c609719b WD	73	ori r4, r4, 0x0 /* Drive CS with external master */
d1c3b275	74	mtdcr EBC0_CFGDATA, r4
c609719b WD	75
	76	/********************************************************************
	77	* Change PCIINT signal to PerWE
	78	*******************************************************************/
d1c3b275	79	mfdcr r4, CPC0_CR1
c609719b	80	ori r4, r4, 0x4000
d1c3b275	81	mtdcr CPC0_CR1, r4
c609719b WD	82
	83	/********************************************************************
	84	* Memory Bank 0 (Flash Bank 0) initialization
	85	*******************************************************************/
d1c3b275 SR	86	addi r3, 0, PB1AP
d1c3b275 SR	87	mtdcr EBC0_CFGADDR, r3
6d0f6bcf JCPV	88	addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
6d0f6bcf JCPV	89	ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
d1c3b275	90	mtdcr EBC0_CFGDATA, r4
c609719b	91
d1c3b275 SR	92	addi r3, 0, PB0CR
d1c3b275 SR	93	mtdcr EBC0_CFGADDR, r3
6d0f6bcf JCPV	94	addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
6d0f6bcf JCPV	95	ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
d1c3b275	96	mtdcr EBC0_CFGDATA, r4
c609719b WD	97
	98	/********************************************************************
	99	* Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
	100	*******************************************************************/
d1c3b275 SR	101	addi r3, 0, PB7AP
d1c3b275 SR	102	mtdcr EBC0_CFGADDR, r3
6d0f6bcf JCPV	103	addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
6d0f6bcf JCPV	104	ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
d1c3b275	105	mtdcr EBC0_CFGDATA, r4
c609719b	106
d1c3b275 SR	107	addi r3, 0, PB7CR
d1c3b275 SR	108	mtdcr EBC0_CFGADDR, r3
6d0f6bcf JCPV	109	addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
6d0f6bcf JCPV	110	ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
d1c3b275	111	mtdcr EBC0_CFGDATA, r4
c609719b WD	112
	113	/* We are all done */
	114	mtlr r0 /* Restore link register */
	115	blr /* Return to calling function */
	116	.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
	117	/* end ext_bus_cntlr_init() */
	118
	119	/******************************************************************************
	120	* Function: sdram_init
	121	*
	122	* Description: Configures SDRAM memory banks.
	123	*
	124	* Serial Presence Detect, "SPD," reads the SDRAM EEPROM
	125	* via the IIC bus and then configures the SDRAM memory
	126	* banks appropriately. If Auto Memory Configuration is
	127	* is not used, it is assumed that a 4MB 11x8x2, non-ECC,
	128	* SDRAM is soldered down.
	129	*
	130	* Notes: Expects that the stack is already setup.
	131	*****************************************************************************/
	132	.section ".text"
	133	.align 2
	134	.globl sdram_init
	135	.type sdram_init, @function
	136	sdram_init:
	137	/* save the return info on stack */
	138	mflr r0 /* Get link register */
	139	stwu r1, -8(r1) /* Save back chain and move SP */
	140	stw r0, +12(r1) /* Save link register */
	141
	142	/*
	143	* First call spd_sdram to try to init SDRAM according to the
	144	* contents of the SPD EEPROM. If the SPD EEPROM is blank or
	145	* erronious, spd_sdram returns 0 in R3.
	146	*/
db2f721f	147	li r3,0
c609719b WD	148	bl spd_sdram
	149	addic. r3, r3, 0 /* Check for error, save dram size */
	150	bne ..sdri_done /* If it worked, we're done... */
	151
	152	/********************************************************************
	153	* If SPD detection fails, we'll default to 4MB, 11x8x2, as this
	154	* is the SMALLEST SDRAM size the 405 supports. We can do this
	155	* because W7O boards have soldered on RAM, and there will always
	156	* be some amount present. If we were using DIMMs, we should hang
	157	* the board instead, since it doesn't have any RAM to continue
	158	* running with.
	159	*******************************************************************/
	160
	161	/*
	162	* Disable memory controller to allow
	163	* values to be changed.
	164	*/
95b602ba	165	addi r3, 0, SDRAM0_CFG
d1c3b275	166	mtdcr SDRAM0_CFGADDR, r3
c609719b WD	167	addis r4, 0, 0x0
c609719b WD	168	ori r4, r4, 0x0
d1c3b275	169	mtdcr SDRAM0_CFGDATA, r4
c609719b WD	170
	171	/*
	172	* Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
	173	* All other banks are disabled.
	174	*/
95b602ba	175	addi r3, 0, SDRAM0_B0CR
d1c3b275	176	mtdcr SDRAM0_CFGADDR, r3
c609719b WD	177	addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
c609719b WD	178	ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
d1c3b275	179	mtdcr SDRAM0_CFGDATA, r4
c609719b WD	180
	181	/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
	182	addi r4, 0, 0 /* Zero the data reg */
	183
	184	addi r3, r3, 4 /* Point to MB1CF reg */
d1c3b275 SR	185	mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
d1c3b275 SR	186	mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
c609719b WD	187
c609719b WD	188	addi r3, r3, 4 /* Point to MB2CF reg */
d1c3b275 SR	189	mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
d1c3b275 SR	190	mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
c609719b WD	191
c609719b WD	192	addi r3, r3, 4 /* Point to MB3CF reg */
d1c3b275 SR	193	mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
d1c3b275 SR	194	mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
c609719b WD	195
	196	/********************************************************************
	197	* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
	198	* To set the appropriate timings, we assume sdram is
	199	* 100MHz (pc100 compliant).
	200	*******************************************************************/
	201
	202	/*
	203	* Set up SDTR1
	204	*/
95b602ba	205	addi r3, 0, SDRAM0_TR
d1c3b275	206	mtdcr SDRAM0_CFGADDR, r3
c609719b WD	207	addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
c609719b WD	208	ori r4, r4, 0x400D
d1c3b275	209	mtdcr SDRAM0_CFGDATA, r4
c609719b WD	210
	211	/*
	212	* Set RTR
	213	*/
95b602ba	214	addi r3, 0, SDRAM0_RTR
d1c3b275	215	mtdcr SDRAM0_CFGADDR, r3
c609719b	216	addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
d1c3b275	217	mtdcr SDRAM0_CFGDATA, r4
c609719b WD	218
	219	/********************************************************************
	220	* Delay to ensure 200usec have elapsed since reset. Assume worst
	221	* case that the core is running 200Mhz:
	222	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	223	*******************************************************************/
	224	addis r3, 0, 0x0000
	225	ori r3, r3, 0xA000 /* Wait 200us from reset */
	226	mtctr r3
	227	..spinlp2:
	228	bdnz ..spinlp2 /* spin loop */
	229
	230	/********************************************************************
	231	* Set memory controller options reg, MCOPT1.
	232	*******************************************************************/
95b602ba	233	addi r3, 0, SDRAM0_CFG
d1c3b275	234	mtdcr SDRAM0_CFGADDR, r3
c609719b WD	235	addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
c609719b WD	236	ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
d1c3b275	237	mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
c609719b WD	238
	239	..sdri_done:
	240	/* restore and return */
	241	lwz r0, +12(r1) /* Get saved link register */
	242	addi r1, r1, +8 /* Remove frame from stack */
	243	mtlr r0 /* Restore link register */
	244	blr /* Return to calling function */
	245	.Lfe1: .size sdram_init,.Lfe1-sdram_init
	246	/* end sdram_init() */