[people/ms/u-boot.git] / board / w7o / init.S

/******************************************************************************
 *
 *	 This source code has been made available to you by IBM on an AS-IS
 *	 basis.	 Anyone receiving this source is licensed under IBM
 *	 copyrights to use it in any way he or she deems fit, including
 *	 copying it, modifying it, compiling it, and redistributing it either
 *	 with or without modifications.	 No license under IBM patents or
 *	 patent applications is to be implied by the copyright license.
 *
 *	 Any user of this software should understand that IBM cannot provide
 *	 technical support for this software and will not be responsible for
 *	 any consequences resulting from the use of this software.
 *
 *	 Any person who transfers this source code or any derivative work
 *	 must include the IBM copyright notice, this paragraph, and the
 *	 preceding two paragraphs in the transferred software.
 *
 *	 COPYRIGHT   I B M   CORPORATION 1995
 *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *
 *****************************************************************************/
#include <config.h>
#include <ppc4xx.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

/******************************************************************************
 * Function:	ext_bus_cntlr_init
 *
 * Description:	Configures EBC Controller and a few basic chip selects.
 *
 *		CS0 is setup to get the Boot Flash out of the addresss range
 *		so that we may setup a stack.  CS7 is setup so that we can
 *		access and reset the hardware watchdog.
 *
 *		IMPORTANT: For pass1 this code must run from
 *		cache since you can not reliably change a peripheral banks
 *		timing register (pbxap) while running code from that bank.
 *		For ex., since we are running from ROM on bank 0, we can NOT
 *		execute the code that modifies bank 0 timings from ROM, so
 *		we run it from cache.
 *
 * Notes:	Does NOT use the stack.
 *****************************************************************************/
	.section ".text"
	.align	2
	.globl	ext_bus_cntlr_init
	.type	ext_bus_cntlr_init, @function
ext_bus_cntlr_init:
	mflr	r0
	/********************************************************************
	 * Prefetch entire ext_bus_cntrl_init function into the icache.
	 * This is necessary because we are going to change the same CS we
	 * are executing from.  Otherwise a CPU lockup may occur.
	 *******************************************************************/
	bl	..getAddr
..getAddr:
	mflr	r3			/* get address of ..getAddr */

	/* Calculate number of cache lines for this function */
	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
	mtctr	r4
..ebcloop:
	icbt	r0, r3			/* prefetch cache line for addr in r3*/
	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
	bdnz	..ebcloop		/* continue for $CTR cache lines */

	/********************************************************************
	 * Delay to ensure all accesses to ROM are complete before changing
	 * bank 0 timings. 200usec should be enough.
	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
	 *******************************************************************/
	addis	r3, 0, 0x0
	ori	r3, r3, 0xA000		/* wait 200us from reset */
	mtctr	r3
..spinlp:
	bdnz	..spinlp		/* spin loop */

	/********************************************************************
	 * Setup External Bus Controller (EBC).
	 *******************************************************************/
	addi	r3, 0, epcr
	mtdcr	ebccfga, r3
	addis	r4, 0, 0xb040		/* Device base timeout = 1024 cycles */
	ori	r4, r4, 0x0		/* Drive CS with external master */
	mtdcr	ebccfgd, r4

	/********************************************************************
	 * Change PCIINT signal to PerWE
	 *******************************************************************/
	mfdcr	r4, cntrl1
	ori	r4, r4, 0x4000
	mtdcr	cntrl1, r4

	/********************************************************************
	 * Memory Bank 0 (Flash Bank 0) initialization
	 *******************************************************************/
	addi	r3, 0, pb0ap
	mtdcr	ebccfga, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
	mtdcr	ebccfgd, r4

	addi	r3, 0, pb0cr
	mtdcr	ebccfga, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
	mtdcr	ebccfgd, r4

	/********************************************************************
	 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
	 *******************************************************************/
	addi	r3, 0, pb7ap
	mtdcr	ebccfga, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
	mtdcr	ebccfgd, r4

	addi	r3, 0, pb7cr
	mtdcr	ebccfga, r3
	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
	mtdcr	ebccfgd, r4

	/* We are all done */
	mtlr	r0			/* Restore link register */
	blr				/* Return to calling function */
.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
/* end ext_bus_cntlr_init() */

/******************************************************************************
 * Function:	sdram_init
 *
 * Description:	Configures SDRAM memory banks.
 *
 *		Serial Presence Detect, "SPD," reads the SDRAM EEPROM
 *		via the IIC bus and then configures the SDRAM memory
 *		banks appropriately. If Auto Memory Configuration is
 *		is not used, it is assumed that a 4MB 11x8x2, non-ECC,
 *		SDRAM is soldered down.
 *
 * Notes:	Expects that the stack is already setup.
 *****************************************************************************/
	.section ".text"
	.align	2
	.globl	sdram_init
	.type	sdram_init, @function
sdram_init:
	/* save the return info on stack */
	mflr	r0			/* Get link register */
	stwu	r1, -8(r1)		/* Save back chain and move SP */
	stw	r0, +12(r1)		/* Save link register */

	/*
	 * First call spd_sdram to try to init SDRAM according to the
	 * contents of the SPD EEPROM.  If the SPD EEPROM is blank or
	 * erronious, spd_sdram returns 0 in R3.
	 */
	li	r3,0
	bl	spd_sdram
	addic.	r3, r3, 0		/* Check for error, save dram size */
	bne	..sdri_done		/* If it worked, we're done... */

	/********************************************************************
	 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
	 * is the SMALLEST SDRAM size the 405 supports.  We can do this
	 * because W7O boards have soldered on RAM, and there will always
	 * be some amount present.  If we were using DIMMs, we should hang
	 * the board instead, since it doesn't have any RAM to continue
	 * running with.
	 *******************************************************************/

	/*
	 * Disable memory controller to allow
	 * values to be changed.
	 */
	addi    r3, 0, mem_mcopt1
	mtdcr   memcfga, r3
	addis   r4, 0, 0x0
	ori     r4, r4, 0x0
	mtdcr   memcfgd, r4

	/*
	 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
	 * All other banks are disabled.
	 */
	addi	r3, 0, mem_mb0cf
	mtdcr	memcfga, r3
	addis	r4, 0, 0x0000		/* BA=0x0, SZ=4MB */
	ori	r4, r4, 0x8001		/* Mode is 5, 11x8x2or4, BE=Enabled */
	mtdcr	memcfgd, r4

	/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
	addi	r4, 0, 0		/* Zero the data reg */

	addi	r3, r3, 4		/* Point to MB1CF reg */
	mtdcr	memcfga, r3		/* Set the address */
	mtdcr	memcfgd, r4		/* Zero the reg */

	addi	r3, r3, 4		/* Point to MB2CF reg */
	mtdcr	memcfga, r3		/* Set the address */
	mtdcr	memcfgd, r4		/* Zero the reg */

	addi	r3, r3, 4		/* Point to MB3CF reg */
	mtdcr	memcfga, r3		/* Set the address */
	mtdcr	memcfgd, r4		/* Zero the reg */

	/********************************************************************
	 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
	 * To set the appropriate timings, we assume sdram is
	 * 100MHz (pc100 compliant).
	 *******************************************************************/

	/*
	 * Set up SDTR1
	 */
	addi    r3, 0, mem_sdtr1
	mtdcr   memcfga, r3
	addis   r4, 0, 0x0086		/* SDTR1 value for 100Mhz */
	ori     r4, r4, 0x400D
	mtdcr   memcfgd, r4

	/*
	 * Set RTR
	 */
	addi    r3, 0, mem_rtr
	mtdcr   memcfga, r3
	addis   r4, 0, 0x05F0		/* RTR refresh val = 15.625ms@100Mhz */
	mtdcr   memcfgd, r4

	/********************************************************************
	 * Delay to ensure 200usec have elapsed since reset. Assume worst
	 * case that the core is running 200Mhz:
	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	 *******************************************************************/
	addis   r3, 0, 0x0000
	ori     r3, r3, 0xA000		/* Wait 200us from reset */
	mtctr   r3
..spinlp2:
	bdnz    ..spinlp2		/* spin loop */

	/********************************************************************
	 * Set memory controller options reg, MCOPT1.
	 *******************************************************************/
	addi    r3, 0, mem_mcopt1
	mtdcr   memcfga, r3
	addis   r4, 0, 0x80E0		/* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
	ori     r4, r4, 0x0000		/* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
	mtdcr   memcfgd, r4		/* EMDULR=1 */

..sdri_done:
	/* restore and return */
	lwz	r0, +12(r1)		/* Get saved link register */
	addi	r1, r1, +8		/* Remove frame from stack */
	mtlr	r0			/* Restore link register */
	blr				/* Return to calling function */
.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
/* end sdram_init() */
Commit	Line	Data
c609719b WD	1	/******************************************************************************
	2	*
	3	* This source code has been made available to you by IBM on an AS-IS
	4	* basis. Anyone receiving this source is licensed under IBM
	5	* copyrights to use it in any way he or she deems fit, including
	6	* copying it, modifying it, compiling it, and redistributing it either
	7	* with or without modifications. No license under IBM patents or
	8	* patent applications is to be implied by the copyright license.
	9	*
	10	* Any user of this software should understand that IBM cannot provide
	11	* technical support for this software and will not be responsible for
	12	* any consequences resulting from the use of this software.
	13	*
	14	* Any person who transfers this source code or any derivative work
	15	* must include the IBM copyright notice, this paragraph, and the
	16	* preceding two paragraphs in the transferred software.
	17	*
	18	* COPYRIGHT I B M CORPORATION 1995
	19	* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
	20	*
	21	*****************************************************************************/
	22	#include <config.h>
	23	#include <ppc4xx.h>
	24
	25	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	26
	27	#include <ppc_asm.tmpl>
	28	#include <ppc_defs.h>
	29
	30	#include <asm/cache.h>
	31	#include <asm/mmu.h>
	32
	33	/******************************************************************************
	34	* Function: ext_bus_cntlr_init
	35	*
	36	* Description: Configures EBC Controller and a few basic chip selects.
	37	*
	38	* CS0 is setup to get the Boot Flash out of the addresss range
	39	* so that we may setup a stack. CS7 is setup so that we can
	40	* access and reset the hardware watchdog.
	41	*
	42	* IMPORTANT: For pass1 this code must run from
	43	* cache since you can not reliably change a peripheral banks
	44	* timing register (pbxap) while running code from that bank.
	45	* For ex., since we are running from ROM on bank 0, we can NOT
	46	* execute the code that modifies bank 0 timings from ROM, so
	47	* we run it from cache.
	48	*
	49	* Notes: Does NOT use the stack.
	50	*****************************************************************************/
	51	.section ".text"
	52	.align 2
	53	.globl ext_bus_cntlr_init
	54	.type ext_bus_cntlr_init, @function
	55	ext_bus_cntlr_init:
	56	mflr r0
	57	/********************************************************************
	58	* Prefetch entire ext_bus_cntrl_init function into the icache.
	59	* This is necessary because we are going to change the same CS we
	60	* are executing from. Otherwise a CPU lockup may occur.
	61	*******************************************************************/
	62	bl ..getAddr
	63	..getAddr:
	64	mflr r3 /* get address of ..getAddr */
65
66	/* Calculate number of cache lines for this function */
6d0f6bcf	67	addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
c609719b WD	68	mtctr r4
	69	..ebcloop:
	70	icbt r0, r3 /* prefetch cache line for addr in r3*/
6d0f6bcf	71	addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
c609719b WD	72	bdnz ..ebcloop /* continue for $CTR cache lines */
	73
	74	/********************************************************************
	75	* Delay to ensure all accesses to ROM are complete before changing
	76	* bank 0 timings. 200usec should be enough.
	77	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
	78	*******************************************************************/
	79	addis r3, 0, 0x0
	80	ori r3, r3, 0xA000 /* wait 200us from reset */
	81	mtctr r3
	82	..spinlp:
	83	bdnz ..spinlp /* spin loop */
	84
	85	/********************************************************************
	86	* Setup External Bus Controller (EBC).
	87	*******************************************************************/
	88	addi r3, 0, epcr
	89	mtdcr ebccfga, r3
	90	addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
	91	ori r4, r4, 0x0 /* Drive CS with external master */
	92	mtdcr ebccfgd, r4
	93
	94	/********************************************************************
	95	* Change PCIINT signal to PerWE
	96	*******************************************************************/
	97	mfdcr r4, cntrl1
	98	ori r4, r4, 0x4000
	99	mtdcr cntrl1, r4
	100
	101	/********************************************************************
	102	* Memory Bank 0 (Flash Bank 0) initialization
	103	*******************************************************************/
	104	addi r3, 0, pb0ap
	105	mtdcr ebccfga, r3
6d0f6bcf JCPV	106	addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
6d0f6bcf JCPV	107	ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
c609719b WD	108	mtdcr ebccfgd, r4
	109
	110	addi r3, 0, pb0cr
	111	mtdcr ebccfga, r3
6d0f6bcf JCPV	112	addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
6d0f6bcf JCPV	113	ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
c609719b WD	114	mtdcr ebccfgd, r4
	115
	116	/********************************************************************
	117	* Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
	118	*******************************************************************/
	119	addi r3, 0, pb7ap
	120	mtdcr ebccfga, r3
6d0f6bcf JCPV	121	addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
6d0f6bcf JCPV	122	ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
c609719b WD	123	mtdcr ebccfgd, r4
	124
	125	addi r3, 0, pb7cr
	126	mtdcr ebccfga, r3
6d0f6bcf JCPV	127	addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
6d0f6bcf JCPV	128	ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
c609719b WD	129	mtdcr ebccfgd, r4
	130
	131	/* We are all done */
	132	mtlr r0 /* Restore link register */
	133	blr /* Return to calling function */
	134	.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
	135	/* end ext_bus_cntlr_init() */
	136
	137	/******************************************************************************
	138	* Function: sdram_init
	139	*
	140	* Description: Configures SDRAM memory banks.
	141	*
	142	* Serial Presence Detect, "SPD," reads the SDRAM EEPROM
	143	* via the IIC bus and then configures the SDRAM memory
	144	* banks appropriately. If Auto Memory Configuration is
	145	* is not used, it is assumed that a 4MB 11x8x2, non-ECC,
	146	* SDRAM is soldered down.
	147	*
	148	* Notes: Expects that the stack is already setup.
	149	*****************************************************************************/
	150	.section ".text"
	151	.align 2
	152	.globl sdram_init
	153	.type sdram_init, @function
	154	sdram_init:
	155	/* save the return info on stack */
	156	mflr r0 /* Get link register */
	157	stwu r1, -8(r1) /* Save back chain and move SP */
	158	stw r0, +12(r1) /* Save link register */
	159
	160	/*
	161	* First call spd_sdram to try to init SDRAM according to the
	162	* contents of the SPD EEPROM. If the SPD EEPROM is blank or
	163	* erronious, spd_sdram returns 0 in R3.
	164	*/
db2f721f	165	li r3,0
c609719b WD	166	bl spd_sdram
	167	addic. r3, r3, 0 /* Check for error, save dram size */
	168	bne ..sdri_done /* If it worked, we're done... */
	169
	170	/********************************************************************
	171	* If SPD detection fails, we'll default to 4MB, 11x8x2, as this
	172	* is the SMALLEST SDRAM size the 405 supports. We can do this
	173	* because W7O boards have soldered on RAM, and there will always
	174	* be some amount present. If we were using DIMMs, we should hang
	175	* the board instead, since it doesn't have any RAM to continue
	176	* running with.
	177	*******************************************************************/
	178
	179	/*
	180	* Disable memory controller to allow
	181	* values to be changed.
	182	*/
	183	addi r3, 0, mem_mcopt1
	184	mtdcr memcfga, r3
	185	addis r4, 0, 0x0
	186	ori r4, r4, 0x0
	187	mtdcr memcfgd, r4
	188
	189	/*
	190	* Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
	191	* All other banks are disabled.
	192	*/
	193	addi r3, 0, mem_mb0cf
	194	mtdcr memcfga, r3
	195	addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
	196	ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
	197	mtdcr memcfgd, r4
	198
	199	/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
	200	addi r4, 0, 0 /* Zero the data reg */
	201
	202	addi r3, r3, 4 /* Point to MB1CF reg */
	203	mtdcr memcfga, r3 /* Set the address */
	204	mtdcr memcfgd, r4 /* Zero the reg */
	205
	206	addi r3, r3, 4 /* Point to MB2CF reg */
	207	mtdcr memcfga, r3 /* Set the address */
	208	mtdcr memcfgd, r4 /* Zero the reg */
	209
	210	addi r3, r3, 4 /* Point to MB3CF reg */
	211	mtdcr memcfga, r3 /* Set the address */
	212	mtdcr memcfgd, r4 /* Zero the reg */
	213
	214	/********************************************************************
	215	* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
	216	* To set the appropriate timings, we assume sdram is
	217	* 100MHz (pc100 compliant).
	218	*******************************************************************/
	219
	220	/*
	221	* Set up SDTR1
	222	*/
	223	addi r3, 0, mem_sdtr1
	224	mtdcr memcfga, r3
	225	addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
	226	ori r4, r4, 0x400D
	227	mtdcr memcfgd, r4
	228
	229	/*
230	* Set RTR
231	*/
232	addi r3, 0, mem_rtr
233	mtdcr memcfga, r3
234	addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
235	mtdcr memcfgd, r4
236
237	/********************************************************************
238	* Delay to ensure 200usec have elapsed since reset. Assume worst
239	* case that the core is running 200Mhz:
240	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
241	*******************************************************************/
242	addis r3, 0, 0x0000
243	ori r3, r3, 0xA000 /* Wait 200us from reset */
244	mtctr r3
245	..spinlp2:
246	bdnz ..spinlp2 /* spin loop */
247
248	/********************************************************************
249	* Set memory controller options reg, MCOPT1.
250	*******************************************************************/
251	addi r3, 0, mem_mcopt1
252	mtdcr memcfga, r3
253	addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
254	ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
255	mtdcr memcfgd, r4 /* EMDULR=1 */
256
257	..sdri_done:
258	/* restore and return */
259	lwz r0, +12(r1) /* Get saved link register */
260	addi r1, r1, +8 /* Remove frame from stack */
261	mtlr r0 /* Restore link register */
262	blr /* Return to calling function */
263	.Lfe1: .size sdram_init,.Lfe1-sdram_init
264	/* end sdram_init() */