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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
8bde7f77 | 9 | #include <command.h> |
c609719b WD |
10 | #include "w7o.h" |
11 | #include <asm/processor.h> | |
12 | ||
13 | #include "vpd.h" | |
14 | #include "errors.h" | |
15 | #include <watchdog.h> | |
16 | ||
c83bf6a2 | 17 | unsigned long get_dram_size (void); |
bbeff30c | 18 | void sdram_init(void); |
c609719b | 19 | |
c609719b WD |
20 | /* ------------------------------------------------------------------------- */ |
21 | ||
c837dcb1 | 22 | int board_early_init_f (void) |
c609719b WD |
23 | { |
24 | #if defined(CONFIG_W7OLMG) | |
c83bf6a2 WD |
25 | /* |
26 | * Setup GPIO pins - reset devices. | |
27 | */ | |
0c8721a4 WD |
28 | out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ |
29 | out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ | |
30 | out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ | |
c83bf6a2 WD |
31 | |
32 | /* | |
33 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
34 | * IRQ 16 405GP internally generated; active low; level sensitive | |
35 | * IRQ 17-24 RESERVED | |
36 | * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive | |
37 | * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive | |
38 | * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive | |
39 | * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive | |
40 | * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive | |
41 | * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive | |
42 | * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive | |
43 | */ | |
952e7760 SR |
44 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
45 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
c83bf6a2 | 46 | |
952e7760 SR |
47 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ |
48 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
49 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
50 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, | |
c83bf6a2 WD |
51 | INT0 highest priority */ |
52 | ||
952e7760 | 53 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
c609719b WD |
54 | |
55 | #elif defined(CONFIG_W7OLMC) | |
c83bf6a2 WD |
56 | /* |
57 | * Setup GPIO pins | |
58 | */ | |
0c8721a4 WD |
59 | out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ |
60 | out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ | |
61 | out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ | |
c83bf6a2 WD |
62 | |
63 | /* | |
64 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
65 | * IRQ 16 405GP internally generated; active low; level sensitive | |
66 | * IRQ 17-24 RESERVED | |
67 | * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive | |
68 | * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive | |
69 | * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive | |
70 | * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive | |
71 | * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive | |
72 | * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive | |
73 | * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive | |
74 | */ | |
952e7760 SR |
75 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
76 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
c83bf6a2 | 77 | |
952e7760 SR |
78 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ |
79 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
80 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
81 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, | |
c83bf6a2 WD |
82 | INT0 highest priority */ |
83 | ||
952e7760 | 84 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
c83bf6a2 WD |
85 | |
86 | #else /* Unknown */ | |
c609719b WD |
87 | # error "Unknown W7O board configuration" |
88 | #endif | |
89 | ||
c83bf6a2 WD |
90 | WATCHDOG_RESET (); /* Reset the watchdog */ |
91 | temp_uart_init (); /* init the uart for debug */ | |
92 | WATCHDOG_RESET (); /* Reset the watchdog */ | |
93 | test_led (); /* test the LEDs */ | |
94 | test_sdram (get_dram_size ()); /* test the dram */ | |
95 | log_stat (ERR_POST1); /* log status,post1 complete */ | |
96 | return 0; | |
c609719b WD |
97 | } |
98 | ||
99 | ||
100 | /* ------------------------------------------------------------------------- */ | |
101 | ||
102 | /* | |
103 | * Check Board Identity: | |
104 | */ | |
105 | int checkboard (void) | |
106 | { | |
c83bf6a2 WD |
107 | VPD vpd; |
108 | ||
109 | puts ("Board: "); | |
110 | ||
111 | /* VPD data present in I2C EEPROM */ | |
6d0f6bcf | 112 | if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) { |
c83bf6a2 WD |
113 | /* |
114 | * Known board type. | |
115 | */ | |
116 | if (vpd.productId[0] && | |
117 | ((strncmp (vpd.productId, "GMM", 3) == 0) || | |
118 | (strncmp (vpd.productId, "CMM", 3) == 0))) { | |
119 | ||
120 | /* Output board information on startup */ | |
121 | printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID); | |
122 | return (0); | |
123 | } | |
c609719b | 124 | } |
c609719b | 125 | |
c83bf6a2 WD |
126 | puts ("### Unknown HW ID - assuming NOTHING\n"); |
127 | return (0); | |
c609719b WD |
128 | } |
129 | ||
130 | /* ------------------------------------------------------------------------- */ | |
131 | ||
9973e3c6 | 132 | phys_size_t initdram (int board_type) |
c609719b | 133 | { |
bbeff30c SR |
134 | /* |
135 | * ToDo: Move the asm init routine sdram_init() to this C file, | |
136 | * or even better use some common ppc4xx code available | |
a47a12be | 137 | * in arch/powerpc/cpu/ppc4xx |
bbeff30c SR |
138 | */ |
139 | sdram_init(); | |
140 | ||
c83bf6a2 | 141 | return get_dram_size (); |
c609719b WD |
142 | } |
143 | ||
144 | unsigned long get_dram_size (void) | |
145 | { | |
c83bf6a2 WD |
146 | int tmp, i, regs[4]; |
147 | int size = 0; | |
c609719b | 148 | |
c83bf6a2 | 149 | /* Get bank Size registers */ |
95b602ba | 150 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ |
d1c3b275 | 151 | regs[0] = mfdcr (SDRAM0_CFGDATA); |
c609719b | 152 | |
95b602ba | 153 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ |
d1c3b275 | 154 | regs[1] = mfdcr (SDRAM0_CFGDATA); |
c609719b | 155 | |
95b602ba | 156 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ |
d1c3b275 | 157 | regs[2] = mfdcr (SDRAM0_CFGDATA); |
c609719b | 158 | |
95b602ba | 159 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ |
d1c3b275 | 160 | regs[3] = mfdcr (SDRAM0_CFGDATA); |
c609719b | 161 | |
c83bf6a2 WD |
162 | /* compute the size, add each bank if enabled */ |
163 | for (i = 0; i < 4; i++) { | |
164 | if (regs[i] & 0x0001) { /* if enabled, */ | |
165 | tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */ | |
166 | tmp = 0x400000 << tmp; /* Size bits X 4MB = size */ | |
167 | size += tmp; | |
168 | } | |
c609719b | 169 | } |
c609719b | 170 | |
c83bf6a2 | 171 | return size; |
c609719b WD |
172 | } |
173 | ||
174 | int misc_init_f (void) | |
175 | { | |
c83bf6a2 | 176 | return 0; |
c609719b WD |
177 | } |
178 | ||
c83bf6a2 | 179 | static void w7o_env_init (VPD * vpd) |
c609719b | 180 | { |
c83bf6a2 WD |
181 | /* |
182 | * Read VPD | |
183 | */ | |
6d0f6bcf | 184 | if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0) |
c83bf6a2 | 185 | return; |
c609719b | 186 | |
c83bf6a2 WD |
187 | /* |
188 | * Known board type. | |
189 | */ | |
190 | if (vpd->productId[0] && | |
191 | ((strncmp (vpd->productId, "GMM", 3) == 0) || | |
192 | (strncmp (vpd->productId, "CMM", 3) == 0))) { | |
193 | char buf[30]; | |
194 | char *eth; | |
77ddac94 WD |
195 | char *serial = getenv ("serial#"); |
196 | char *ethaddr = getenv ("ethaddr"); | |
c83bf6a2 WD |
197 | |
198 | /* Set 'serial#' envvar if serial# isn't set */ | |
199 | if (!serial) { | |
200 | sprintf (buf, "%s-%ld", vpd->productId, | |
201 | vpd->serialNum); | |
202 | setenv ("serial#", buf); | |
203 | } | |
204 | ||
205 | /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ | |
77ddac94 | 206 | eth = (char *)(vpd->ethAddrs[0]); |
c83bf6a2 | 207 | if (ethaddr |
5368c55d | 208 | && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) { |
c83bf6a2 WD |
209 | /* Now setup ethaddr */ |
210 | sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", | |
211 | eth[0], eth[1], eth[2], eth[3], eth[4], | |
212 | eth[5]); | |
213 | setenv ("ethaddr", buf); | |
214 | } | |
c609719b | 215 | } |
c83bf6a2 | 216 | } /* w7o_env_init() */ |
c609719b WD |
217 | |
218 | ||
219 | int misc_init_r (void) | |
220 | { | |
c83bf6a2 | 221 | VPD vpd; /* VPD information */ |
c609719b WD |
222 | |
223 | #if defined(CONFIG_W7OLMG) | |
c83bf6a2 | 224 | unsigned long greg; /* GPIO Register */ |
c609719b | 225 | |
0c8721a4 | 226 | greg = in32 (PPC405GP_GPIO0_OR); |
c609719b | 227 | |
c83bf6a2 WD |
228 | /* |
229 | * XXX - Unreset devices - this should be moved into VxWorks driver code | |
230 | */ | |
231 | greg |= 0x41800000L; /* SAM, PHY, Galileo */ | |
c609719b | 232 | |
0c8721a4 | 233 | out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */ |
c609719b WD |
234 | #endif /* CONFIG_W7OLMG */ |
235 | ||
c83bf6a2 WD |
236 | /* |
237 | * Initialize W7O environment variables | |
238 | */ | |
239 | w7o_env_init (&vpd); | |
c609719b | 240 | |
c83bf6a2 WD |
241 | /* |
242 | * Initialize the FPGA(s). | |
243 | */ | |
244 | if (init_fpga () == 0) | |
245 | test_fpga ((unsigned short *) CONFIG_FPGAS_BASE); | |
c609719b | 246 | |
c83bf6a2 WD |
247 | /* More POST testing. */ |
248 | post2 (); | |
c609719b | 249 | |
c83bf6a2 WD |
250 | /* Done with hardware initialization and POST. */ |
251 | log_stat (ERR_POSTOK); | |
c609719b | 252 | |
c83bf6a2 WD |
253 | /* Call silly, fail safe boot init routine */ |
254 | init_fsboot (); | |
c609719b WD |
255 | |
256 | return (0); | |
257 | } |