[people/ms/u-boot.git] / board / w7o / w7o.c

/*
 * (C) Copyright 2001
 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include "w7o.h"
#include <asm/processor.h>

#include "vpd.h"
#include "errors.h"
#include <watchdog.h>

unsigned long get_dram_size (void);
void sdram_init(void);

/* ------------------------------------------------------------------------- */

int board_early_init_f (void)
{
#if defined(CONFIG_W7OLMG)
	/*
	 * Setup GPIO pins - reset devices.
	 */
	out32 (PPC405GP_GPIO0_ODR, 0x10000000);	/* one open drain pin */
	out32 (PPC405GP_GPIO0_OR, 0x3E000000);	/* set output pins to default */
	out32 (PPC405GP_GPIO0_TCR, 0x7f800000);	/* setup for output */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
	 */
	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */

	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,
					   INT0 highest priority */

	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */

#elif defined(CONFIG_W7OLMC)
	/*
	 * Setup GPIO pins
	 */
	out32 (PPC405GP_GPIO0_ODR, 0x01800000);	/* XCV Done Open Drain */
	out32 (PPC405GP_GPIO0_OR, 0x03800000);	/* set out pins to default */
	out32 (PPC405GP_GPIO0_TCR, 0x66C00000);	/* setup for output */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
	 */
	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */

	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,
					   INT0 highest priority */

	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */

#else  /* Unknown */
#    error "Unknown W7O board configuration"
#endif

	WATCHDOG_RESET ();	/* Reset the watchdog */
	temp_uart_init ();	/* init the uart for debug */
	WATCHDOG_RESET ();	/* Reset the watchdog */
	test_led ();		/* test the LEDs */
	test_sdram (get_dram_size ());	/* test the dram */
	log_stat (ERR_POST1);	/* log status,post1 complete */
	return 0;
}


/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */
int checkboard (void)
{
	VPD vpd;

	puts ("Board: ");

	/* VPD data present in I2C EEPROM */
	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
		/*
		 * Known board type.
		 */
		if (vpd.productId[0] &&
		    ((strncmp (vpd.productId, "GMM", 3) == 0) ||
		     (strncmp (vpd.productId, "CMM", 3) == 0))) {

			/* Output board information on startup */
			printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
			return (0);
		}
	}

	puts ("### Unknown HW ID - assuming NOTHING\n");
	return (0);
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	/*
	 * ToDo: Move the asm init routine sdram_init() to this C file,
	 * or even better use some common ppc4xx code available
	 * in arch/powerpc/cpu/ppc4xx
	 */
	sdram_init();

	return get_dram_size ();
}

unsigned long get_dram_size (void)
{
	int tmp, i, regs[4];
	int size = 0;

	/* Get bank Size registers */
	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);	/* get bank 0 config reg */
	regs[0] = mfdcr (SDRAM0_CFGDATA);

	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);	/* get bank 1 config reg */
	regs[1] = mfdcr (SDRAM0_CFGDATA);

	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);	/* get bank 2 config reg */
	regs[2] = mfdcr (SDRAM0_CFGDATA);

	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);	/* get bank 3 config reg */
	regs[3] = mfdcr (SDRAM0_CFGDATA);

	/* compute the size, add each bank if enabled */
	for (i = 0; i < 4; i++) {
		if (regs[i] & 0x0001) {	/* if enabled, */
			tmp = ((regs[i] >> (31 - 14)) & 0x7);	/* get size bits */
			tmp = 0x400000 << tmp;	/* Size bits X 4MB = size */
			size += tmp;
		}
	}

	return size;
}

int misc_init_f (void)
{
	return 0;
}

static void w7o_env_init (VPD * vpd)
{
	/*
	 * Read VPD
	 */
	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
		return;

	/*
	 * Known board type.
	 */
	if (vpd->productId[0] &&
	    ((strncmp (vpd->productId, "GMM", 3) == 0) ||
	     (strncmp (vpd->productId, "CMM", 3) == 0))) {
		char buf[30];
		char *eth;
		char *serial = getenv ("serial#");
		char *ethaddr = getenv ("ethaddr");

		/* Set 'serial#' envvar if serial# isn't set */
		if (!serial) {
			sprintf (buf, "%s-%ld", vpd->productId,
				 vpd->serialNum);
			setenv ("serial#", buf);
		}

		/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
		eth = (char *)(vpd->ethAddrs[0]);
		if (ethaddr
		    && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
			/* Now setup ethaddr */
			sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
				 eth[0], eth[1], eth[2], eth[3], eth[4],
				 eth[5]);
			setenv ("ethaddr", buf);
		}
	}
}				/* w7o_env_init() */


int misc_init_r (void)
{
	VPD vpd;		/* VPD information */

#if defined(CONFIG_W7OLMG)
	unsigned long greg;	/* GPIO Register */

	greg = in32 (PPC405GP_GPIO0_OR);

	/*
	 * XXX - Unreset devices - this should be moved into VxWorks driver code
	 */
	greg |= 0x41800000L;	/* SAM, PHY, Galileo */

	out32 (PPC405GP_GPIO0_OR, greg);	/* set output pins to default */
#endif /* CONFIG_W7OLMG */

	/*
	 * Initialize W7O environment variables
	 */
	w7o_env_init (&vpd);

	/*
	 * Initialize the FPGA(s).
	 */
	if (init_fpga () == 0)
		test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);

	/* More POST testing. */
	post2 ();

	/* Done with hardware initialization and POST. */
	log_stat (ERR_POSTOK);

	/* Call silly, fail safe boot init routine */
	init_fsboot ();

	return (0);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
8bde7f77	25	#include <command.h>
c609719b WD	26	#include "w7o.h"
	27	#include <asm/processor.h>
	28
	29	#include "vpd.h"
	30	#include "errors.h"
	31	#include <watchdog.h>
	32
c83bf6a2	33	unsigned long get_dram_size (void);
bbeff30c	34	void sdram_init(void);
c609719b	35
c609719b WD	36	/* ------------------------------------------------------------------------- */
c609719b WD	37
c837dcb1	38	int board_early_init_f (void)
c609719b WD	39	{
c609719b WD	40	#if defined(CONFIG_W7OLMG)
c83bf6a2 WD	41	/*
	42	* Setup GPIO pins - reset devices.
	43	*/
0c8721a4 WD	44	out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
	45	out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
	46	out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
c83bf6a2 WD	47
	48	/*
	49	* IRQ 0-15 405GP internally generated; active high; level sensitive
	50	* IRQ 16 405GP internally generated; active low; level sensitive
	51	* IRQ 17-24 RESERVED
	52	* IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
	53	* IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
	54	* IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
	55	* IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
	56	* IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
	57	* IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
	58	* IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
	59	*/
952e7760 SR	60	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
952e7760 SR	61	mtdcr (UIC0ER, 0x00000000); /* disable all ints */
c83bf6a2	62
952e7760 SR	63	mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
	64	mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
	65	mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
	66	mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
c83bf6a2 WD	67	INT0 highest priority */
c83bf6a2 WD	68
952e7760	69	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
c609719b WD	70
c609719b WD	71	#elif defined(CONFIG_W7OLMC)
c83bf6a2 WD	72	/*
	73	* Setup GPIO pins
	74	*/
0c8721a4 WD	75	out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
	76	out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
	77	out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
c83bf6a2 WD	78
	79	/*
	80	* IRQ 0-15 405GP internally generated; active high; level sensitive
	81	* IRQ 16 405GP internally generated; active low; level sensitive
	82	* IRQ 17-24 RESERVED
	83	* IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
	84	* IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
	85	* IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
	86	* IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
	87	* IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
	88	* IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
	89	* IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
	90	*/
952e7760 SR	91	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
952e7760 SR	92	mtdcr (UIC0ER, 0x00000000); /* disable all ints */
c83bf6a2	93
952e7760 SR	94	mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
	95	mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
	96	mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
	97	mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
c83bf6a2 WD	98	INT0 highest priority */
c83bf6a2 WD	99
952e7760	100	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
c83bf6a2 WD	101
c83bf6a2 WD	102	#else /* Unknown */
c609719b WD	103	# error "Unknown W7O board configuration"
	104	#endif
	105
c83bf6a2 WD	106	WATCHDOG_RESET (); /* Reset the watchdog */
	107	temp_uart_init (); /* init the uart for debug */
	108	WATCHDOG_RESET (); /* Reset the watchdog */
	109	test_led (); /* test the LEDs */
	110	test_sdram (get_dram_size ()); /* test the dram */
	111	log_stat (ERR_POST1); /* log status,post1 complete */
	112	return 0;
c609719b WD	113	}
	114
	115
	116	/* ------------------------------------------------------------------------- */
	117
	118	/*
	119	* Check Board Identity:
	120	*/
	121	int checkboard (void)
	122	{
c83bf6a2 WD	123	VPD vpd;
	124
	125	puts ("Board: ");
	126
	127	/* VPD data present in I2C EEPROM */
6d0f6bcf	128	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
c83bf6a2 WD	129	/*
	130	* Known board type.
	131	*/
	132	if (vpd.productId[0] &&
	133	((strncmp (vpd.productId, "GMM", 3) == 0) \|\|
	134	(strncmp (vpd.productId, "CMM", 3) == 0))) {
	135
	136	/* Output board information on startup */
	137	printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
	138	return (0);
	139	}
c609719b	140	}
c609719b	141
c83bf6a2 WD	142	puts ("### Unknown HW ID - assuming NOTHING\n");
c83bf6a2 WD	143	return (0);
c609719b WD	144	}
	145
	146	/* ------------------------------------------------------------------------- */
	147
9973e3c6	148	phys_size_t initdram (int board_type)
c609719b	149	{
bbeff30c SR	150	/*
	151	* ToDo: Move the asm init routine sdram_init() to this C file,
	152	* or even better use some common ppc4xx code available
a47a12be	153	* in arch/powerpc/cpu/ppc4xx
bbeff30c SR	154	*/
	155	sdram_init();
	156
c83bf6a2	157	return get_dram_size ();
c609719b WD	158	}
	159
	160	unsigned long get_dram_size (void)
	161	{
c83bf6a2 WD	162	int tmp, i, regs[4];
c83bf6a2 WD	163	int size = 0;
c609719b	164
c83bf6a2	165	/* Get bank Size registers */
95b602ba	166	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
d1c3b275	167	regs[0] = mfdcr (SDRAM0_CFGDATA);
c609719b	168
95b602ba	169	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
d1c3b275	170	regs[1] = mfdcr (SDRAM0_CFGDATA);
c609719b	171
95b602ba	172	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
d1c3b275	173	regs[2] = mfdcr (SDRAM0_CFGDATA);
c609719b	174
95b602ba	175	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
d1c3b275	176	regs[3] = mfdcr (SDRAM0_CFGDATA);
c609719b	177
c83bf6a2 WD	178	/* compute the size, add each bank if enabled */
	179	for (i = 0; i < 4; i++) {
	180	if (regs[i] & 0x0001) { /* if enabled, */
	181	tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
	182	tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
	183	size += tmp;
	184	}
c609719b	185	}
c609719b	186
c83bf6a2	187	return size;
c609719b WD	188	}
	189
	190	int misc_init_f (void)
	191	{
c83bf6a2	192	return 0;
c609719b WD	193	}
c609719b WD	194
c83bf6a2	195	static void w7o_env_init (VPD * vpd)
c609719b	196	{
c83bf6a2 WD	197	/*
	198	* Read VPD
	199	*/
6d0f6bcf	200	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
c83bf6a2	201	return;
c609719b	202
c83bf6a2 WD	203	/*
	204	* Known board type.
	205	*/
	206	if (vpd->productId[0] &&
	207	((strncmp (vpd->productId, "GMM", 3) == 0) \|\|
	208	(strncmp (vpd->productId, "CMM", 3) == 0))) {
	209	char buf[30];
	210	char *eth;
77ddac94 WD	211	char *serial = getenv ("serial#");
77ddac94 WD	212	char *ethaddr = getenv ("ethaddr");
c83bf6a2 WD	213
	214	/* Set 'serial#' envvar if serial# isn't set */
	215	if (!serial) {
	216	sprintf (buf, "%s-%ld", vpd->productId,
	217	vpd->serialNum);
	218	setenv ("serial#", buf);
	219	}
	220
	221	/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
77ddac94	222	eth = (char *)(vpd->ethAddrs[0]);
c83bf6a2	223	if (ethaddr
5368c55d	224	&& (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
c83bf6a2 WD	225	/* Now setup ethaddr */
	226	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
	227	eth[0], eth[1], eth[2], eth[3], eth[4],
	228	eth[5]);
	229	setenv ("ethaddr", buf);
	230	}
c609719b	231	}
c83bf6a2	232	} /* w7o_env_init() */
c609719b WD	233
	234
	235	int misc_init_r (void)
	236	{
c83bf6a2	237	VPD vpd; /* VPD information */
c609719b WD	238
c609719b WD	239	#if defined(CONFIG_W7OLMG)
c83bf6a2	240	unsigned long greg; /* GPIO Register */
c609719b	241
0c8721a4	242	greg = in32 (PPC405GP_GPIO0_OR);
c609719b	243
c83bf6a2 WD	244	/*
	245	* XXX - Unreset devices - this should be moved into VxWorks driver code
	246	*/
	247	greg \|= 0x41800000L; /* SAM, PHY, Galileo */
c609719b	248
0c8721a4	249	out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
c609719b WD	250	#endif /* CONFIG_W7OLMG */
c609719b WD	251
c83bf6a2 WD	252	/*
	253	* Initialize W7O environment variables
	254	*/
	255	w7o_env_init (&vpd);
c609719b	256
c83bf6a2 WD	257	/*
	258	* Initialize the FPGA(s).
	259	*/
	260	if (init_fpga () == 0)
	261	test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
c609719b	262
c83bf6a2 WD	263	/* More POST testing. */
c83bf6a2 WD	264	post2 ();
c609719b	265
c83bf6a2 WD	266	/* Done with hardware initialization and POST. */
c83bf6a2 WD	267	log_stat (ERR_POSTOK);
c609719b	268
c83bf6a2 WD	269	/* Call silly, fail safe boot init routine */
c83bf6a2 WD	270	init_fsboot ();
c609719b WD	271
	272	return (0);
	273	}