[people/ms/u-boot.git] / board / w7o / w7o.c

/*
 * (C) Copyright 2001
 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include "w7o.h"
#include <asm/processor.h>

#include "vpd.h"
#include "errors.h"
#include <watchdog.h>

unsigned long get_dram_size (void);
void sdram_init(void);

/*
 * Macros to transform values
 * into environment strings.
 */
#define XMK_STR(x)	#x
#define MK_STR(x)	XMK_STR(x)

/* ------------------------------------------------------------------------- */

int board_early_init_f (void)
{
#if defined(CONFIG_W7OLMG)
	/*
	 * Setup GPIO pins - reset devices.
	 */
	out32 (PPC405GP_GPIO0_ODR, 0x10000000);	/* one open drain pin */
	out32 (PPC405GP_GPIO0_OR, 0x3E000000);	/* set output pins to default */
	out32 (PPC405GP_GPIO0_TCR, 0x7f800000);	/* setup for output */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
	 */
	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (uicer, 0x00000000);	/* disable all ints */

	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,
					   INT0 highest priority */

	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */

#elif defined(CONFIG_W7OLMC)
	/*
	 * Setup GPIO pins
	 */
	out32 (PPC405GP_GPIO0_ODR, 0x01800000);	/* XCV Done Open Drain */
	out32 (PPC405GP_GPIO0_OR, 0x03800000);	/* set out pins to default */
	out32 (PPC405GP_GPIO0_TCR, 0x66C00000);	/* setup for output */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
	 */
	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (uicer, 0x00000000);	/* disable all ints */

	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,
					   INT0 highest priority */

	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */

#else  /* Unknown */
#    error "Unknown W7O board configuration"
#endif

	WATCHDOG_RESET ();	/* Reset the watchdog */
	temp_uart_init ();	/* init the uart for debug */
	WATCHDOG_RESET ();	/* Reset the watchdog */
	test_led ();		/* test the LEDs */
	test_sdram (get_dram_size ());	/* test the dram */
	log_stat (ERR_POST1);	/* log status,post1 complete */
	return 0;
}


/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */
int checkboard (void)
{
	VPD vpd;

	puts ("Board: ");

	/* VPD data present in I2C EEPROM */
	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
		/*
		 * Known board type.
		 */
		if (vpd.productId[0] &&
		    ((strncmp (vpd.productId, "GMM", 3) == 0) ||
		     (strncmp (vpd.productId, "CMM", 3) == 0))) {

			/* Output board information on startup */
			printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
			return (0);
		}
	}

	puts ("### Unknown HW ID - assuming NOTHING\n");
	return (0);
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	/*
	 * ToDo: Move the asm init routine sdram_init() to this C file,
	 * or even better use some common ppc4xx code available
	 * in cpu/ppc4xx
	 */
	sdram_init();

	return get_dram_size ();
}

unsigned long get_dram_size (void)
{
	int tmp, i, regs[4];
	int size = 0;

	/* Get bank Size registers */
	mtdcr (memcfga, mem_mb0cf);	/* get bank 0 config reg */
	regs[0] = mfdcr (memcfgd);

	mtdcr (memcfga, mem_mb1cf);	/* get bank 1 config reg */
	regs[1] = mfdcr (memcfgd);

	mtdcr (memcfga, mem_mb2cf);	/* get bank 2 config reg */
	regs[2] = mfdcr (memcfgd);

	mtdcr (memcfga, mem_mb3cf);	/* get bank 3 config reg */
	regs[3] = mfdcr (memcfgd);

	/* compute the size, add each bank if enabled */
	for (i = 0; i < 4; i++) {
		if (regs[i] & 0x0001) {	/* if enabled, */
			tmp = ((regs[i] >> (31 - 14)) & 0x7);	/* get size bits */
			tmp = 0x400000 << tmp;	/* Size bits X 4MB = size */
			size += tmp;
		}
	}

	return size;
}

int misc_init_f (void)
{
	return 0;
}

static void w7o_env_init (VPD * vpd)
{
	/*
	 * Read VPD
	 */
	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
		return;

	/*
	 * Known board type.
	 */
	if (vpd->productId[0] &&
	    ((strncmp (vpd->productId, "GMM", 3) == 0) ||
	     (strncmp (vpd->productId, "CMM", 3) == 0))) {
		char buf[30];
		char *eth;
		char *serial = getenv ("serial#");
		char *ethaddr = getenv ("ethaddr");

		/* Set 'serial#' envvar if serial# isn't set */
		if (!serial) {
			sprintf (buf, "%s-%ld", vpd->productId,
				 vpd->serialNum);
			setenv ("serial#", buf);
		}

		/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
		eth = (char *)(vpd->ethAddrs[0]);
		if (ethaddr
		    && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
			/* Now setup ethaddr */
			sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
				 eth[0], eth[1], eth[2], eth[3], eth[4],
				 eth[5]);
			setenv ("ethaddr", buf);
		}
	}
}				/* w7o_env_init() */


int misc_init_r (void)
{
	VPD vpd;		/* VPD information */

#if defined(CONFIG_W7OLMG)
	unsigned long greg;	/* GPIO Register */

	greg = in32 (PPC405GP_GPIO0_OR);

	/*
	 * XXX - Unreset devices - this should be moved into VxWorks driver code
	 */
	greg |= 0x41800000L;	/* SAM, PHY, Galileo */

	out32 (PPC405GP_GPIO0_OR, greg);	/* set output pins to default */
#endif /* CONFIG_W7OLMG */

	/*
	 * Initialize W7O environment variables
	 */
	w7o_env_init (&vpd);

	/*
	 * Initialize the FPGA(s).
	 */
	if (init_fpga () == 0)
		test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);

	/* More POST testing. */
	post2 ();

	/* Done with hardware initialization and POST. */
	log_stat (ERR_POSTOK);

	/* Call silly, fail safe boot init routine */
	init_fsboot ();

	return (0);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
8bde7f77	25	#include <command.h>
c609719b WD	26	#include "w7o.h"
	27	#include <asm/processor.h>
	28
	29	#include "vpd.h"
	30	#include "errors.h"
	31	#include <watchdog.h>
	32
c83bf6a2	33	unsigned long get_dram_size (void);
bbeff30c	34	void sdram_init(void);
c609719b WD	35
	36	/*
	37	* Macros to transform values
	38	* into environment strings.
	39	*/
	40	#define XMK_STR(x) #x
	41	#define MK_STR(x) XMK_STR(x)
	42
	43	/* ------------------------------------------------------------------------- */
	44
c837dcb1	45	int board_early_init_f (void)
c609719b WD	46	{
c609719b WD	47	#if defined(CONFIG_W7OLMG)
c83bf6a2 WD	48	/*
	49	* Setup GPIO pins - reset devices.
	50	*/
0c8721a4 WD	51	out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
	52	out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
	53	out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
c83bf6a2 WD	54
	55	/*
	56	* IRQ 0-15 405GP internally generated; active high; level sensitive
	57	* IRQ 16 405GP internally generated; active low; level sensitive
	58	* IRQ 17-24 RESERVED
	59	* IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
	60	* IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
	61	* IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
	62	* IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
	63	* IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
	64	* IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
	65	* IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
	66	*/
	67	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
	68	mtdcr (uicer, 0x00000000); /* disable all ints */
	69
	70	mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
	71	mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
	72	mtdcr (uictr, 0x10000000); /* set int trigger levels */
	73	mtdcr (uicvcr, 0x00000001); /* set vect base=0,
	74	INT0 highest priority */
	75
	76	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
c609719b WD	77
c609719b WD	78	#elif defined(CONFIG_W7OLMC)
c83bf6a2 WD	79	/*
	80	* Setup GPIO pins
	81	*/
0c8721a4 WD	82	out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
	83	out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
	84	out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
c83bf6a2 WD	85
	86	/*
	87	* IRQ 0-15 405GP internally generated; active high; level sensitive
	88	* IRQ 16 405GP internally generated; active low; level sensitive
	89	* IRQ 17-24 RESERVED
	90	* IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
	91	* IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
	92	* IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
	93	* IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
	94	* IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
	95	* IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
	96	* IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
	97	*/
	98	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
	99	mtdcr (uicer, 0x00000000); /* disable all ints */
	100
	101	mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
	102	mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
	103	mtdcr (uictr, 0x10000000); /* set int trigger levels */
	104	mtdcr (uicvcr, 0x00000001); /* set vect base=0,
	105	INT0 highest priority */
	106
	107	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
	108
	109	#else /* Unknown */
c609719b WD	110	# error "Unknown W7O board configuration"
	111	#endif
	112
c83bf6a2 WD	113	WATCHDOG_RESET (); /* Reset the watchdog */
	114	temp_uart_init (); /* init the uart for debug */
	115	WATCHDOG_RESET (); /* Reset the watchdog */
	116	test_led (); /* test the LEDs */
	117	test_sdram (get_dram_size ()); /* test the dram */
	118	log_stat (ERR_POST1); /* log status,post1 complete */
	119	return 0;
c609719b WD	120	}
	121
	122
	123	/* ------------------------------------------------------------------------- */
	124
	125	/*
	126	* Check Board Identity:
	127	*/
	128	int checkboard (void)
	129	{
c83bf6a2 WD	130	VPD vpd;
	131
	132	puts ("Board: ");
	133
	134	/* VPD data present in I2C EEPROM */
6d0f6bcf	135	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
c83bf6a2 WD	136	/*
	137	* Known board type.
	138	*/
	139	if (vpd.productId[0] &&
	140	((strncmp (vpd.productId, "GMM", 3) == 0) \|\|
	141	(strncmp (vpd.productId, "CMM", 3) == 0))) {
	142
	143	/* Output board information on startup */
	144	printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
	145	return (0);
	146	}
c609719b	147	}
c609719b	148
c83bf6a2 WD	149	puts ("### Unknown HW ID - assuming NOTHING\n");
c83bf6a2 WD	150	return (0);
c609719b WD	151	}
	152
	153	/* ------------------------------------------------------------------------- */
	154
9973e3c6	155	phys_size_t initdram (int board_type)
c609719b	156	{
bbeff30c SR	157	/*
	158	* ToDo: Move the asm init routine sdram_init() to this C file,
	159	* or even better use some common ppc4xx code available
	160	* in cpu/ppc4xx
	161	*/
	162	sdram_init();
	163
c83bf6a2	164	return get_dram_size ();
c609719b WD	165	}
	166
	167	unsigned long get_dram_size (void)
	168	{
c83bf6a2 WD	169	int tmp, i, regs[4];
c83bf6a2 WD	170	int size = 0;
c609719b	171
c83bf6a2 WD	172	/* Get bank Size registers */
	173	mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */
	174	regs[0] = mfdcr (memcfgd);
c609719b	175
c83bf6a2 WD	176	mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */
c83bf6a2 WD	177	regs[1] = mfdcr (memcfgd);
c609719b	178
c83bf6a2 WD	179	mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */
c83bf6a2 WD	180	regs[2] = mfdcr (memcfgd);
c609719b	181
c83bf6a2 WD	182	mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */
c83bf6a2 WD	183	regs[3] = mfdcr (memcfgd);
c609719b	184
c83bf6a2 WD	185	/* compute the size, add each bank if enabled */
	186	for (i = 0; i < 4; i++) {
	187	if (regs[i] & 0x0001) { /* if enabled, */
	188	tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
	189	tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
	190	size += tmp;
	191	}
c609719b	192	}
c609719b	193
c83bf6a2	194	return size;
c609719b WD	195	}
	196
	197	int misc_init_f (void)
	198	{
c83bf6a2	199	return 0;
c609719b WD	200	}
c609719b WD	201
c83bf6a2	202	static void w7o_env_init (VPD * vpd)
c609719b	203	{
c83bf6a2 WD	204	/*
	205	* Read VPD
	206	*/
6d0f6bcf	207	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
c83bf6a2	208	return;
c609719b	209
c83bf6a2 WD	210	/*
	211	* Known board type.
	212	*/
	213	if (vpd->productId[0] &&
	214	((strncmp (vpd->productId, "GMM", 3) == 0) \|\|
	215	(strncmp (vpd->productId, "CMM", 3) == 0))) {
	216	char buf[30];
	217	char *eth;
77ddac94 WD	218	char *serial = getenv ("serial#");
77ddac94 WD	219	char *ethaddr = getenv ("ethaddr");
c83bf6a2 WD	220
	221	/* Set 'serial#' envvar if serial# isn't set */
	222	if (!serial) {
	223	sprintf (buf, "%s-%ld", vpd->productId,
	224	vpd->serialNum);
	225	setenv ("serial#", buf);
	226	}
	227
	228	/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
77ddac94	229	eth = (char *)(vpd->ethAddrs[0]);
c83bf6a2 WD	230	if (ethaddr
	231	&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
	232	/* Now setup ethaddr */
	233	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
	234	eth[0], eth[1], eth[2], eth[3], eth[4],
	235	eth[5]);
	236	setenv ("ethaddr", buf);
	237	}
c609719b	238	}
c83bf6a2	239	} /* w7o_env_init() */
c609719b WD	240
	241
	242	int misc_init_r (void)
	243	{
c83bf6a2	244	VPD vpd; /* VPD information */
c609719b WD	245
c609719b WD	246	#if defined(CONFIG_W7OLMG)
c83bf6a2	247	unsigned long greg; /* GPIO Register */
c609719b	248
0c8721a4	249	greg = in32 (PPC405GP_GPIO0_OR);
c609719b	250
c83bf6a2 WD	251	/*
	252	* XXX - Unreset devices - this should be moved into VxWorks driver code
	253	*/
	254	greg \|= 0x41800000L; /* SAM, PHY, Galileo */
c609719b	255
0c8721a4	256	out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
c609719b WD	257	#endif /* CONFIG_W7OLMG */
c609719b WD	258
c83bf6a2 WD	259	/*
	260	* Initialize W7O environment variables
	261	*/
	262	w7o_env_init (&vpd);
c609719b	263
c83bf6a2 WD	264	/*
	265	* Initialize the FPGA(s).
	266	*/
	267	if (init_fpga () == 0)
	268	test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
c609719b	269
c83bf6a2 WD	270	/* More POST testing. */
c83bf6a2 WD	271	post2 ();
c609719b	272
c83bf6a2 WD	273	/* Done with hardware initialization and POST. */
c83bf6a2 WD	274	log_stat (ERR_POSTOK);
c609719b	275
c83bf6a2 WD	276	/* Call silly, fail safe boot init routine */
c83bf6a2 WD	277	init_fsboot ();
c609719b WD	278
	279	return (0);
	280	}