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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include "w7o.h" | |
26 | #include <asm/processor.h> | |
27 | ||
28 | #include "vpd.h" | |
29 | #include "errors.h" | |
30 | #include <watchdog.h> | |
31 | ||
32 | unsigned long get_dram_size(void); | |
33 | ||
34 | /* | |
35 | * Macros to transform values | |
36 | * into environment strings. | |
37 | */ | |
38 | #define XMK_STR(x) #x | |
39 | #define MK_STR(x) XMK_STR(x) | |
40 | ||
41 | /* ------------------------------------------------------------------------- */ | |
42 | ||
43 | int board_pre_init (void) | |
44 | { | |
45 | #if defined(CONFIG_W7OLMG) | |
46 | /* | |
47 | * Setup GPIO pins - reset devices. | |
48 | */ | |
49 | out32(IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ | |
50 | out32(IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ | |
51 | out32(IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ | |
52 | ||
53 | /* | |
54 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
55 | * IRQ 16 405GP internally generated; active low; level sensitive | |
56 | * IRQ 17-24 RESERVED | |
57 | * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive | |
58 | * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive | |
59 | * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive | |
60 | * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive | |
61 | * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive | |
62 | * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive | |
63 | * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive | |
64 | */ | |
65 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
66 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
67 | ||
68 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
69 | mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ | |
70 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ | |
71 | mtdcr(uicvcr, 0x00000001); /* set vect base=0, | |
72 | INT0 highest priority*/ | |
73 | ||
74 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
75 | ||
76 | #elif defined(CONFIG_W7OLMC) | |
77 | /* | |
78 | * Setup GPIO pins | |
79 | */ | |
80 | out32(IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ | |
81 | out32(IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ | |
82 | out32(IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ | |
83 | ||
84 | /* | |
85 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
86 | * IRQ 16 405GP internally generated; active low; level sensitive | |
87 | * IRQ 17-24 RESERVED | |
88 | * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive | |
89 | * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive | |
90 | * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive | |
91 | * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive | |
92 | * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive | |
93 | * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive | |
94 | * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive | |
95 | */ | |
96 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
97 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
98 | ||
99 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
100 | mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ | |
101 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ | |
102 | mtdcr(uicvcr, 0x00000001); /* set vect base=0, | |
103 | INT0 highest priority*/ | |
104 | ||
105 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
106 | ||
107 | #else /* Unknown */ | |
108 | # error "Unknown W7O board configuration" | |
109 | #endif | |
110 | ||
111 | WATCHDOG_RESET(); /* Reset the watchdog */ | |
112 | temp_uart_init(); /* init the uart for debug */ | |
113 | WATCHDOG_RESET(); /* Reset the watchdog */ | |
114 | test_led(); /* test the LEDs */ | |
115 | test_sdram(get_dram_size()); /* test the dram */ | |
116 | log_stat(ERR_POST1); /* log status,post1 complete */ | |
117 | return 0; | |
118 | } | |
119 | ||
120 | ||
121 | /* ------------------------------------------------------------------------- */ | |
122 | ||
123 | /* | |
124 | * Check Board Identity: | |
125 | */ | |
126 | int checkboard (void) | |
127 | { | |
128 | VPD vpd; | |
129 | ||
130 | puts ("Board: "); | |
131 | ||
132 | /* VPD data present in I2C EEPROM */ | |
133 | if (vpd_get_data(CFG_DEF_EEPROM_ADDR, &vpd) == 0) { | |
134 | /* | |
135 | * Known board type. | |
136 | */ | |
137 | if (vpd.productId[0] && | |
138 | ((strncmp(vpd.productId, "GMM", 3) == 0) || | |
139 | (strncmp(vpd.productId, "CMM", 3) == 0))) { | |
140 | ||
141 | /* Output board information on startup */ | |
142 | printf("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", | |
143 | vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID); | |
144 | return (0); | |
145 | } | |
146 | } | |
147 | ||
148 | puts ("### Unknown HW ID - assuming NOTHING\n"); | |
149 | return (0); | |
150 | } | |
151 | ||
152 | /* ------------------------------------------------------------------------- */ | |
153 | ||
154 | long int initdram (int board_type) | |
155 | { | |
156 | return get_dram_size(); | |
157 | } | |
158 | ||
159 | unsigned long get_dram_size (void) | |
160 | { | |
161 | int tmp, i, regs[4]; | |
162 | int size = 0; | |
163 | ||
164 | /* Get bank Size registers */ | |
165 | mtdcr(memcfga, mem_mb0cf); /* get bank 0 config reg */ | |
166 | regs[0] = mfdcr(memcfgd); | |
167 | ||
168 | mtdcr(memcfga, mem_mb1cf); /* get bank 1 config reg */ | |
169 | regs[1] = mfdcr(memcfgd); | |
170 | ||
171 | mtdcr(memcfga, mem_mb2cf); /* get bank 2 config reg */ | |
172 | regs[2] = mfdcr(memcfgd); | |
173 | ||
174 | mtdcr(memcfga, mem_mb3cf); /* get bank 3 config reg */ | |
175 | regs[3] = mfdcr(memcfgd); | |
176 | ||
177 | /* compute the size, add each bank if enabled */ | |
178 | for(i = 0; i < 4; i++) { | |
179 | if (regs[i] & 0x0001) { /* if enabled, */ | |
180 | tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */ | |
181 | tmp = 0x400000 << tmp; /* Size bits X 4MB = size */ | |
182 | size += tmp; | |
183 | } | |
184 | } | |
185 | ||
186 | return size; | |
187 | } | |
188 | ||
189 | int misc_init_f (void) | |
190 | { | |
191 | return 0; | |
192 | } | |
193 | ||
194 | static void | |
195 | w7o_env_init(VPD *vpd) | |
196 | { | |
197 | /* | |
198 | * Read VPD | |
199 | */ | |
200 | if (vpd_get_data(CFG_DEF_EEPROM_ADDR, vpd) != 0) | |
201 | return; | |
202 | ||
203 | /* | |
204 | * Known board type. | |
205 | */ | |
206 | if (vpd->productId[0] && | |
207 | ((strncmp(vpd->productId, "GMM", 3) == 0) || | |
208 | (strncmp(vpd->productId, "CMM", 3) == 0))) { | |
209 | char buf[30]; | |
210 | char *eth; | |
211 | unsigned char *serial = getenv("serial#"); | |
212 | unsigned char *ethaddr = getenv("ethaddr"); | |
213 | ||
214 | /* Set 'serial#' envvar if serial# isn't set */ | |
215 | if (!serial) { | |
216 | sprintf(buf, "%s-%ld", vpd->productId, vpd->serialNum); | |
217 | setenv("serial#", buf); | |
218 | } | |
219 | ||
220 | /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ | |
221 | eth = vpd->ethAddrs[0]; | |
222 | if (ethaddr && (strcmp(ethaddr, MK_STR(CONFIG_ETHADDR)) == 0)) { | |
223 | /* Now setup ethaddr */ | |
224 | sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", | |
225 | eth[0], eth[1], eth[2], eth[3], eth[4], eth[5]); | |
226 | setenv("ethaddr", buf); | |
227 | } | |
228 | } | |
229 | } /* w7o_env_init() */ | |
230 | ||
231 | ||
232 | int misc_init_r (void) | |
233 | { | |
234 | VPD vpd; /* VPD information */ | |
235 | ||
236 | #if defined(CONFIG_W7OLMG) | |
237 | unsigned long greg; /* GPIO Register */ | |
238 | ||
239 | greg = in32(IBM405GP_GPIO0_OR); | |
240 | ||
241 | /* | |
242 | * XXX - Unreset devices - this should be moved into VxWorks driver code | |
243 | */ | |
244 | greg |= 0x41800000L; /* SAM, PHY, Galileo */ | |
245 | ||
246 | out32(IBM405GP_GPIO0_OR, greg); /* set output pins to default */ | |
247 | #endif /* CONFIG_W7OLMG */ | |
248 | ||
249 | /* | |
250 | * Initialize W7O environment variables | |
251 | */ | |
252 | w7o_env_init(&vpd); | |
253 | ||
254 | /* | |
255 | * Initialize the FPGA(s). | |
256 | */ | |
257 | if (init_fpga() == 0) | |
258 | test_fpga((unsigned short *)CONFIG_FPGAS_BASE); | |
259 | ||
260 | /* More POST testing. */ | |
261 | post2(); | |
262 | ||
263 | /* Done with hardware initialization and POST. */ | |
264 | log_stat(ERR_POSTOK); | |
265 | ||
266 | /* Call silly, fail safe boot init routine */ | |
267 | init_fsboot(); | |
268 | ||
269 | return (0); | |
270 | } | |
271 |