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1 | /* |
2 | * Copyright (C) 2014 Wandboard | |
3 | * Author: Tungyi Lin <tungyilin1127@gmail.com> | |
4 | * Richard Hu <hakahu@gmail.com> | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <asm/arch/clock.h> | |
9 | #include <asm/arch/imx-regs.h> | |
10 | #include <asm/arch/iomux.h> | |
11 | #include <asm/arch/mx6-pins.h> | |
1221ce45 | 12 | #include <linux/errno.h> |
0d1ea052 FE |
13 | #include <asm/gpio.h> |
14 | #include <asm/imx-common/iomux-v3.h> | |
15 | #include <asm/imx-common/video.h> | |
16 | #include <mmc.h> | |
17 | #include <fsl_esdhc.h> | |
18 | #include <asm/arch/crm_regs.h> | |
19 | #include <asm/io.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <spl.h> | |
22 | ||
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
25 | #if defined(CONFIG_SPL_BUILD) | |
26 | #include <asm/arch/mx6-ddr.h> | |
27 | /* | |
28 | * Driving strength: | |
29 | * 0x30 == 40 Ohm | |
30 | * 0x28 == 48 Ohm | |
31 | */ | |
32 | ||
33 | #define IMX6DQ_DRIVE_STRENGTH 0x30 | |
34 | #define IMX6SDL_DRIVE_STRENGTH 0x28 | |
35 | ||
36 | /* configure MX6Q/DUAL mmdc DDR io registers */ | |
37 | static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { | |
38 | .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, | |
39 | .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, | |
40 | .dram_cas = IMX6DQ_DRIVE_STRENGTH, | |
41 | .dram_ras = IMX6DQ_DRIVE_STRENGTH, | |
42 | .dram_reset = IMX6DQ_DRIVE_STRENGTH, | |
43 | .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, | |
44 | .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, | |
45 | .dram_sdba2 = 0x00000000, | |
46 | .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, | |
47 | .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, | |
48 | .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, | |
49 | .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, | |
50 | .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, | |
51 | .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, | |
52 | .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, | |
53 | .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, | |
54 | .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, | |
55 | .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, | |
56 | .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, | |
57 | .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, | |
58 | .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, | |
59 | .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, | |
60 | .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, | |
61 | .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, | |
62 | .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, | |
63 | .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, | |
64 | }; | |
65 | ||
66 | /* configure MX6Q/DUAL mmdc GRP io registers */ | |
67 | static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { | |
68 | .grp_ddr_type = 0x000c0000, | |
69 | .grp_ddrmode_ctl = 0x00020000, | |
70 | .grp_ddrpke = 0x00000000, | |
71 | .grp_addds = IMX6DQ_DRIVE_STRENGTH, | |
72 | .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, | |
73 | .grp_ddrmode = 0x00020000, | |
74 | .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, | |
75 | .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, | |
76 | .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, | |
77 | .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, | |
78 | .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, | |
79 | .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, | |
80 | .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, | |
81 | .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, | |
82 | }; | |
83 | ||
84 | /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ | |
85 | struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { | |
86 | .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, | |
87 | .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, | |
88 | .dram_cas = IMX6SDL_DRIVE_STRENGTH, | |
89 | .dram_ras = IMX6SDL_DRIVE_STRENGTH, | |
90 | .dram_reset = IMX6SDL_DRIVE_STRENGTH, | |
91 | .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, | |
92 | .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, | |
93 | .dram_sdba2 = 0x00000000, | |
94 | .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, | |
95 | .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, | |
96 | .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, | |
97 | .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, | |
98 | .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, | |
99 | .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, | |
100 | .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, | |
101 | .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, | |
102 | .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, | |
103 | .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, | |
104 | .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, | |
105 | .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, | |
106 | .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, | |
107 | .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, | |
108 | .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, | |
109 | .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, | |
110 | .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, | |
111 | .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, | |
112 | }; | |
113 | ||
114 | /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ | |
115 | struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { | |
116 | .grp_ddr_type = 0x000c0000, | |
117 | .grp_ddrmode_ctl = 0x00020000, | |
118 | .grp_ddrpke = 0x00000000, | |
119 | .grp_addds = IMX6SDL_DRIVE_STRENGTH, | |
120 | .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, | |
121 | .grp_ddrmode = 0x00020000, | |
122 | .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, | |
123 | .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, | |
124 | .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, | |
125 | .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, | |
126 | .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, | |
127 | .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, | |
128 | .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, | |
129 | .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, | |
130 | }; | |
131 | ||
132 | /* H5T04G63AFR-PB */ | |
133 | static struct mx6_ddr3_cfg h5t04g63afr = { | |
134 | .mem_speed = 1600, | |
135 | .density = 4, | |
136 | .width = 16, | |
137 | .banks = 8, | |
138 | .rowaddr = 15, | |
139 | .coladdr = 10, | |
140 | .pagesz = 2, | |
141 | .trcd = 1375, | |
142 | .trcmin = 4875, | |
143 | .trasmin = 3500, | |
144 | }; | |
145 | ||
146 | /* H5TQ2G63DFR-H9 */ | |
147 | static struct mx6_ddr3_cfg h5tq2g63dfr = { | |
148 | .mem_speed = 1333, | |
149 | .density = 2, | |
150 | .width = 16, | |
151 | .banks = 8, | |
152 | .rowaddr = 14, | |
153 | .coladdr = 10, | |
154 | .pagesz = 2, | |
155 | .trcd = 1350, | |
156 | .trcmin = 4950, | |
157 | .trasmin = 3600, | |
158 | }; | |
159 | ||
160 | static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = { | |
161 | .p0_mpwldectrl0 = 0x001f001f, | |
162 | .p0_mpwldectrl1 = 0x001f001f, | |
163 | .p1_mpwldectrl0 = 0x001f001f, | |
164 | .p1_mpwldectrl1 = 0x001f001f, | |
165 | .p0_mpdgctrl0 = 0x4301030d, | |
166 | .p0_mpdgctrl1 = 0x03020277, | |
167 | .p1_mpdgctrl0 = 0x4300030a, | |
168 | .p1_mpdgctrl1 = 0x02780248, | |
169 | .p0_mprddlctl = 0x4536393b, | |
170 | .p1_mprddlctl = 0x36353441, | |
171 | .p0_mpwrdlctl = 0x41414743, | |
172 | .p1_mpwrdlctl = 0x462f453f, | |
173 | }; | |
174 | ||
175 | /* DDR 64bit 2GB */ | |
176 | static struct mx6_ddr_sysinfo mem_q = { | |
177 | .dsize = 2, | |
178 | .cs1_mirror = 0, | |
179 | /* config for full 4GB range so that get_mem_size() works */ | |
180 | .cs_density = 32, | |
181 | .ncs = 1, | |
182 | .bi_on = 1, | |
183 | .rtt_nom = 1, | |
184 | .rtt_wr = 0, | |
185 | .ralat = 5, | |
186 | .walat = 0, | |
187 | .mif3_mode = 3, | |
188 | .rst_to_cke = 0x23, | |
189 | .sde_to_rst = 0x10, | |
edf00937 | 190 | .refsel = 1, /* Refresh cycles at 32KHz */ |
ba4e159f | 191 | .refr = 3, /* 4 refresh commands per refresh cycle */ |
0d1ea052 FE |
192 | }; |
193 | ||
194 | static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { | |
195 | .p0_mpwldectrl0 = 0x001f001f, | |
196 | .p0_mpwldectrl1 = 0x001f001f, | |
197 | .p1_mpwldectrl0 = 0x001f001f, | |
198 | .p1_mpwldectrl1 = 0x001f001f, | |
199 | .p0_mpdgctrl0 = 0x420e020e, | |
200 | .p0_mpdgctrl1 = 0x02000200, | |
201 | .p1_mpdgctrl0 = 0x42020202, | |
202 | .p1_mpdgctrl1 = 0x01720172, | |
203 | .p0_mprddlctl = 0x494c4f4c, | |
204 | .p1_mprddlctl = 0x4a4c4c49, | |
205 | .p0_mpwrdlctl = 0x3f3f3133, | |
206 | .p1_mpwrdlctl = 0x39373f2e, | |
207 | }; | |
208 | ||
209 | static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = { | |
210 | .p0_mpwldectrl0 = 0x0040003c, | |
211 | .p0_mpwldectrl1 = 0x0032003e, | |
212 | .p0_mpdgctrl0 = 0x42350231, | |
213 | .p0_mpdgctrl1 = 0x021a0218, | |
214 | .p0_mprddlctl = 0x4b4b4e49, | |
215 | .p0_mpwrdlctl = 0x3f3f3035, | |
216 | }; | |
217 | ||
218 | /* DDR 64bit 1GB */ | |
219 | static struct mx6_ddr_sysinfo mem_dl = { | |
220 | .dsize = 2, | |
221 | .cs1_mirror = 0, | |
222 | /* config for full 4GB range so that get_mem_size() works */ | |
223 | .cs_density = 32, | |
224 | .ncs = 1, | |
225 | .bi_on = 1, | |
226 | .rtt_nom = 1, | |
227 | .rtt_wr = 0, | |
228 | .ralat = 5, | |
229 | .walat = 0, | |
230 | .mif3_mode = 3, | |
231 | .rst_to_cke = 0x23, | |
232 | .sde_to_rst = 0x10, | |
edf00937 | 233 | .refsel = 1, /* Refresh cycles at 32KHz */ |
ba4e159f | 234 | .refr = 3, /* 4 refresh commands per refresh cycle */ |
0d1ea052 FE |
235 | }; |
236 | ||
237 | /* DDR 32bit 512MB */ | |
238 | static struct mx6_ddr_sysinfo mem_s = { | |
239 | .dsize = 1, | |
240 | .cs1_mirror = 0, | |
241 | /* config for full 4GB range so that get_mem_size() works */ | |
242 | .cs_density = 32, | |
243 | .ncs = 1, | |
244 | .bi_on = 1, | |
245 | .rtt_nom = 1, | |
246 | .rtt_wr = 0, | |
247 | .ralat = 5, | |
248 | .walat = 0, | |
249 | .mif3_mode = 3, | |
250 | .rst_to_cke = 0x23, | |
251 | .sde_to_rst = 0x10, | |
edf00937 | 252 | .refsel = 1, /* Refresh cycles at 32KHz */ |
ba4e159f | 253 | .refr = 3, /* 4 refresh commands per refresh cycle */ |
0d1ea052 FE |
254 | }; |
255 | ||
256 | static void ccgr_init(void) | |
257 | { | |
258 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
259 | ||
260 | writel(0x00C03F3F, &ccm->CCGR0); | |
261 | writel(0x0030FC03, &ccm->CCGR1); | |
262 | writel(0x0FFFC000, &ccm->CCGR2); | |
263 | writel(0x3FF00000, &ccm->CCGR3); | |
264 | writel(0x00FFF300, &ccm->CCGR4); | |
265 | writel(0x0F0000C3, &ccm->CCGR5); | |
266 | writel(0x000003FF, &ccm->CCGR6); | |
267 | } | |
268 | ||
269 | static void gpr_init(void) | |
270 | { | |
271 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
272 | ||
273 | /* enable AXI cache for VDOA/VPU/IPU */ | |
274 | writel(0xF00000CF, &iomux->gpr[4]); | |
275 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ | |
276 | writel(0x007F007F, &iomux->gpr[6]); | |
277 | writel(0x007F007F, &iomux->gpr[7]); | |
278 | } | |
279 | ||
280 | static void spl_dram_init(void) | |
281 | { | |
282 | if (is_cpu_type(MXC_CPU_MX6SOLO)) { | |
283 | mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
284 | mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); | |
285 | } else if (is_cpu_type(MXC_CPU_MX6DL)) { | |
286 | mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
287 | mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr); | |
288 | } else if (is_cpu_type(MXC_CPU_MX6Q)) { | |
289 | mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); | |
290 | mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr); | |
291 | } | |
292 | ||
293 | udelay(100); | |
294 | } | |
295 | ||
296 | void board_init_f(ulong dummy) | |
297 | { | |
298 | ccgr_init(); | |
299 | ||
300 | /* setup AIPS and disable watchdog */ | |
301 | arch_cpu_init(); | |
302 | ||
303 | gpr_init(); | |
304 | ||
305 | /* iomux */ | |
306 | board_early_init_f(); | |
307 | ||
308 | /* setup GP timer */ | |
309 | timer_init(); | |
310 | ||
311 | /* UART clocks enabled and gd valid - init serial console */ | |
312 | preloader_console_init(); | |
313 | ||
314 | /* DDR initialization */ | |
315 | spl_dram_init(); | |
316 | ||
317 | /* Clear the BSS. */ | |
318 | memset(__bss_start, 0, __bss_end - __bss_start); | |
319 | ||
320 | /* load/boot image from boot device */ | |
321 | board_init_r(NULL, 0); | |
322 | } | |
323 | #endif |