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e2d282a1 FE |
1 | /* |
2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
e2d282a1 FE |
7 | */ |
8 | ||
9 | #include <asm/arch/clock.h> | |
7bcb983f | 10 | #include <asm/arch/crm_regs.h> |
e2d282a1 FE |
11 | #include <asm/arch/iomux.h> |
12 | #include <asm/arch/imx-regs.h> | |
13 | #include <asm/arch/mx6-pins.h> | |
7bcb983f | 14 | #include <asm/arch/mxc_hdmi.h> |
e2d282a1 FE |
15 | #include <asm/arch/sys_proto.h> |
16 | #include <asm/gpio.h> | |
17 | #include <asm/imx-common/iomux-v3.h> | |
eaffaa2d | 18 | #include <asm/imx-common/boot_mode.h> |
e2d282a1 FE |
19 | #include <asm/io.h> |
20 | #include <asm/sizes.h> | |
21 | #include <common.h> | |
22 | #include <fsl_esdhc.h> | |
7bcb983f | 23 | #include <ipu_pixfmt.h> |
e2d282a1 FE |
24 | #include <mmc.h> |
25 | #include <miiphy.h> | |
26 | #include <netdev.h> | |
7bcb983f | 27 | #include <linux/fb.h> |
e2d282a1 FE |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
7e2173cf BT |
31 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
32 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | |
33 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
e2d282a1 | 34 | |
7e2173cf BT |
35 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
36 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | |
37 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
e2d282a1 | 38 | |
7e2173cf BT |
39 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
40 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
e2d282a1 | 41 | |
5ed15738 | 42 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) |
08f32f7d | 43 | #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) |
e2d282a1 FE |
44 | #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) |
45 | ||
46 | int dram_init(void) | |
47 | { | |
491f2947 | 48 | gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; |
e2d282a1 FE |
49 | |
50 | return 0; | |
51 | } | |
52 | ||
53 | static iomux_v3_cfg_t const uart1_pads[] = { | |
54 | MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), | |
55 | MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), | |
56 | }; | |
57 | ||
5ed15738 OS |
58 | iomux_v3_cfg_t const usdhc1_pads[] = { |
59 | MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
60 | MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
61 | MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
62 | MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
63 | MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
64 | MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
65 | /* Carrier MicroSD Card Detect */ | |
66 | MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
67 | }; | |
68 | ||
e2d282a1 FE |
69 | static iomux_v3_cfg_t const usdhc3_pads[] = { |
70 | MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
71 | MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
72 | MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
73 | MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
74 | MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
75 | MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
08f32f7d OS |
76 | /* SOM MicroSD Card Detect */ |
77 | MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
e2d282a1 FE |
78 | }; |
79 | ||
80 | static iomux_v3_cfg_t const enet_pads[] = { | |
81 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
82 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
83 | MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
84 | MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
85 | MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
86 | MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
87 | MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
88 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
89 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
90 | MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
91 | MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
92 | MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
93 | MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
94 | MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
95 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
96 | /* AR8031 PHY Reset */ | |
97 | MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
98 | }; | |
99 | ||
100 | static void setup_iomux_uart(void) | |
101 | { | |
102 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | |
103 | } | |
104 | ||
105 | static void setup_iomux_enet(void) | |
106 | { | |
107 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
108 | ||
109 | /* Reset AR8031 PHY */ | |
110 | gpio_direction_output(ETH_PHY_RESET, 0); | |
111 | udelay(500); | |
112 | gpio_set_value(ETH_PHY_RESET, 1); | |
113 | } | |
114 | ||
5ed15738 | 115 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
e2d282a1 | 116 | {USDHC3_BASE_ADDR}, |
5ed15738 | 117 | {USDHC1_BASE_ADDR}, |
e2d282a1 FE |
118 | }; |
119 | ||
08f32f7d OS |
120 | int board_mmc_getcd(struct mmc *mmc) |
121 | { | |
122 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
123 | int ret = 0; | |
124 | ||
125 | switch (cfg->esdhc_base) { | |
5ed15738 OS |
126 | case USDHC1_BASE_ADDR: |
127 | ret = !gpio_get_value(USDHC1_CD_GPIO); | |
128 | break; | |
08f32f7d OS |
129 | case USDHC3_BASE_ADDR: |
130 | ret = !gpio_get_value(USDHC3_CD_GPIO); | |
131 | break; | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
e2d282a1 FE |
137 | int board_mmc_init(bd_t *bis) |
138 | { | |
5ed15738 OS |
139 | s32 status = 0; |
140 | u32 index = 0; | |
141 | ||
142 | /* | |
143 | * Following map is done: | |
144 | * (U-boot device node) (Physical Port) | |
145 | * mmc0 SOM MicroSD | |
146 | * mmc1 Carrier board MicroSD | |
147 | */ | |
148 | for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { | |
149 | switch (index) { | |
150 | case 0: | |
151 | imx_iomux_v3_setup_multiple_pads( | |
152 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | |
153 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
154 | usdhc_cfg[0].max_bus_width = 4; | |
155 | gpio_direction_input(USDHC3_CD_GPIO); | |
156 | break; | |
157 | case 1: | |
158 | imx_iomux_v3_setup_multiple_pads( | |
159 | usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); | |
160 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
161 | usdhc_cfg[1].max_bus_width = 4; | |
162 | gpio_direction_input(USDHC1_CD_GPIO); | |
163 | break; | |
164 | default: | |
165 | printf("Warning: you configured more USDHC controllers" | |
166 | "(%d) then supported by the board (%d)\n", | |
167 | index + 1, CONFIG_SYS_FSL_USDHC_NUM); | |
168 | return status; | |
169 | } | |
170 | ||
171 | status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); | |
172 | } | |
aad4659a | 173 | |
5ed15738 | 174 | return status; |
e2d282a1 FE |
175 | } |
176 | ||
177 | static int mx6_rgmii_rework(struct phy_device *phydev) | |
178 | { | |
179 | unsigned short val; | |
180 | ||
181 | /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ | |
182 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); | |
183 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); | |
184 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); | |
185 | ||
186 | val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); | |
187 | val &= 0xffe3; | |
188 | val |= 0x18; | |
189 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); | |
190 | ||
191 | /* introduce tx clock delay */ | |
192 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); | |
193 | val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); | |
194 | val |= 0x0100; | |
195 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | int board_phy_config(struct phy_device *phydev) | |
201 | { | |
202 | mx6_rgmii_rework(phydev); | |
203 | ||
204 | if (phydev->drv->config) | |
205 | phydev->drv->config(phydev); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
7bcb983f | 210 | #if defined(CONFIG_VIDEO_IPUV3) |
7bcb983f FE |
211 | static struct fb_videomode const hdmi = { |
212 | .name = "HDMI", | |
213 | .refresh = 60, | |
214 | .xres = 1024, | |
215 | .yres = 768, | |
216 | .pixclock = 15385, | |
217 | .left_margin = 220, | |
218 | .right_margin = 40, | |
219 | .upper_margin = 21, | |
220 | .lower_margin = 7, | |
221 | .hsync_len = 60, | |
222 | .vsync_len = 10, | |
223 | .sync = FB_SYNC_EXT, | |
224 | .vmode = FB_VMODE_NONINTERLACED | |
225 | }; | |
226 | ||
227 | int board_video_skip(void) | |
228 | { | |
229 | int ret; | |
230 | ||
231 | ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); | |
232 | ||
233 | if (ret) | |
234 | printf("HDMI cannot be configured: %d\n", ret); | |
235 | ||
5ea7f0e3 | 236 | imx_enable_hdmi_phy(); |
7bcb983f FE |
237 | |
238 | return ret; | |
239 | } | |
240 | ||
241 | static void setup_display(void) | |
242 | { | |
243 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
7bcb983f FE |
244 | int reg; |
245 | ||
5ea7f0e3 PKS |
246 | enable_ipu_clock(); |
247 | imx_setup_hdmi(); | |
7bcb983f FE |
248 | |
249 | reg = readl(&mxc_ccm->chsccdr); | |
7bcb983f | 250 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
5ea7f0e3 | 251 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
7bcb983f FE |
252 | writel(reg, &mxc_ccm->chsccdr); |
253 | } | |
254 | #endif /* CONFIG_VIDEO_IPUV3 */ | |
255 | ||
e2d282a1 FE |
256 | int board_eth_init(bd_t *bis) |
257 | { | |
258 | int ret; | |
259 | ||
260 | setup_iomux_enet(); | |
261 | ||
262 | ret = cpu_eth_init(bis); | |
263 | if (ret) | |
264 | printf("FEC MXC: %s:failed\n", __func__); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | int board_early_init_f(void) | |
270 | { | |
271 | setup_iomux_uart(); | |
7bcb983f FE |
272 | #if defined(CONFIG_VIDEO_IPUV3) |
273 | setup_display(); | |
274 | #endif | |
e2d282a1 FE |
275 | return 0; |
276 | } | |
277 | ||
7bcb983f FE |
278 | /* |
279 | * Do not overwrite the console | |
280 | * Use always serial for U-Boot console | |
281 | */ | |
282 | int overwrite_console(void) | |
283 | { | |
284 | return 1; | |
285 | } | |
286 | ||
eaffaa2d OS |
287 | #ifdef CONFIG_CMD_BMODE |
288 | static const struct boot_mode board_boot_modes[] = { | |
289 | /* 4 bit bus width */ | |
290 | {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
291 | {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, | |
292 | {NULL, 0}, | |
293 | }; | |
294 | #endif | |
295 | ||
296 | int board_late_init(void) | |
297 | { | |
298 | #ifdef CONFIG_CMD_BMODE | |
299 | add_board_boot_modes(board_boot_modes); | |
300 | #endif | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
e2d282a1 FE |
305 | int board_init(void) |
306 | { | |
307 | /* address of boot parameters */ | |
308 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
e2d282a1 FE |
313 | int checkboard(void) |
314 | { | |
315 | puts("Board: Wandboard\n"); | |
316 | ||
317 | return 0; | |
318 | } |