[thirdparty/u-boot.git] / board / warp7 / warp7.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 NXP Semiconductors
 * Author: Fabio Estevam <fabio.estevam@nxp.com>
 */

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../freescale/common/pfuze.h"
#include <asm/setup.h>
#include <asm/bootm.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
			PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |	\
			PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)

#define I2C_PAD_CTRL	(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)

#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
		.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
		.gp = IMX_GPIO_NR(4, 8),
	},
	.sda = {
		.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
		.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
		.gp = IMX_GPIO_NR(4, 9),
	},
};
#endif

int dram_init(void)
{
	gd->ram_size = PHYS_SDRAM_SIZE;

	/* Subtract the defined OPTEE runtime firmware length */
#ifdef CONFIG_OPTEE_TZDRAM_SIZE
		gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
#endif

	return 0;
}

static iomux_v3_cfg_t const wdog_pads[] = {
	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const uart1_pads[] = {
	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
};

static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
		/* Assume uSDHC3 emmc is always present */
		return 1;
}

int board_mmc_init(bd_t *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

#ifdef CONFIG_POWER
#define I2C_PMIC       0
static struct pmic *pfuze;
int power_init_board(void)
{
	int ret;
	unsigned int reg, rev_id;

	ret = power_pfuze3000_init(I2C_PMIC);
	if (ret)
		return ret;

	pfuze = pmic_get("PFUZE3000");
	ret = pmic_probe(pfuze);
	if (ret)
		return ret;

	pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
	pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);

	/* disable Low Power Mode during standby mode */
	pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);

	return 0;
}
#endif

int board_eth_init(bd_t *bis)
{
	int ret = 0;

#ifdef CONFIG_USB_ETHER
	ret = usb_eth_initialize(bis);
	if (ret < 0)
		printf("Error %d registering USB ether.\n", ret);
#endif

	return ret;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	#ifdef CONFIG_SYS_I2C_MXC
		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	#endif

	return 0;
}

int checkboard(void)
{
	char *mode;

	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
		mode = "secure";
	else
		mode = "non-secure";

#ifdef CONFIG_OPTEE_TZDRAM_SIZE
	unsigned long optee_start, optee_end;

	optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
	optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;

	printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
	       mode, optee_start, optee_end);
#else
	printf("Board: WARP7 in %s mode\n", mode);
#endif

	return 0;
}

int board_usb_phy_mode(int port)
{
	return USB_INIT_DEVICE;
}

int board_late_init(void)
{
	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
#ifdef CONFIG_SERIAL_TAG
	struct tag_serialnr serialnr;
	char serial_string[0x20];
#endif

	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

	set_wdog_reset(wdog);

	/*
	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
	 * since we use PMIC_PWRON to reset the board.
	 */
	clrsetbits_le16(&wdog->wcr, 0, 0x10);

#ifdef CONFIG_SECURE_BOOT
	/* Determine HAB state */
	env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
#else
	env_set_ulong(HAB_ENABLED_ENVNAME, 0);
#endif

#ifdef CONFIG_SERIAL_TAG
	/* Set serial# standard environment variable based on OTP settings */
	get_board_serial(&serialnr);
	snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
		 serialnr.low, serialnr.high);
	env_set("serial#", serial_string);
#endif

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
47173483 FE	2	/*
	3	* Copyright (C) 2016 NXP Semiconductors
	4	* Author: Fabio Estevam <fabio.estevam@nxp.com>
47173483 FE	5	*/
	6
	7	#include <asm/arch/clock.h>
	8	#include <asm/arch/imx-regs.h>
	9	#include <asm/arch/mx7-pins.h>
	10	#include <asm/arch/sys_proto.h>
	11	#include <asm/gpio.h>
a2accd84	12	#include <asm/mach-imx/hab.h>
552a848e SB	13	#include <asm/mach-imx/iomux-v3.h>
552a848e SB	14	#include <asm/mach-imx/mxc_i2c.h>
47173483 FE	15	#include <asm/io.h>
	16	#include <common.h>
	17	#include <fsl_esdhc.h>
7d301a59	18	#include <i2c.h>
47173483 FE	19	#include <mmc.h>
	20	#include <asm/arch/crm_regs.h>
	21	#include <usb.h>
25aaebdb	22	#include <netdev.h>
7d301a59 VM	23	#include <power/pmic.h>
	24	#include <power/pfuze3000_pmic.h>
	25	#include "../freescale/common/pfuze.h"
852cc548 BD	26	#include <asm/setup.h>
852cc548 BD	27	#include <asm/bootm.h>
47173483 FE	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM \| PAD_CTL_PUS_PU100KOHM \| \
	32	PAD_CTL_HYS)
	33	#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM \| PAD_CTL_SRE_SLOW \| \
	34	PAD_CTL_HYS \| PAD_CTL_PUE \| PAD_CTL_PUS_PU47KOHM)
	35
7d301a59 VM	36	#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM \| PAD_CTL_SRE_SLOW \| \
	37	PAD_CTL_HYS \| PAD_CTL_PUE \| PAD_CTL_PUS_PU100KOHM)
	38
	39	#ifdef CONFIG_SYS_I2C_MXC
	40	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	41	/* I2C1 for PMIC */
	42	static struct i2c_pads_info i2c_pad_info1 = {
	43	.scl = {
	44	.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL \| PC,
	45	.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 \| PC,
	46	.gp = IMX_GPIO_NR(4, 8),
	47	},
	48	.sda = {
	49	.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA \| PC,
	50	.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 \| PC,
	51	.gp = IMX_GPIO_NR(4, 9),
	52	},
	53	};
	54	#endif
	55
47173483 FE	56	int dram_init(void)
	57	{
	58	gd->ram_size = PHYS_SDRAM_SIZE;
	59
7175ef4a BD	60	/* Subtract the defined OPTEE runtime firmware length */
	61	#ifdef CONFIG_OPTEE_TZDRAM_SIZE
	62	gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
	63	#endif
	64
47173483 FE	65	return 0;
	66	}
	67
0a35cc93 MF	68	static iomux_v3_cfg_t const wdog_pads[] = {
	69	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B \| MUX_PAD_CTRL(NO_PAD_CTRL),
	70	};
	71
47173483 FE	72	static iomux_v3_cfg_t const uart1_pads[] = {
	73	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	74	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	75	};
	76
	77	static iomux_v3_cfg_t const usdhc3_pads[] = {
	78	MX7D_PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	79	MX7D_PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	80	MX7D_PAD_SD3_DATA0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	81	MX7D_PAD_SD3_DATA1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	82	MX7D_PAD_SD3_DATA2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	83	MX7D_PAD_SD3_DATA3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	84	MX7D_PAD_SD3_DATA4__SD3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	85	MX7D_PAD_SD3_DATA5__SD3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	86	MX7D_PAD_SD3_DATA6__SD3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	87	MX7D_PAD_SD3_DATA7__SD3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	88	MX7D_PAD_SD3_RESET_B__SD3_RESET_B \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	89	};
	90
	91	static void setup_iomux_uart(void)
	92	{
	93	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	94	};
	95
	96	static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	97	{USDHC3_BASE_ADDR},
	98	};
	99
	100	int board_mmc_getcd(struct mmc *mmc)
	101	{
	102	/* Assume uSDHC3 emmc is always present */
	103	return 1;
	104	}
	105
	106	int board_mmc_init(bd_t *bis)
	107	{
	108	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	109	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	110
	111	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	112	}
	113
	114	int board_early_init_f(void)
	115	{
	116	setup_iomux_uart();
	117
	118	return 0;
	119	}
	120
7d301a59 VM	121	#ifdef CONFIG_POWER
	122	#define I2C_PMIC 0
	123	static struct pmic *pfuze;
	124	int power_init_board(void)
	125	{
	126	int ret;
	127	unsigned int reg, rev_id;
	128
	129	ret = power_pfuze3000_init(I2C_PMIC);
	130	if (ret)
	131	return ret;
	132
	133	pfuze = pmic_get("PFUZE3000");
	134	ret = pmic_probe(pfuze);
	135	if (ret)
	136	return ret;
	137
	138	pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
	139	pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
	140	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
	141
	142	/* disable Low Power Mode during standby mode */
	143	pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
	144
	145	return 0;
	146	}
	147	#endif
	148
25aaebdb KH	149	int board_eth_init(bd_t *bis)
	150	{
	151	int ret = 0;
	152
	153	#ifdef CONFIG_USB_ETHER
	154	ret = usb_eth_initialize(bis);
	155	if (ret < 0)
	156	printf("Error %d registering USB ether.\n", ret);
	157	#endif
	158
	159	return ret;
	160	}
	161
47173483 FE	162	int board_init(void)
	163	{
	164	/* address of boot parameters */
	165	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	166
7d301a59 VM	167	#ifdef CONFIG_SYS_I2C_MXC
	168	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	169	#endif
	170
47173483 FE	171	return 0;
	172	}
	173
	174	int checkboard(void)
	175	{
d4ee5043 FE	176	char *mode;
	177
	178	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
	179	mode = "secure";
	180	else
	181	mode = "non-secure";
	182
fbbf44af BD	183	#ifdef CONFIG_OPTEE_TZDRAM_SIZE
	184	unsigned long optee_start, optee_end;
	185
	186	optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
	187	optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
	188
	189	printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
	190	mode, optee_start, optee_end);
	191	#else
d4ee5043	192	printf("Board: WARP7 in %s mode\n", mode);
fbbf44af	193	#endif
47173483 FE	194
	195	return 0;
	196	}
	197
	198	int board_usb_phy_mode(int port)
	199	{
	200	return USB_INIT_DEVICE;
	201	}
0a35cc93 MF	202
	203	int board_late_init(void)
	204	{
	205	struct wdog_regs wdog = (struct wdog_regs )WDOG1_BASE_ADDR;
852cc548 BD	206	#ifdef CONFIG_SERIAL_TAG
	207	struct tag_serialnr serialnr;
	208	char serial_string[0x20];
	209	#endif
0a35cc93 MF	210
	211	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
	212
	213	set_wdog_reset(wdog);
	214
	215	/*
	216	* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
	217	* since we use PMIC_PWRON to reset the board.
	218	*/
	219	clrsetbits_le16(&wdog->wcr, 0, 0x10);
	220
a2accd84 BD	221	#ifdef CONFIG_SECURE_BOOT
	222	/* Determine HAB state */
	223	env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
	224	#else
	225	env_set_ulong(HAB_ENABLED_ENVNAME, 0);
	226	#endif
	227
852cc548 BD	228	#ifdef CONFIG_SERIAL_TAG
	229	/* Set serial# standard environment variable based on OTP settings */
	230	get_board_serial(&serialnr);
	231	snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
	232	serialnr.low, serialnr.high);
	233	env_set("serial#", serial_string);
	234	#endif
	235
0a35cc93 MF	236	return 0;
0a35cc93 MF	237	}