projects / u-boot.git / blame
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1 | /* |
| 2 | * Copyright (C) 2002 ETC s.r.o. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * Redistribution and use in source and binary forms, with or without | |
| 6 | * modification, are permitted provided that the following conditions | |
| 7 | * are met: | |
| 8 | * 1. Redistributions of source code must retain the above copyright | |
| 9 | * notice, this list of conditions and the following disclaimer. | |
| 10 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer in the | |
| 12 | * documentation and/or other materials provided with the distribution. | |
| 13 | * 3. Neither the name of the ETC s.r.o. nor the names of its contributors | |
| 14 | * may be used to endorse or promote products derived from this software | |
| 15 | * without specific prior written permission. | |
| 16 | * | |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 18 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE | |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 23 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 24 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 27 | * | |
| 28 | * Written by Marcel Telka <marcel@telka.sk>, 2002. | |
| 29 | * | |
| 30 | * Documentation: | |
| 31 | * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, | |
| 32 | * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 | |
| 33 | * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, | |
| 34 | * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 | |
| 35 | * | |
| 36 | * This file is taken from OpenWinCE project hosted by SourceForge.net | |
| 37 | * | |
| 38 | */ | |
| 39 | ||
| 40 | #ifndef FLASH_INTEL_H | |
| 41 | #define FLASH_INTEL_H | |
| 42 | ||
| 43 | #include <common.h> | |
| 44 | ||
| 45 | /* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ | |
| 46 | ||
| 47 | #define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 48 | #define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 49 | #define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 50 | #define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 51 | #define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 52 | #define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 53 | #define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 54 | #define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 55 | #define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 56 | #define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 57 | #define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 58 | #define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 59 | #define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 60 | #define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 61 | #define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ | |
| 62 | #define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ | |
| 63 | ||
| 64 | /* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ | |
| 65 | ||
| 66 | #define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 67 | #define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 68 | #define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 69 | #define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 70 | #define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 71 | #define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 72 | #define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
| 73 | #define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ | |
| 74 | ||
| 75 | /* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ | |
| 76 | ||
| 77 | #define CFI_CHIP_INTEL_28F320J3A 0x0016 | |
| 78 | #define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" | |
| 79 | #define CFI_CHIP_INTEL_28F640J3A 0x0017 | |
| 80 | #define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" | |
| 81 | #define CFI_CHIP_INTEL_28F128J3A 0x0018 | |
| 82 | #define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" | |
| 83 | ||
| 84 | /* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ | |
| 85 | ||
| 86 | #define CFI_CHIP_INTEL_28F640K3 0x8801 | |
| 87 | #define CFI_CHIPN_INTEL_28F640K3 "28F640K3" | |
| 88 | #define CFI_CHIP_INTEL_28F128K3 0x8802 | |
| 89 | #define CFI_CHIPN_INTEL_28F128K3 "28F128K3" | |
| 90 | #define CFI_CHIP_INTEL_28F256K3 0x8803 | |
| 91 | #define CFI_CHIPN_INTEL_28F256K3 "28F256K3" | |
| 92 | #define CFI_CHIP_INTEL_28F640K18 0x8805 | |
| 93 | #define CFI_CHIPN_INTEL_28F640K18 "28F640K18" | |
| 94 | #define CFI_CHIP_INTEL_28F128K18 0x8806 | |
| 95 | #define CFI_CHIPN_INTEL_28F128K18 "28F128K18" | |
| 96 | #define CFI_CHIP_INTEL_28F256K18 0x8807 | |
| 97 | #define CFI_CHIPN_INTEL_28F256K18 "28F256K18" | |
| 98 | ||
| 99 | #endif /* FLASH_INTEL_H */ |