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Commit | Line | Data |
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ba56f625 | 1 | /* |
e0299076 | 2 | * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> |
ba56f625 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ba56f625 WD |
5 | */ |
6 | ||
ba56f625 WD |
7 | #include <common.h> |
8 | #include <asm/processor.h> | |
9 | #include <spd_sdram.h> | |
10 | #include <i2c.h> | |
d2567be9 | 11 | #include <net.h> |
ba56f625 | 12 | |
d87080b7 WD |
13 | DECLARE_GLOBAL_DATA_PTR; |
14 | ||
3c74e32a | 15 | int board_early_init_f(void) |
ba56f625 WD |
16 | { |
17 | unsigned long sdrreg; | |
e0299076 | 18 | |
b88da157 PT |
19 | /* |
20 | * Enable GPIO for pins 18 - 24 | |
21 | * 18 = SEEPROM_WP | |
22 | * 19 = #M_RST | |
23 | * 20 = #MONARCH | |
24 | * 21 = #LED_ALARM | |
25 | * 22 = #LED_ACT | |
26 | * 23 = #LED_STATUS1 | |
27 | * 24 = #LED_STATUS2 | |
28 | */ | |
d1c3b275 SR |
29 | mfsdr(SDR0_PFC0, sdrreg); |
30 | mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); | |
6d0f6bcf | 31 | out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); |
ba56f625 WD |
32 | LED0_OFF(); |
33 | LED1_OFF(); | |
34 | LED2_OFF(); | |
35 | LED3_OFF(); | |
36 | ||
e0299076 | 37 | /* Setup the external bus controller/chip selects */ |
d1c3b275 SR |
38 | mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */ |
39 | mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ | |
40 | mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */ | |
41 | mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ | |
42 | mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ | |
43 | mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ | |
44 | mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ | |
45 | mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ | |
ba56f625 | 46 | |
5de85140 | 47 | /* |
e0299076 PT |
48 | * Setup the interrupt controller polarities, triggers, etc. |
49 | * | |
5de85140 SR |
50 | * Because of the interrupt handling rework to handle 440GX interrupts |
51 | * with the common code, we needed to change names of the UIC registers. | |
52 | * Here the new relationship: | |
53 | * | |
54 | * U-Boot name 440GX name | |
55 | * ----------------------- | |
56 | * UIC0 UICB0 | |
57 | * UIC1 UIC0 | |
58 | * UIC2 UIC1 | |
59 | * UIC3 UIC2 | |
60 | */ | |
952e7760 SR |
61 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
62 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
63 | mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */ | |
64 | mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */ | |
65 | mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */ | |
66 | mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ | |
67 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
e0299076 | 68 | |
952e7760 SR |
69 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
70 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
71 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
72 | mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */ | |
73 | mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */ | |
74 | mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ | |
75 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
e0299076 | 76 | |
952e7760 SR |
77 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
78 | mtdcr(UIC3ER, 0x00000000); /* disable all */ | |
79 | mtdcr(UIC3CR, 0x00000000); /* all non-critical */ | |
80 | mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ | |
81 | mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */ | |
82 | mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ | |
83 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ | |
e0299076 | 84 | |
952e7760 SR |
85 | mtdcr(UIC0SR, 0xfc000000); /* clear all */ |
86 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
87 | mtdcr(UIC0CR, 0x00000000); /* all non-critical */ | |
88 | mtdcr(UIC0PR, 0xfc000000); /* */ | |
89 | mtdcr(UIC0TR, 0x00000000); /* */ | |
90 | mtdcr(UIC0VR, 0x00000001); /* */ | |
ba56f625 WD |
91 | |
92 | LED0_ON(); | |
93 | ||
ba56f625 WD |
94 | return 0; |
95 | } | |
96 | ||
e0299076 | 97 | int checkboard(void) |
ba56f625 | 98 | { |
f0c0b3a9 WD |
99 | char buf[64]; |
100 | int i; | |
54381b79 PT |
101 | |
102 | printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME); | |
103 | printf(" "); | |
f0c0b3a9 WD |
104 | i = getenv_f("board_rev", buf, sizeof(buf)); |
105 | if (i > 0) | |
106 | printf("Rev %s, ", buf); | |
107 | i = getenv_f("serial#", buf, sizeof(buf)); | |
108 | if (i > 0) | |
109 | printf("Serial# %s, ", buf); | |
110 | i = getenv_f("board_cfg", buf, sizeof(buf)); | |
111 | if (i > 0) | |
112 | printf("Cfg %s", buf); | |
54381b79 | 113 | printf("\n"); |
ba56f625 | 114 | |
e0299076 | 115 | return 0; |
ba56f625 WD |
116 | } |
117 | ||
e0299076 | 118 | phys_size_t initdram(int board_type) |
ba56f625 | 119 | { |
108d6d00 | 120 | return spd_sdram(); |
ba56f625 | 121 | } |
ba56f625 | 122 | |
e0299076 | 123 | /* |
a760b020 SR |
124 | * Override weak pci_pre_init() |
125 | * | |
e0299076 PT |
126 | * This routine is called just prior to registering the hose and gives |
127 | * the board the opportunity to check things. Returning a value of zero | |
128 | * indicates that things are bad & PCI initialization should be aborted. | |
ba56f625 | 129 | * |
e0299076 PT |
130 | * Different boards may wish to customize the pci controller structure |
131 | * (add regions, override default access routines, etc) or perform | |
132 | * certain pre-initialization actions. | |
133 | */ | |
466fff1a | 134 | #if defined(CONFIG_PCI) |
e0299076 | 135 | int pci_pre_init(struct pci_controller * hose) |
ba56f625 WD |
136 | { |
137 | unsigned long strap; | |
e0299076 | 138 | |
3c74e32a | 139 | /* See if we're supposed to setup the pci */ |
d1c3b275 | 140 | mfsdr(SDR0_SDSTP1, strap); |
e0299076 PT |
141 | if ((strap & 0x00010000) == 0) |
142 | return 0; | |
ba56f625 | 143 | |
6d0f6bcf | 144 | #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) |
ddc922ff | 145 | /* Setup System Device Register PCIL0_XCR */ |
d1c3b275 | 146 | mfsdr(SDR0_XCR, strap); |
3c74e32a | 147 | strap &= 0x0f000000; |
d1c3b275 | 148 | mtsdr(SDR0_XCR, strap); |
3c74e32a | 149 | #endif |
e0299076 | 150 | |
ba56f625 WD |
151 | return 1; |
152 | } | |
466fff1a | 153 | #endif /* defined(CONFIG_PCI) */ |
ba56f625 | 154 | |
e0299076 PT |
155 | #if defined(CONFIG_PCI) |
156 | /* | |
9a81c612 SR |
157 | * Override weak is_pci_host() |
158 | * | |
e0299076 PT |
159 | * This routine is called to determine if a pci scan should be |
160 | * performed. With various hardware environments (especially cPCI and | |
161 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
162 | * bit in the strap register, or generic host/adapter assumptions. | |
ba56f625 | 163 | * |
e0299076 PT |
164 | * Rather than hard-code a bad assumption in the general 440 code, the |
165 | * 440 pci code requires the board to decide at runtime. | |
ba56f625 | 166 | * |
e0299076 PT |
167 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
168 | */ | |
ba56f625 WD |
169 | int is_pci_host(struct pci_controller *hose) |
170 | { | |
6d0f6bcf | 171 | return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); |
ba56f625 WD |
172 | } |
173 | #endif /* defined(CONFIG_PCI) */ | |
174 | ||
175 | #ifdef CONFIG_POST | |
176 | /* | |
177 | * Returns 1 if keys pressed to start the power-on long-running tests | |
178 | * Called from board_init_f(). | |
179 | */ | |
180 | int post_hotkeys_pressed(void) | |
181 | { | |
e0299076 | 182 | return ctrlc(); |
ba56f625 | 183 | } |
e0299076 | 184 | #endif |