projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5da048ad MS |
1 | /* |
| 2 | * (C) Copyright 2007 Michal Simek | |
| 3 | * | |
| 4 | * Michal SIMEK <monstr@monstr.eu> | |
| 5 | * | |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 5da048ad | 7 | * |
| 20637888 SL |
8 | * CAUTION: This file is a faked configuration !!! |
| 9 | * There is no real target for the microblaze-generic | |
| 10 | * configuration. You have to replace this file with | |
| 11 | * the generated file from your Xilinx design flow. | |
| 5da048ad | 12 | */ |
| 17980495 | 13 | |
| 330e5545 MS |
14 | #define XILINX_BOARD_NAME microblaze-generic |
| 15 | ||
| 17980495 | 16 | /* System Clock Frequency */ |
| 9d1d6a34 | 17 | #define XILINX_CLOCK_FREQ 100000000 |
| 17980495 | 18 | |
| ffc50f9b | 19 | /* Microblaze is microblaze_0 */ |
| fb05f6da | 20 | #define XILINX_USE_MSR_INSTR 1 |
| 48fbd3a4 | 21 | #define XILINX_FSL_NUMBER 3 |
| ffc50f9b | 22 | |
| 48fbd3a4 | 23 | /* Interrupt controller is opb_intc_0 */ |
| 9d1d6a34 | 24 | #define XILINX_INTC_BASEADDR 0x41200000 |
| fb05f6da | 25 | #define XILINX_INTC_NUM_INTR_INPUTS 6 |
| 17980495 | 26 | |
| 48fbd3a4 | 27 | /* Timer pheriphery is opb_timer_1 */ |
| 9d1d6a34 | 28 | #define XILINX_TIMER_BASEADDR 0x41c00000 |
| 17980495 MS |
29 | #define XILINX_TIMER_IRQ 0 |
| 30 | ||
| 48fbd3a4 | 31 | /* Uart pheriphery is RS232_Uart */ |
| af7ae1a4 MS |
32 | #define XILINX_UARTLITE_BASEADDR 0x40600000 |
| 33 | #define XILINX_UARTLITE_BAUDRATE 115200 | |
| 17980495 | 34 | |
| 48fbd3a4 MS |
35 | /* IIC pheriphery is IIC_EEPROM */ |
| 36 | #define XILINX_IIC_0_BASEADDR 0x40800000 | |
| 37 | #define XILINX_IIC_0_FREQ 100000 | |
| 38 | #define XILINX_IIC_0_BIT 0 | |
| 39 | ||
| 40 | /* GPIO is LEDs_4Bit*/ | |
| 41 | #define XILINX_GPIO_BASEADDR 0x40000000 | |
| 17980495 | 42 | |
| 48fbd3a4 | 43 | /* Flash Memory is FLASH_2Mx32 */ |
| 9d1d6a34 | 44 | #define XILINX_FLASH_START 0x2c000000 |
| 17980495 MS |
45 | #define XILINX_FLASH_SIZE 0x00800000 |
| 46 | ||
| 48fbd3a4 | 47 | /* Main Memory is DDR_SDRAM_64Mx32 */ |
| 9d1d6a34 MS |
48 | #define XILINX_RAM_START 0x28000000 |
| 49 | #define XILINX_RAM_SIZE 0x04000000 | |
| 17980495 | 50 | |
| 48fbd3a4 | 51 | /* Sysace Controller is SysACE_CompactFlash */ |
| 9d1d6a34 | 52 | #define XILINX_SYSACE_BASEADDR 0x41800000 |
| 48fbd3a4 | 53 | #define XILINX_SYSACE_HIGHADDR 0x4180ffff |
| 17980495 MS |
54 | #define XILINX_SYSACE_MEM_WIDTH 16 |
| 55 | ||
| 48fbd3a4 | 56 | /* Ethernet controller is Ethernet_MAC */ |
| 6bf3e982 | 57 | #define XILINX_EMACLITE_BASEADDR 0x40C00000 |
| 20637888 SL |
58 | |
| 59 | /* LL_TEMAC Ethernet controller */ | |
| 60 | #define XILINX_LLTEMAC_BASEADDR 0x44000000 | |
| 61 | #define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 | |
| 62 | #define XILINX_LLTEMAC_BASEADDR1 0x44200000 | |
| 63 | #define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 | |
| 0f21f98d MS |
64 | |
| 65 | /* Watchdog IP is wxi_timebase_wdt_0 */ | |
| 66 | #define XILINX_WATCHDOG_BASEADDR 0x50000000 | |
| 67 | #define XILINX_WATCHDOG_IRQ 1 |