[thirdparty/u-boot.git] / board / xilinx / versal / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2018 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <common.h>
#include <cpu_func.h>
#include <fdtdec.h>
#include <init.h>
#include <malloc.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include "../common/board.h"

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = XILINX_VERSAL_DESC;
#endif

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA_VERSALPL)
	fpga_init();
	fpga_add(fpga_xilinx, &versalpl);
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	debug("iou_switch ctrl div0 %x\n",
	      readl(&crlapb_base->iou_switch_ctrl));

	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
	       &crlapb_base->iou_switch_ctrl);

	/* Global timer init - Program time stamp reference clk */
	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	writel(val, &crlapb_base->timestamp_ref_ctrl);

	debug("ref ctrl 0x%x\n",
	      readl(&crlapb_base->timestamp_ref_ctrl));

	/* Clear reset of timestamp reg */
	writel(0, &crlapb_base->rst_timestamp);

	/*
	 * Program freq register in System counter and
	 * enable system counter.
	 */
	writel(COUNTER_FREQUENCY,
	       &iou_scntr_secure->base_frequency_id_register);

	debug("counter val 0x%x\n",
	      readl(&iou_scntr_secure->base_frequency_id_register));

	writel(IOU_SCNTRS_CONTROL_EN,
	       &iou_scntr_secure->counter_control_register);

	debug("scntrs control 0x%x\n",
	      readl(&iou_scntr_secure->counter_control_register));
	debug("timer 0x%llx\n", get_ticks());
	debug("timer 0x%llx\n", get_ticks());

	return 0;
}

static u8 versal_get_bootmode(void)
{
	u8 bootmode;
	u32 reg = 0;

	reg = readl(&crp_base->boot_mode_usr);

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	return bootmode;
}

int board_late_init(void)
{
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode;
	char *new_targets;
	char *env_targets;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	bootmode = versal_get_bootmode();

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "dfu_usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "jtag pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
		puts("QSPI_MODE_24\n");
		mode = "xspi0";
		break;
	case QSPI_MODE_32BIT:
		puts("QSPI_MODE_32\n");
		mode = "xspi0";
		break;
	case OSPI_MODE:
		puts("OSPI_MODE\n");
		mode = "xspi0";
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from EMMC but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
		mode = "mmc";
		bootseq = dev->seq;
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1040000", &dev)) {
			puts("Boot from SD0 but without SD0 enabled!\n");
			return -1;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from SD1 but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (bootseq >= 0) {
		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
		debug("Bootseq len: %x\n", bootseq_len);
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets)
		env_targets_len = strlen(env_targets);

	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
			     bootseq_len);
	if (!new_targets)
		return -ENOMEM;

	if (bootseq >= 0)
		sprintf(new_targets, "%s%x %s", mode, bootseq,
			env_targets ? env_targets : "");
	else
		sprintf(new_targets, "%s %s", mode,
			env_targets ? env_targets : "");

	env_set("boot_targets", new_targets);

	return board_late_init_xilinx();
}

int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

void reset_cpu(ulong addr)
{
}
Commit	Line	Data
ec48b6c9 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 - 2018 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
	5	*/
	6
	7	#include <common.h>
9a3b4ceb	8	#include <cpu_func.h>
ec48b6c9	9	#include <fdtdec.h>
5255932f	10	#include <init.h>
ec48b6c9	11	#include <malloc.h>
1045315d	12	#include <time.h>
90526e9f	13	#include <asm/cache.h>
ec48b6c9 MS	14	#include <asm/io.h>
ec48b6c9 MS	15	#include <asm/arch/hardware.h>
aef149e9	16	#include <asm/arch/sys_proto.h>
bfd092f9 SDPP	17	#include <dm/device.h>
bfd092f9 SDPP	18	#include <dm/uclass.h>
26e054c9	19	#include <versalpl.h>
80fdef12	20	#include "../common/board.h"
ec48b6c9 MS	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
26e054c9 SDPP	24	#if defined(CONFIG_FPGA_VERSALPL)
	25	static xilinx_desc versalpl = XILINX_VERSAL_DESC;
	26	#endif
	27
ec48b6c9 MS	28	int board_init(void)
	29	{
	30	printf("EL Level:\tEL%d\n", current_el());
	31
26e054c9 SDPP	32	#if defined(CONFIG_FPGA_VERSALPL)
	33	fpga_init();
	34	fpga_add(fpga_xilinx, &versalpl);
	35	#endif
	36
ec48b6c9 MS	37	return 0;
	38	}
	39
	40	int board_early_init_r(void)
	41	{
fb771793 MS	42	u32 val;
	43
	44	if (current_el() != 3)
	45	return 0;
	46
47a766f9 MS	47	debug("iou_switch ctrl div0 %x\n",
	48	readl(&crlapb_base->iou_switch_ctrl));
	49
fb771793	50	writel(IOU_SWITCH_CTRL_CLKACT_BIT \|
47a766f9	51	(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
fb771793 MS	52	&crlapb_base->iou_switch_ctrl);
	53
	54	/* Global timer init - Program time stamp reference clk */
	55	val = readl(&crlapb_base->timestamp_ref_ctrl);
	56	val \|= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	57	writel(val, &crlapb_base->timestamp_ref_ctrl);
	58
	59	debug("ref ctrl 0x%x\n",
	60	readl(&crlapb_base->timestamp_ref_ctrl));
	61
	62	/* Clear reset of timestamp reg */
	63	writel(0, &crlapb_base->rst_timestamp);
	64
	65	/*
	66	* Program freq register in System counter and
	67	* enable system counter.
	68	*/
	69	writel(COUNTER_FREQUENCY,
	70	&iou_scntr_secure->base_frequency_id_register);
	71
	72	debug("counter val 0x%x\n",
	73	readl(&iou_scntr_secure->base_frequency_id_register));
	74
	75	writel(IOU_SCNTRS_CONTROL_EN,
	76	&iou_scntr_secure->counter_control_register);
	77
	78	debug("scntrs control 0x%x\n",
	79	readl(&iou_scntr_secure->counter_control_register));
	80	debug("timer 0x%llx\n", get_ticks());
	81	debug("timer 0x%llx\n", get_ticks());
ec48b6c9 MS	82
	83	return 0;
	84	}
	85
51f6c52e	86	static u8 versal_get_bootmode(void)
bfd092f9	87	{
51f6c52e	88	u8 bootmode;
bfd092f9	89	u32 reg = 0;
51f6c52e MS	90
	91	reg = readl(&crp_base->boot_mode_usr);
	92
	93	if (reg >> BOOT_MODE_ALT_SHIFT)
	94	reg >>= BOOT_MODE_ALT_SHIFT;
	95
	96	bootmode = reg & BOOT_MODES_MASK;
	97
	98	return bootmode;
	99	}
	100
	101	int board_late_init(void)
	102	{
bfd092f9 SDPP	103	u8 bootmode;
	104	struct udevice *dev;
	105	int bootseq = -1;
	106	int bootseq_len = 0;
	107	int env_targets_len = 0;
	108	const char *mode;
	109	char *new_targets;
	110	char *env_targets;
	111
	112	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	113	debug("Saved variables - Skipping\n");
	114	return 0;
	115	}
	116
51f6c52e	117	bootmode = versal_get_bootmode();
bfd092f9 SDPP	118
	119	puts("Bootmode: ");
	120	switch (bootmode) {
f0c16cd6 KR	121	case USB_MODE:
	122	puts("USB_MODE\n");
	123	mode = "dfu_usb";
	124	break;
bfd092f9 SDPP	125	case JTAG_MODE:
bfd092f9 SDPP	126	puts("JTAG_MODE\n");
3d865acb	127	mode = "jtag pxe dhcp";
bfd092f9 SDPP	128	break;
	129	case QSPI_MODE_24BIT:
	130	puts("QSPI_MODE_24\n");
	131	mode = "xspi0";
	132	break;
	133	case QSPI_MODE_32BIT:
	134	puts("QSPI_MODE_32\n");
	135	mode = "xspi0";
	136	break;
	137	case OSPI_MODE:
	138	puts("OSPI_MODE\n");
	139	mode = "xspi0";
	140	break;
	141	case EMMC_MODE:
	142	puts("EMMC_MODE\n");
7c5b7bb1 KR	143	if (uclass_get_device_by_name(UCLASS_MMC,
	144	"sdhci@f1050000", &dev)) {
	145	puts("Boot from EMMC but without SD1 enabled!\n");
	146	return -1;
	147	}
	148	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	149	mode = "mmc";
	150	bootseq = dev->seq;
bfd092f9 SDPP	151	break;
	152	case SD_MODE:
	153	puts("SD_MODE\n");
	154	if (uclass_get_device_by_name(UCLASS_MMC,
	155	"sdhci@f1040000", &dev)) {
	156	puts("Boot from SD0 but without SD0 enabled!\n");
	157	return -1;
	158	}
	159	debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
	160
	161	mode = "mmc";
	162	bootseq = dev->seq;
	163	break;
	164	case SD1_LSHFT_MODE:
	165	puts("LVL_SHFT_");
	166	/* fall through */
	167	case SD_MODE1:
	168	puts("SD_MODE1\n");
	169	if (uclass_get_device_by_name(UCLASS_MMC,
	170	"sdhci@f1050000", &dev)) {
	171	puts("Boot from SD1 but without SD1 enabled!\n");
	172	return -1;
	173	}
	174	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	175
	176	mode = "mmc";
	177	bootseq = dev->seq;
	178	break;
	179	default:
	180	mode = "";
	181	printf("Invalid Boot Mode:0x%x\n", bootmode);
	182	break;
	183	}
	184
	185	if (bootseq >= 0) {
	186	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	187	debug("Bootseq len: %x\n", bootseq_len);
	188	}
	189
	190	/*
	191	* One terminating char + one byte for space between mode
	192	* and default boot_targets
	193	*/
	194	env_targets = env_get("boot_targets");
	195	if (env_targets)
	196	env_targets_len = strlen(env_targets);
	197
	198	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
	199	bootseq_len);
	200	if (!new_targets)
	201	return -ENOMEM;
	202
	203	if (bootseq >= 0)
	204	sprintf(new_targets, "%s%x %s", mode, bootseq,
	205	env_targets ? env_targets : "");
	206	else
	207	sprintf(new_targets, "%s %s", mode,
	208	env_targets ? env_targets : "");
	209
	210	env_set("boot_targets", new_targets);
	211
80fdef12	212	return board_late_init_xilinx();
bfd092f9 SDPP	213	}
bfd092f9 SDPP	214
ec48b6c9 MS	215	int dram_init_banksize(void)
ec48b6c9 MS	216	{
aef149e9 MS	217	int ret;
	218
	219	ret = fdtdec_setup_memory_banksize();
	220	if (ret)
	221	return ret;
	222
	223	mem_map_fill();
ec48b6c9 MS	224
	225	return 0;
	226	}
	227
	228	int dram_init(void)
	229	{
	230	if (fdtdec_setup_mem_size_base() != 0)
	231	return -EINVAL;
	232
	233	return 0;
	234	}
	235
	236	void reset_cpu(ulong addr)
	237	{
	238	}