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Commit | Line | Data |
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f22651cf MS |
1 | /* |
2 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> | |
3 | * | |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
f22651cf MS |
5 | */ |
6 | ||
7 | #include <common.h> | |
9e0e37ac | 8 | #include <fdtdec.h> |
5b73caff MS |
9 | #include <fpga.h> |
10 | #include <mmc.h> | |
d5dae85f | 11 | #include <zynqpl.h> |
7193653e MS |
12 | #include <asm/arch/hardware.h> |
13 | #include <asm/arch/sys_proto.h> | |
f22651cf MS |
14 | |
15 | DECLARE_GLOBAL_DATA_PTR; | |
16 | ||
0b680206 MS |
17 | #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ |
18 | (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
5b73caff | 19 | static xilinx_desc fpga; |
d5dae85f MS |
20 | |
21 | /* It can be done differently */ | |
05c59d0b | 22 | static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); |
5b73caff | 23 | static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); |
05c59d0b MS |
24 | static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); |
25 | static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); | |
5b73caff MS |
26 | static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); |
27 | static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); | |
28 | static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); | |
b9103809 | 29 | static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); |
5b73caff MS |
30 | static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); |
31 | static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); | |
d5dae85f MS |
32 | #endif |
33 | ||
f22651cf MS |
34 | int board_init(void) |
35 | { | |
0b680206 MS |
36 | #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ |
37 | (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
d5dae85f MS |
38 | u32 idcode; |
39 | ||
40 | idcode = zynq_slcr_get_idcode(); | |
41 | ||
42 | switch (idcode) { | |
05c59d0b MS |
43 | case XILINX_ZYNQ_7007S: |
44 | fpga = fpga007s; | |
45 | break; | |
d5dae85f MS |
46 | case XILINX_ZYNQ_7010: |
47 | fpga = fpga010; | |
48 | break; | |
05c59d0b MS |
49 | case XILINX_ZYNQ_7012S: |
50 | fpga = fpga012s; | |
51 | break; | |
52 | case XILINX_ZYNQ_7014S: | |
53 | fpga = fpga014s; | |
54 | break; | |
31993d6a MS |
55 | case XILINX_ZYNQ_7015: |
56 | fpga = fpga015; | |
57 | break; | |
d5dae85f MS |
58 | case XILINX_ZYNQ_7020: |
59 | fpga = fpga020; | |
60 | break; | |
61 | case XILINX_ZYNQ_7030: | |
62 | fpga = fpga030; | |
63 | break; | |
b9103809 SDPP |
64 | case XILINX_ZYNQ_7035: |
65 | fpga = fpga035; | |
66 | break; | |
d5dae85f MS |
67 | case XILINX_ZYNQ_7045: |
68 | fpga = fpga045; | |
69 | break; | |
fd2b10b6 MS |
70 | case XILINX_ZYNQ_7100: |
71 | fpga = fpga100; | |
72 | break; | |
d5dae85f MS |
73 | } |
74 | #endif | |
75 | ||
0b680206 MS |
76 | #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ |
77 | (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
d5dae85f MS |
78 | fpga_init(); |
79 | fpga_add(fpga_xilinx, &fpga); | |
80 | #endif | |
81 | ||
f22651cf MS |
82 | return 0; |
83 | } | |
84 | ||
b3de9249 JT |
85 | int board_late_init(void) |
86 | { | |
87 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { | |
085b2b82 | 88 | case ZYNQ_BM_QSPI: |
382bee57 | 89 | env_set("modeboot", "qspiboot"); |
085b2b82 MS |
90 | break; |
91 | case ZYNQ_BM_NAND: | |
382bee57 | 92 | env_set("modeboot", "nandboot"); |
085b2b82 | 93 | break; |
b3de9249 | 94 | case ZYNQ_BM_NOR: |
382bee57 | 95 | env_set("modeboot", "norboot"); |
b3de9249 JT |
96 | break; |
97 | case ZYNQ_BM_SD: | |
382bee57 | 98 | env_set("modeboot", "sdboot"); |
b3de9249 JT |
99 | break; |
100 | case ZYNQ_BM_JTAG: | |
382bee57 | 101 | env_set("modeboot", "jtagboot"); |
b3de9249 JT |
102 | break; |
103 | default: | |
382bee57 | 104 | env_set("modeboot", ""); |
b3de9249 JT |
105 | break; |
106 | } | |
107 | ||
108 | return 0; | |
109 | } | |
f22651cf | 110 | |
5a82d53c MS |
111 | #ifdef CONFIG_DISPLAY_BOARDINFO |
112 | int checkboard(void) | |
113 | { | |
5af08556 | 114 | puts("Board: Xilinx Zynq\n"); |
5a82d53c MS |
115 | return 0; |
116 | } | |
117 | #endif | |
118 | ||
a509a1d4 JH |
119 | int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
120 | { | |
121 | #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ | |
122 | defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) | |
123 | if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, | |
124 | CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, | |
125 | ethaddr, 6)) | |
126 | printf("I2C EEPROM MAC address read failed\n"); | |
127 | #endif | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
758f29d0 | 132 | #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) |
76b00aca | 133 | int dram_init_banksize(void) |
361a8799 | 134 | { |
de9bf1b5 | 135 | fdtdec_setup_memory_banksize(); |
76b00aca SG |
136 | |
137 | return 0; | |
361a8799 | 138 | } |
8a5db0ab | 139 | |
361a8799 TR |
140 | int dram_init(void) |
141 | { | |
de9bf1b5 NR |
142 | if (fdtdec_setup_memory_size() != 0) |
143 | return -EINVAL; | |
64b67fb2 | 144 | |
361a8799 | 145 | zynq_ddrc_init(); |
64b67fb2 | 146 | |
361a8799 | 147 | return 0; |
758f29d0 | 148 | } |
758f29d0 MS |
149 | #else |
150 | int dram_init(void) | |
151 | { | |
152 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; | |
153 | ||
148ba55c MS |
154 | zynq_ddrc_init(); |
155 | ||
f22651cf MS |
156 | return 0; |
157 | } | |
758f29d0 | 158 | #endif |