[people/ms/u-boot.git] / board / xilinx / zynq / board.c

/*
 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_FPGA
static xilinx_desc fpga;

/* It can be done differently */
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif

int board_init(void)
{
#ifdef CONFIG_FPGA
	u32 idcode;

	idcode = zynq_slcr_get_idcode();

	switch (idcode) {
	case XILINX_ZYNQ_7010:
		fpga = fpga010;
		break;
	case XILINX_ZYNQ_7015:
		fpga = fpga015;
		break;
	case XILINX_ZYNQ_7020:
		fpga = fpga020;
		break;
	case XILINX_ZYNQ_7030:
		fpga = fpga030;
		break;
	case XILINX_ZYNQ_7045:
		fpga = fpga045;
		break;
	case XILINX_ZYNQ_7100:
		fpga = fpga100;
		break;
	}
#endif

#ifdef CONFIG_FPGA
	fpga_init();
	fpga_add(fpga_xilinx, &fpga);
#endif

	return 0;
}

int board_late_init(void)
{
	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
	case ZYNQ_BM_NOR:
		setenv("modeboot", "norboot");
		break;
	case ZYNQ_BM_SD:
		setenv("modeboot", "sdboot");
		break;
	case ZYNQ_BM_JTAG:
		setenv("modeboot", "jtagboot");
		break;
	default:
		setenv("modeboot", "");
		break;
	}

	return 0;
}

int board_eth_init(bd_t *bis)
{
	u32 ret = 0;

#ifdef CONFIG_XILINX_AXIEMAC
	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
						XILINX_AXIDMA_BASEADDR);
#endif
#ifdef CONFIG_XILINX_EMACLITE
	u32 txpp = 0;
	u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
	txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
	rxpp = 1;
# endif
	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
			txpp, rxpp);
#endif

#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
						CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
						CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif
#endif
	return ret;
}

#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
	int ret = 0;

#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
	ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
	return ret;
}
#endif

int dram_init(void)
{
#ifdef CONFIG_OF_CONTROL
	int node;
	fdt_addr_t addr;
	fdt_size_t size;
	const void *blob = gd->fdt_blob;

	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
					     "memory", 7);
	if (node == -FDT_ERR_NOTFOUND) {
		debug("ZYNQ DRAM: Can't get memory node\n");
		return -1;
	}
	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
	if (addr == FDT_ADDR_T_NONE || size == 0) {
		debug("ZYNQ DRAM: Can't get base address or size\n");
		return -1;
	}
	gd->ram_size = size;
#else
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#endif
	zynq_ddrc_init();

	return 0;
}
Commit	Line	Data
f22651cf MS	1	/*
	2	* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
f22651cf MS	5	*/
	6
	7	#include <common.h>
9e0e37ac	8	#include <fdtdec.h>
5b73caff MS	9	#include <fpga.h>
5b73caff MS	10	#include <mmc.h>
f22651cf	11	#include <netdev.h>
d5dae85f	12	#include <zynqpl.h>
7193653e MS	13	#include <asm/arch/hardware.h>
7193653e MS	14	#include <asm/arch/sys_proto.h>
f22651cf MS	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
d5dae85f	18	#ifdef CONFIG_FPGA
5b73caff	19	static xilinx_desc fpga;
d5dae85f MS	20
d5dae85f MS	21	/* It can be done differently */
5b73caff MS	22	static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
	23	static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
	24	static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
	25	static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
	26	static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
	27	static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
d5dae85f MS	28	#endif
d5dae85f MS	29
f22651cf MS	30	int board_init(void)
f22651cf MS	31	{
d5dae85f MS	32	#ifdef CONFIG_FPGA
	33	u32 idcode;
	34
	35	idcode = zynq_slcr_get_idcode();
	36
	37	switch (idcode) {
	38	case XILINX_ZYNQ_7010:
	39	fpga = fpga010;
	40	break;
31993d6a MS	41	case XILINX_ZYNQ_7015:
	42	fpga = fpga015;
	43	break;
d5dae85f MS	44	case XILINX_ZYNQ_7020:
	45	fpga = fpga020;
	46	break;
	47	case XILINX_ZYNQ_7030:
	48	fpga = fpga030;
	49	break;
	50	case XILINX_ZYNQ_7045:
	51	fpga = fpga045;
	52	break;
fd2b10b6 MS	53	case XILINX_ZYNQ_7100:
	54	fpga = fpga100;
	55	break;
d5dae85f MS	56	}
	57	#endif
	58
d5dae85f MS	59	#ifdef CONFIG_FPGA
	60	fpga_init();
	61	fpga_add(fpga_xilinx, &fpga);
	62	#endif
	63
f22651cf MS	64	return 0;
	65	}
	66
b3de9249 JT	67	int board_late_init(void)
	68	{
	69	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
	70	case ZYNQ_BM_NOR:
	71	setenv("modeboot", "norboot");
	72	break;
	73	case ZYNQ_BM_SD:
	74	setenv("modeboot", "sdboot");
	75	break;
	76	case ZYNQ_BM_JTAG:
	77	setenv("modeboot", "jtagboot");
	78	break;
	79	default:
	80	setenv("modeboot", "");
	81	break;
	82	}
	83
	84	return 0;
	85	}
f22651cf	86
f22651cf MS	87	int board_eth_init(bd_t *bis)
	88	{
	89	u32 ret = 0;
	90
2d83d33a MS	91	#ifdef CONFIG_XILINX_AXIEMAC
	92	ret \|= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
	93	XILINX_AXIDMA_BASEADDR);
	94	#endif
	95	#ifdef CONFIG_XILINX_EMACLITE
	96	u32 txpp = 0;
	97	u32 rxpp = 0;
	98	# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
	99	txpp = 1;
	100	# endif
	101	# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
	102	rxpp = 1;
	103	# endif
	104	ret \|= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
	105	txpp, rxpp);
	106	#endif
	107
7193653e MS	108	#if defined(CONFIG_ZYNQ_GEM)
7193653e MS	109	# if defined(CONFIG_ZYNQ_GEM0)
117cd4cc	110	ret \|= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
01fbf310	111	CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
7193653e MS	112	# endif
7193653e MS	113	# if defined(CONFIG_ZYNQ_GEM1)
117cd4cc	114	ret \|= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
01fbf310	115	CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
7193653e	116	# endif
f22651cf	117	#endif
f22651cf MS	118	return ret;
f22651cf MS	119	}
f22651cf	120
293eb33f MS	121	#ifdef CONFIG_CMD_MMC
	122	int board_mmc_init(bd_t *bd)
	123	{
	124	int ret = 0;
	125
	126	#if defined(CONFIG_ZYNQ_SDHCI)
	127	# if defined(CONFIG_ZYNQ_SDHCI0)
	128	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
	129	# endif
	130	# if defined(CONFIG_ZYNQ_SDHCI1)
	131	ret \|= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
	132	# endif
	133	#endif
	134	return ret;
	135	}
	136	#endif
	137
f22651cf MS	138	int dram_init(void)
f22651cf MS	139	{
9e0e37ac MS	140	#ifdef CONFIG_OF_CONTROL
	141	int node;
	142	fdt_addr_t addr;
	143	fdt_size_t size;
	144	const void *blob = gd->fdt_blob;
	145
	146	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
	147	"memory", 7);
	148	if (node == -FDT_ERR_NOTFOUND) {
	149	debug("ZYNQ DRAM: Can't get memory node\n");
	150	return -1;
	151	}
	152	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
	153	if (addr == FDT_ADDR_T_NONE \|\| size == 0) {
	154	debug("ZYNQ DRAM: Can't get base address or size\n");
	155	return -1;
	156	}
	157	gd->ram_size = size;
	158	#else
f22651cf	159	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
9e0e37ac	160	#endif
148ba55c MS	161	zynq_ddrc_init();
148ba55c MS	162
f22651cf MS	163	return 0;
f22651cf MS	164	}