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1 | /****************************************************************************** |
2 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. | |
3 | * | |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0+ |
95b237ec MY |
5 | * |
6 | * | |
7 | ******************************************************************************/ | |
8 | /****************************************************************************/ | |
9 | /** | |
10 | * | |
11 | * @file ps7_init_gpl.c | |
12 | * | |
13 | * This file is automatically generated | |
14 | * | |
15 | *****************************************************************************/ | |
16 | ||
460b05d9 | 17 | #include <asm/arch/ps7_init_gpl.h> |
95b237ec MY |
18 | |
19 | unsigned long ps7_pll_init_data_3_0[] = { | |
20 | // START: top | |
21 | // .. START: SLCR SETTINGS | |
22 | // .. UNLOCK_KEY = 0XDF0D | |
23 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
24 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
25 | // .. | |
26 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
27 | // .. FINISH: SLCR SETTINGS | |
28 | // .. START: PLL SLCR REGISTERS | |
29 | // .. .. START: ARM PLL INIT | |
30 | // .. .. PLL_RES = 0x2 | |
31 | // .. .. ==> 0XF8000110[7:4] = 0x00000002U | |
32 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
33 | // .. .. PLL_CP = 0x2 | |
34 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | |
35 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
36 | // .. .. LOCK_CNT = 0xfa | |
37 | // .. .. ==> 0XF8000110[21:12] = 0x000000FAU | |
38 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | |
39 | // .. .. | |
40 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), | |
41 | // .. .. .. START: UPDATE FB_DIV | |
42 | // .. .. .. PLL_FDIV = 0x28 | |
43 | // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U | |
44 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U | |
45 | // .. .. .. | |
46 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), | |
47 | // .. .. .. FINISH: UPDATE FB_DIV | |
48 | // .. .. .. START: BY PASS PLL | |
49 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
50 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | |
51 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
52 | // .. .. .. | |
53 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | |
54 | // .. .. .. FINISH: BY PASS PLL | |
55 | // .. .. .. START: ASSERT RESET | |
56 | // .. .. .. PLL_RESET = 1 | |
57 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | |
58 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
59 | // .. .. .. | |
60 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | |
61 | // .. .. .. FINISH: ASSERT RESET | |
62 | // .. .. .. START: DEASSERT RESET | |
63 | // .. .. .. PLL_RESET = 0 | |
64 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | |
65 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
66 | // .. .. .. | |
67 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | |
68 | // .. .. .. FINISH: DEASSERT RESET | |
69 | // .. .. .. START: CHECK PLL STATUS | |
70 | // .. .. .. ARM_PLL_LOCK = 1 | |
71 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | |
72 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
73 | // .. .. .. | |
74 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | |
75 | // .. .. .. FINISH: CHECK PLL STATUS | |
76 | // .. .. .. START: REMOVE PLL BY PASS | |
77 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
78 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | |
79 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
80 | // .. .. .. | |
81 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | |
82 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
83 | // .. .. .. SRCSEL = 0x0 | |
84 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | |
85 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
86 | // .. .. .. DIVISOR = 0x2 | |
87 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U | |
88 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U | |
89 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | |
90 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | |
91 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | |
92 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | |
93 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | |
94 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | |
95 | // .. .. .. CPU_2XCLKACT = 0x1 | |
96 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | |
97 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | |
98 | // .. .. .. CPU_1XCLKACT = 0x1 | |
99 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | |
100 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | |
101 | // .. .. .. CPU_PERI_CLKACT = 0x1 | |
102 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | |
103 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
104 | // .. .. .. | |
105 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), | |
106 | // .. .. FINISH: ARM PLL INIT | |
107 | // .. .. START: DDR PLL INIT | |
108 | // .. .. PLL_RES = 0x2 | |
109 | // .. .. ==> 0XF8000114[7:4] = 0x00000002U | |
110 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
111 | // .. .. PLL_CP = 0x2 | |
112 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | |
113 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
114 | // .. .. LOCK_CNT = 0x12c | |
115 | // .. .. ==> 0XF8000114[21:12] = 0x0000012CU | |
116 | // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U | |
117 | // .. .. | |
118 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), | |
119 | // .. .. .. START: UPDATE FB_DIV | |
120 | // .. .. .. PLL_FDIV = 0x20 | |
121 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U | |
122 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U | |
123 | // .. .. .. | |
124 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), | |
125 | // .. .. .. FINISH: UPDATE FB_DIV | |
126 | // .. .. .. START: BY PASS PLL | |
127 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
128 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | |
129 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
130 | // .. .. .. | |
131 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | |
132 | // .. .. .. FINISH: BY PASS PLL | |
133 | // .. .. .. START: ASSERT RESET | |
134 | // .. .. .. PLL_RESET = 1 | |
135 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | |
136 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
137 | // .. .. .. | |
138 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | |
139 | // .. .. .. FINISH: ASSERT RESET | |
140 | // .. .. .. START: DEASSERT RESET | |
141 | // .. .. .. PLL_RESET = 0 | |
142 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | |
143 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
144 | // .. .. .. | |
145 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | |
146 | // .. .. .. FINISH: DEASSERT RESET | |
147 | // .. .. .. START: CHECK PLL STATUS | |
148 | // .. .. .. DDR_PLL_LOCK = 1 | |
149 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | |
150 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
151 | // .. .. .. | |
152 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | |
153 | // .. .. .. FINISH: CHECK PLL STATUS | |
154 | // .. .. .. START: REMOVE PLL BY PASS | |
155 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
156 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | |
157 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
158 | // .. .. .. | |
159 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | |
160 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
161 | // .. .. .. DDR_3XCLKACT = 0x1 | |
162 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | |
163 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
164 | // .. .. .. DDR_2XCLKACT = 0x1 | |
165 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | |
166 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
167 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | |
168 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | |
169 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | |
170 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | |
171 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | |
172 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | |
173 | // .. .. .. | |
174 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | |
175 | // .. .. FINISH: DDR PLL INIT | |
176 | // .. .. START: IO PLL INIT | |
177 | // .. .. PLL_RES = 0xc | |
178 | // .. .. ==> 0XF8000118[7:4] = 0x0000000CU | |
179 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | |
180 | // .. .. PLL_CP = 0x2 | |
181 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | |
182 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
183 | // .. .. LOCK_CNT = 0x145 | |
184 | // .. .. ==> 0XF8000118[21:12] = 0x00000145U | |
185 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U | |
186 | // .. .. | |
187 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), | |
188 | // .. .. .. START: UPDATE FB_DIV | |
189 | // .. .. .. PLL_FDIV = 0x1e | |
190 | // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU | |
191 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U | |
192 | // .. .. .. | |
193 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), | |
194 | // .. .. .. FINISH: UPDATE FB_DIV | |
195 | // .. .. .. START: BY PASS PLL | |
196 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
197 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | |
198 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
199 | // .. .. .. | |
200 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | |
201 | // .. .. .. FINISH: BY PASS PLL | |
202 | // .. .. .. START: ASSERT RESET | |
203 | // .. .. .. PLL_RESET = 1 | |
204 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | |
205 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
206 | // .. .. .. | |
207 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | |
208 | // .. .. .. FINISH: ASSERT RESET | |
209 | // .. .. .. START: DEASSERT RESET | |
210 | // .. .. .. PLL_RESET = 0 | |
211 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | |
212 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
213 | // .. .. .. | |
214 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | |
215 | // .. .. .. FINISH: DEASSERT RESET | |
216 | // .. .. .. START: CHECK PLL STATUS | |
217 | // .. .. .. IO_PLL_LOCK = 1 | |
218 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | |
219 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
220 | // .. .. .. | |
221 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | |
222 | // .. .. .. FINISH: CHECK PLL STATUS | |
223 | // .. .. .. START: REMOVE PLL BY PASS | |
224 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
225 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | |
226 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
227 | // .. .. .. | |
228 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | |
229 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
230 | // .. .. FINISH: IO PLL INIT | |
231 | // .. FINISH: PLL SLCR REGISTERS | |
232 | // .. START: LOCK IT BACK | |
233 | // .. LOCK_KEY = 0X767B | |
234 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
235 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
236 | // .. | |
237 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
238 | // .. FINISH: LOCK IT BACK | |
239 | // FINISH: top | |
240 | // | |
241 | EMIT_EXIT(), | |
242 | ||
243 | // | |
244 | }; | |
245 | ||
246 | unsigned long ps7_clock_init_data_3_0[] = { | |
247 | // START: top | |
248 | // .. START: SLCR SETTINGS | |
249 | // .. UNLOCK_KEY = 0XDF0D | |
250 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
251 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
252 | // .. | |
253 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
254 | // .. FINISH: SLCR SETTINGS | |
255 | // .. START: CLOCK CONTROL SLCR REGISTERS | |
256 | // .. CLKACT = 0x1 | |
257 | // .. ==> 0XF8000128[0:0] = 0x00000001U | |
258 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
259 | // .. DIVISOR0 = 0x23 | |
260 | // .. ==> 0XF8000128[13:8] = 0x00000023U | |
261 | // .. ==> MASK : 0x00003F00U VAL : 0x00002300U | |
262 | // .. DIVISOR1 = 0x3 | |
263 | // .. ==> 0XF8000128[25:20] = 0x00000003U | |
264 | // .. ==> MASK : 0x03F00000U VAL : 0x00300000U | |
265 | // .. | |
266 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), | |
267 | // .. CLKACT = 0x1 | |
268 | // .. ==> 0XF8000138[0:0] = 0x00000001U | |
269 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
270 | // .. SRCSEL = 0x0 | |
271 | // .. ==> 0XF8000138[4:4] = 0x00000000U | |
272 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
273 | // .. | |
274 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | |
275 | // .. CLKACT = 0x1 | |
276 | // .. ==> 0XF8000140[0:0] = 0x00000001U | |
277 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
278 | // .. SRCSEL = 0x0 | |
279 | // .. ==> 0XF8000140[6:4] = 0x00000000U | |
280 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
281 | // .. DIVISOR = 0x8 | |
282 | // .. ==> 0XF8000140[13:8] = 0x00000008U | |
283 | // .. ==> MASK : 0x00003F00U VAL : 0x00000800U | |
284 | // .. DIVISOR1 = 0x1 | |
285 | // .. ==> 0XF8000140[25:20] = 0x00000001U | |
286 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
287 | // .. | |
288 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), | |
289 | // .. CLKACT = 0x1 | |
290 | // .. ==> 0XF800014C[0:0] = 0x00000001U | |
291 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
292 | // .. SRCSEL = 0x0 | |
293 | // .. ==> 0XF800014C[5:4] = 0x00000000U | |
294 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
295 | // .. DIVISOR = 0x5 | |
296 | // .. ==> 0XF800014C[13:8] = 0x00000005U | |
297 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | |
298 | // .. | |
299 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), | |
300 | // .. CLKACT0 = 0x1 | |
301 | // .. ==> 0XF8000150[0:0] = 0x00000001U | |
302 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
303 | // .. CLKACT1 = 0x0 | |
304 | // .. ==> 0XF8000150[1:1] = 0x00000000U | |
305 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
306 | // .. SRCSEL = 0x0 | |
307 | // .. ==> 0XF8000150[5:4] = 0x00000000U | |
308 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
309 | // .. DIVISOR = 0x14 | |
310 | // .. ==> 0XF8000150[13:8] = 0x00000014U | |
311 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
312 | // .. | |
313 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), | |
314 | // .. CLKACT0 = 0x0 | |
315 | // .. ==> 0XF8000154[0:0] = 0x00000000U | |
316 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
317 | // .. CLKACT1 = 0x1 | |
318 | // .. ==> 0XF8000154[1:1] = 0x00000001U | |
319 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
320 | // .. SRCSEL = 0x0 | |
321 | // .. ==> 0XF8000154[5:4] = 0x00000000U | |
322 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
323 | // .. DIVISOR = 0x14 | |
324 | // .. ==> 0XF8000154[13:8] = 0x00000014U | |
325 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
326 | // .. | |
327 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), | |
328 | // .. CLKACT = 0x1 | |
329 | // .. ==> 0XF8000168[0:0] = 0x00000001U | |
330 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
331 | // .. SRCSEL = 0x0 | |
332 | // .. ==> 0XF8000168[5:4] = 0x00000000U | |
333 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
334 | // .. DIVISOR = 0x5 | |
335 | // .. ==> 0XF8000168[13:8] = 0x00000005U | |
336 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | |
337 | // .. | |
338 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), | |
339 | // .. SRCSEL = 0x0 | |
340 | // .. ==> 0XF8000170[5:4] = 0x00000000U | |
341 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
342 | // .. DIVISOR0 = 0xa | |
343 | // .. ==> 0XF8000170[13:8] = 0x0000000AU | |
344 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | |
345 | // .. DIVISOR1 = 0x1 | |
346 | // .. ==> 0XF8000170[25:20] = 0x00000001U | |
347 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
348 | // .. | |
349 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), | |
350 | // .. SRCSEL = 0x0 | |
351 | // .. ==> 0XF8000180[5:4] = 0x00000000U | |
352 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
353 | // .. DIVISOR0 = 0xa | |
354 | // .. ==> 0XF8000180[13:8] = 0x0000000AU | |
355 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | |
356 | // .. DIVISOR1 = 0x1 | |
357 | // .. ==> 0XF8000180[25:20] = 0x00000001U | |
358 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
359 | // .. | |
360 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), | |
361 | // .. SRCSEL = 0x0 | |
362 | // .. ==> 0XF8000190[5:4] = 0x00000000U | |
363 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
364 | // .. DIVISOR0 = 0x1e | |
365 | // .. ==> 0XF8000190[13:8] = 0x0000001EU | |
366 | // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U | |
367 | // .. DIVISOR1 = 0x1 | |
368 | // .. ==> 0XF8000190[25:20] = 0x00000001U | |
369 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
370 | // .. | |
371 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), | |
372 | // .. SRCSEL = 0x0 | |
373 | // .. ==> 0XF80001A0[5:4] = 0x00000000U | |
374 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
375 | // .. DIVISOR0 = 0x14 | |
376 | // .. ==> 0XF80001A0[13:8] = 0x00000014U | |
377 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
378 | // .. DIVISOR1 = 0x1 | |
379 | // .. ==> 0XF80001A0[25:20] = 0x00000001U | |
380 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
381 | // .. | |
382 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), | |
383 | // .. CLK_621_TRUE = 0x1 | |
384 | // .. ==> 0XF80001C4[0:0] = 0x00000001U | |
385 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
386 | // .. | |
387 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | |
388 | // .. DMA_CPU_2XCLKACT = 0x1 | |
389 | // .. ==> 0XF800012C[0:0] = 0x00000001U | |
390 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
391 | // .. USB0_CPU_1XCLKACT = 0x1 | |
392 | // .. ==> 0XF800012C[2:2] = 0x00000001U | |
393 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
394 | // .. USB1_CPU_1XCLKACT = 0x1 | |
395 | // .. ==> 0XF800012C[3:3] = 0x00000001U | |
396 | // .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
397 | // .. GEM0_CPU_1XCLKACT = 0x1 | |
398 | // .. ==> 0XF800012C[6:6] = 0x00000001U | |
399 | // .. ==> MASK : 0x00000040U VAL : 0x00000040U | |
400 | // .. GEM1_CPU_1XCLKACT = 0x0 | |
401 | // .. ==> 0XF800012C[7:7] = 0x00000000U | |
402 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
403 | // .. SDI0_CPU_1XCLKACT = 0x1 | |
404 | // .. ==> 0XF800012C[10:10] = 0x00000001U | |
405 | // .. ==> MASK : 0x00000400U VAL : 0x00000400U | |
406 | // .. SDI1_CPU_1XCLKACT = 0x0 | |
407 | // .. ==> 0XF800012C[11:11] = 0x00000000U | |
408 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
409 | // .. SPI0_CPU_1XCLKACT = 0x0 | |
410 | // .. ==> 0XF800012C[14:14] = 0x00000000U | |
411 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
412 | // .. SPI1_CPU_1XCLKACT = 0x0 | |
413 | // .. ==> 0XF800012C[15:15] = 0x00000000U | |
414 | // .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
415 | // .. CAN0_CPU_1XCLKACT = 0x0 | |
416 | // .. ==> 0XF800012C[16:16] = 0x00000000U | |
417 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
418 | // .. CAN1_CPU_1XCLKACT = 0x0 | |
419 | // .. ==> 0XF800012C[17:17] = 0x00000000U | |
420 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
421 | // .. I2C0_CPU_1XCLKACT = 0x1 | |
422 | // .. ==> 0XF800012C[18:18] = 0x00000001U | |
423 | // .. ==> MASK : 0x00040000U VAL : 0x00040000U | |
424 | // .. I2C1_CPU_1XCLKACT = 0x1 | |
425 | // .. ==> 0XF800012C[19:19] = 0x00000001U | |
426 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
427 | // .. UART0_CPU_1XCLKACT = 0x0 | |
428 | // .. ==> 0XF800012C[20:20] = 0x00000000U | |
429 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
430 | // .. UART1_CPU_1XCLKACT = 0x1 | |
431 | // .. ==> 0XF800012C[21:21] = 0x00000001U | |
432 | // .. ==> MASK : 0x00200000U VAL : 0x00200000U | |
433 | // .. GPIO_CPU_1XCLKACT = 0x1 | |
434 | // .. ==> 0XF800012C[22:22] = 0x00000001U | |
435 | // .. ==> MASK : 0x00400000U VAL : 0x00400000U | |
436 | // .. LQSPI_CPU_1XCLKACT = 0x1 | |
437 | // .. ==> 0XF800012C[23:23] = 0x00000001U | |
438 | // .. ==> MASK : 0x00800000U VAL : 0x00800000U | |
439 | // .. SMC_CPU_1XCLKACT = 0x1 | |
440 | // .. ==> 0XF800012C[24:24] = 0x00000001U | |
441 | // .. ==> MASK : 0x01000000U VAL : 0x01000000U | |
442 | // .. | |
443 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), | |
444 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | |
445 | // .. START: THIS SHOULD BE BLANK | |
446 | // .. FINISH: THIS SHOULD BE BLANK | |
447 | // .. START: LOCK IT BACK | |
448 | // .. LOCK_KEY = 0X767B | |
449 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
450 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
451 | // .. | |
452 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
453 | // .. FINISH: LOCK IT BACK | |
454 | // FINISH: top | |
455 | // | |
456 | EMIT_EXIT(), | |
457 | ||
458 | // | |
459 | }; | |
460 | ||
461 | unsigned long ps7_ddr_init_data_3_0[] = { | |
462 | // START: top | |
463 | // .. START: DDR INITIALIZATION | |
464 | // .. .. START: LOCK DDR | |
465 | // .. .. reg_ddrc_soft_rstb = 0 | |
466 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | |
467 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
468 | // .. .. reg_ddrc_powerdown_en = 0x0 | |
469 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | |
470 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
471 | // .. .. reg_ddrc_data_bus_width = 0x0 | |
472 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | |
473 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | |
474 | // .. .. reg_ddrc_burst8_refresh = 0x0 | |
475 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | |
476 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
477 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | |
478 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | |
479 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | |
480 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | |
481 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | |
482 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
483 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | |
484 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | |
485 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
486 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | |
487 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | |
488 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
489 | // .. .. | |
490 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | |
491 | // .. .. FINISH: LOCK DDR | |
492 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 | |
493 | // .. .. ==> 0XF8006004[11:0] = 0x00000081U | |
494 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U | |
495 | // .. .. reserved_reg_ddrc_active_ranks = 0x1 | |
496 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | |
497 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | |
498 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | |
499 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | |
500 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | |
501 | // .. .. | |
502 | EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), | |
503 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | |
504 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | |
505 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | |
506 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | |
507 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | |
508 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | |
509 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | |
510 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | |
511 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | |
512 | // .. .. | |
513 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | |
514 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | |
515 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | |
516 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | |
517 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | |
518 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | |
519 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | |
520 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | |
521 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | |
522 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | |
523 | // .. .. | |
524 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | |
525 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | |
526 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | |
527 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | |
528 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | |
529 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | |
530 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | |
531 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | |
532 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | |
533 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | |
534 | // .. .. | |
535 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | |
536 | // .. .. reg_ddrc_t_rc = 0x1a | |
537 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | |
538 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | |
539 | // .. .. reg_ddrc_t_rfc_min = 0xa0 | |
540 | // .. .. ==> 0XF8006014[13:6] = 0x000000A0U | |
541 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U | |
542 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | |
543 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | |
544 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | |
545 | // .. .. | |
546 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), | |
547 | // .. .. reg_ddrc_wr2pre = 0x12 | |
548 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | |
549 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | |
550 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | |
551 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | |
552 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | |
553 | // .. .. reg_ddrc_t_faw = 0x16 | |
554 | // .. .. ==> 0XF8006018[15:10] = 0x00000016U | |
555 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U | |
556 | // .. .. reg_ddrc_t_ras_max = 0x24 | |
557 | // .. .. ==> 0XF8006018[21:16] = 0x00000024U | |
558 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U | |
559 | // .. .. reg_ddrc_t_ras_min = 0x13 | |
560 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | |
561 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | |
562 | // .. .. reg_ddrc_t_cke = 0x4 | |
563 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | |
564 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | |
565 | // .. .. | |
566 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), | |
567 | // .. .. reg_ddrc_write_latency = 0x5 | |
568 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | |
569 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | |
570 | // .. .. reg_ddrc_rd2wr = 0x7 | |
571 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | |
572 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | |
573 | // .. .. reg_ddrc_wr2rd = 0xe | |
574 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | |
575 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | |
576 | // .. .. reg_ddrc_t_xp = 0x4 | |
577 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | |
578 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | |
579 | // .. .. reg_ddrc_pad_pd = 0x0 | |
580 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | |
581 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | |
582 | // .. .. reg_ddrc_rd2pre = 0x4 | |
583 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | |
584 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | |
585 | // .. .. reg_ddrc_t_rcd = 0x7 | |
586 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | |
587 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | |
588 | // .. .. | |
589 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | |
590 | // .. .. reg_ddrc_t_ccd = 0x4 | |
591 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | |
592 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | |
593 | // .. .. reg_ddrc_t_rrd = 0x6 | |
594 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | |
595 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | |
596 | // .. .. reg_ddrc_refresh_margin = 0x2 | |
597 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | |
598 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
599 | // .. .. reg_ddrc_t_rp = 0x7 | |
600 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | |
601 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | |
602 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | |
603 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | |
604 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | |
605 | // .. .. reg_ddrc_mobile = 0x0 | |
606 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | |
607 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
608 | // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 | |
609 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | |
610 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
611 | // .. .. reg_ddrc_read_latency = 0x7 | |
612 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | |
613 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | |
614 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | |
615 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | |
616 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | |
617 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | |
618 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | |
619 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | |
620 | // .. .. | |
621 | EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), | |
622 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | |
623 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | |
624 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
625 | // .. .. reg_ddrc_prefer_write = 0x0 | |
626 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | |
627 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
628 | // .. .. reg_ddrc_mr_wr = 0x0 | |
629 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | |
630 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
631 | // .. .. reg_ddrc_mr_addr = 0x0 | |
632 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | |
633 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | |
634 | // .. .. reg_ddrc_mr_data = 0x0 | |
635 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | |
636 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | |
637 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | |
638 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | |
639 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
640 | // .. .. reg_ddrc_mr_type = 0x0 | |
641 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | |
642 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | |
643 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | |
644 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | |
645 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | |
646 | // .. .. | |
647 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), | |
648 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | |
649 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | |
650 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | |
651 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | |
652 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | |
653 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | |
654 | // .. .. reg_ddrc_t_mrd = 0x4 | |
655 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | |
656 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | |
657 | // .. .. | |
658 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | |
659 | // .. .. reg_ddrc_emr2 = 0x8 | |
660 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | |
661 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | |
662 | // .. .. reg_ddrc_emr3 = 0x0 | |
663 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | |
664 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | |
665 | // .. .. | |
666 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | |
667 | // .. .. reg_ddrc_mr = 0x930 | |
668 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | |
669 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | |
670 | // .. .. reg_ddrc_emr = 0x4 | |
671 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | |
672 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | |
673 | // .. .. | |
674 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | |
675 | // .. .. reg_ddrc_burst_rdwr = 0x4 | |
676 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | |
677 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | |
678 | // .. .. reg_ddrc_pre_cke_x1024 = 0x105 | |
679 | // .. .. ==> 0XF8006034[13:4] = 0x00000105U | |
680 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U | |
681 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | |
682 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | |
683 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | |
684 | // .. .. reg_ddrc_burstchop = 0x0 | |
685 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | |
686 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | |
687 | // .. .. | |
688 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), | |
689 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | |
690 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | |
691 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
692 | // .. .. reg_ddrc_dis_dq = 0x0 | |
693 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | |
694 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
695 | // .. .. | |
696 | EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), | |
697 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | |
698 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | |
699 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | |
700 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | |
701 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | |
702 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | |
703 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | |
704 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | |
705 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | |
706 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | |
707 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | |
708 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | |
709 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | |
710 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | |
711 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | |
712 | // .. .. | |
713 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | |
714 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | |
715 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | |
716 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
717 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | |
718 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | |
719 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
720 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | |
721 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | |
722 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | |
723 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | |
724 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | |
725 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | |
726 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | |
727 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | |
728 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | |
729 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | |
730 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | |
731 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | |
732 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | |
733 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | |
734 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | |
735 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | |
736 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | |
737 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | |
738 | // .. .. | |
739 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | |
740 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | |
741 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | |
742 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | |
743 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | |
744 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | |
745 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | |
746 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | |
747 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | |
748 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | |
749 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | |
750 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | |
751 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | |
752 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | |
753 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | |
754 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | |
755 | // .. .. reg_ddrc_addrmap_row_b14 = 0x6 | |
756 | // .. .. ==> 0XF8006044[23:20] = 0x00000006U | |
757 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U | |
758 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | |
759 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | |
760 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | |
761 | // .. .. | |
762 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), | |
763 | // .. .. reg_phy_rd_local_odt = 0x0 | |
764 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | |
765 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | |
766 | // .. .. reg_phy_wr_local_odt = 0x3 | |
767 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | |
768 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | |
769 | // .. .. reg_phy_idle_local_odt = 0x3 | |
770 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | |
771 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | |
772 | // .. .. | |
773 | EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), | |
774 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | |
775 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | |
776 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
777 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | |
778 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | |
779 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
780 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | |
781 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | |
782 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | |
783 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | |
784 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | |
785 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
786 | // .. .. reg_phy_use_fixed_re = 0x1 | |
787 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | |
788 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | |
789 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | |
790 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | |
791 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
792 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | |
793 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | |
794 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
795 | // .. .. reg_phy_clk_stall_level = 0x0 | |
796 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | |
797 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
798 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | |
799 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | |
800 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | |
801 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | |
802 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | |
803 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | |
804 | // .. .. | |
805 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | |
806 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | |
807 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | |
808 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
809 | // .. .. | |
810 | EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), | |
811 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | |
812 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | |
813 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | |
814 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | |
815 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | |
816 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
817 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | |
818 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | |
819 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | |
820 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | |
821 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | |
822 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | |
823 | // .. .. | |
824 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | |
825 | // .. .. reg_ddrc_pageclose = 0x0 | |
826 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | |
827 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
828 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | |
829 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | |
830 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | |
831 | // .. .. reg_ddrc_auto_pre_en = 0x0 | |
832 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | |
833 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
834 | // .. .. reg_ddrc_refresh_update_level = 0x0 | |
835 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | |
836 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
837 | // .. .. reg_ddrc_dis_wc = 0x0 | |
838 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | |
839 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
840 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | |
841 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | |
842 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
843 | // .. .. reg_ddrc_selfref_en = 0x0 | |
844 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | |
845 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
846 | // .. .. | |
847 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | |
848 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | |
849 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | |
850 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | |
851 | // .. .. reg_arb_go2critical_en = 0x1 | |
852 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | |
853 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | |
854 | // .. .. | |
855 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | |
856 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | |
857 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | |
858 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | |
859 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | |
860 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | |
861 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | |
862 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | |
863 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | |
864 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | |
865 | // .. .. | |
866 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | |
867 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | |
868 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | |
869 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | |
870 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | |
871 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | |
872 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | |
873 | // .. .. | |
874 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | |
875 | // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 | |
876 | // .. .. ==> 0XF8006078[3:0] = 0x00000001U | |
877 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U | |
878 | // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 | |
879 | // .. .. ==> 0XF8006078[7:4] = 0x00000001U | |
880 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U | |
881 | // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 | |
882 | // .. .. ==> 0XF8006078[11:8] = 0x00000001U | |
883 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U | |
884 | // .. .. reg_ddrc_t_cksre = 0x6 | |
885 | // .. .. ==> 0XF8006078[15:12] = 0x00000006U | |
886 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | |
887 | // .. .. reg_ddrc_t_cksrx = 0x6 | |
888 | // .. .. ==> 0XF8006078[19:16] = 0x00000006U | |
889 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | |
890 | // .. .. reg_ddrc_t_ckesr = 0x4 | |
891 | // .. .. ==> 0XF8006078[25:20] = 0x00000004U | |
892 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U | |
893 | // .. .. | |
894 | EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), | |
895 | // .. .. reg_ddrc_t_ckpde = 0x2 | |
896 | // .. .. ==> 0XF800607C[3:0] = 0x00000002U | |
897 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U | |
898 | // .. .. reg_ddrc_t_ckpdx = 0x2 | |
899 | // .. .. ==> 0XF800607C[7:4] = 0x00000002U | |
900 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
901 | // .. .. reg_ddrc_t_ckdpde = 0x2 | |
902 | // .. .. ==> 0XF800607C[11:8] = 0x00000002U | |
903 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
904 | // .. .. reg_ddrc_t_ckdpdx = 0x2 | |
905 | // .. .. ==> 0XF800607C[15:12] = 0x00000002U | |
906 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U | |
907 | // .. .. reg_ddrc_t_ckcsx = 0x3 | |
908 | // .. .. ==> 0XF800607C[19:16] = 0x00000003U | |
909 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U | |
910 | // .. .. | |
911 | EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), | |
912 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | |
913 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | |
914 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
915 | // .. .. reg_ddrc_ddr3 = 0x1 | |
916 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | |
917 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
918 | // .. .. reg_ddrc_t_mod = 0x200 | |
919 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | |
920 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | |
921 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | |
922 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | |
923 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | |
924 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | |
925 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | |
926 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | |
927 | // .. .. | |
928 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | |
929 | // .. .. t_zq_short_interval_x1024 = 0xcb73 | |
930 | // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U | |
931 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U | |
932 | // .. .. dram_rstn_x1024 = 0x69 | |
933 | // .. .. ==> 0XF80060A8[27:20] = 0x00000069U | |
934 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U | |
935 | // .. .. | |
936 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), | |
937 | // .. .. deeppowerdown_en = 0x0 | |
938 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | |
939 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
940 | // .. .. deeppowerdown_to_x1024 = 0xff | |
941 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | |
942 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | |
943 | // .. .. | |
944 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | |
945 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | |
946 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | |
947 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | |
948 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | |
949 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | |
950 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | |
951 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | |
952 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | |
953 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
954 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | |
955 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | |
956 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
957 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | |
958 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | |
959 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | |
960 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | |
961 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | |
962 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | |
963 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | |
964 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | |
965 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
966 | // .. .. | |
967 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | |
968 | // .. .. reg_ddrc_skip_ocd = 0x1 | |
969 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | |
970 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | |
971 | // .. .. | |
972 | EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), | |
973 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | |
974 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | |
975 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | |
976 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | |
977 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | |
978 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | |
979 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | |
980 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | |
981 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | |
982 | // .. .. | |
983 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | |
984 | // .. .. START: RESET ECC ERROR | |
985 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | |
986 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | |
987 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
988 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | |
989 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | |
990 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
991 | // .. .. | |
992 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | |
993 | // .. .. FINISH: RESET ECC ERROR | |
994 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | |
995 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | |
996 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
997 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | |
998 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | |
999 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1000 | // .. .. | |
1001 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | |
1002 | // .. .. CORR_ECC_LOG_VALID = 0x0 | |
1003 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | |
1004 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1005 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | |
1006 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | |
1007 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | |
1008 | // .. .. | |
1009 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | |
1010 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | |
1011 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | |
1012 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1013 | // .. .. | |
1014 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | |
1015 | // .. .. STAT_NUM_CORR_ERR = 0x0 | |
1016 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | |
1017 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | |
1018 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | |
1019 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | |
1020 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | |
1021 | // .. .. | |
1022 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | |
1023 | // .. .. reg_ddrc_ecc_mode = 0x0 | |
1024 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | |
1025 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | |
1026 | // .. .. reg_ddrc_dis_scrub = 0x1 | |
1027 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | |
1028 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
1029 | // .. .. | |
1030 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | |
1031 | // .. .. reg_phy_dif_on = 0x0 | |
1032 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | |
1033 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
1034 | // .. .. reg_phy_dif_off = 0x0 | |
1035 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | |
1036 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
1037 | // .. .. | |
1038 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | |
1039 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
1040 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | |
1041 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1042 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
1043 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | |
1044 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1045 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
1046 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | |
1047 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1048 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
1049 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | |
1050 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1051 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
1052 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | |
1053 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
1054 | // .. .. reg_phy_bist_err_clr = 0x0 | |
1055 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | |
1056 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
1057 | // .. .. reg_phy_dq_offset = 0x40 | |
1058 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | |
1059 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
1060 | // .. .. | |
1061 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), | |
1062 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
1063 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | |
1064 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1065 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
1066 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | |
1067 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1068 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
1069 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | |
1070 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1071 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
1072 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | |
1073 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1074 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
1075 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | |
1076 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
1077 | // .. .. reg_phy_bist_err_clr = 0x0 | |
1078 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | |
1079 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
1080 | // .. .. reg_phy_dq_offset = 0x40 | |
1081 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | |
1082 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
1083 | // .. .. | |
1084 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), | |
1085 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
1086 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | |
1087 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1088 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
1089 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | |
1090 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1091 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
1092 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | |
1093 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1094 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
1095 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | |
1096 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1097 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
1098 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | |
1099 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
1100 | // .. .. reg_phy_bist_err_clr = 0x0 | |
1101 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | |
1102 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
1103 | // .. .. reg_phy_dq_offset = 0x40 | |
1104 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | |
1105 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
1106 | // .. .. | |
1107 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), | |
1108 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
1109 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | |
1110 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1111 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
1112 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | |
1113 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1114 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
1115 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | |
1116 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1117 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
1118 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | |
1119 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1120 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
1121 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | |
1122 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
1123 | // .. .. reg_phy_bist_err_clr = 0x0 | |
1124 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | |
1125 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
1126 | // .. .. reg_phy_dq_offset = 0x40 | |
1127 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | |
1128 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
1129 | // .. .. | |
1130 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), | |
1131 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | |
1132 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | |
1133 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | |
1134 | // .. .. reg_phy_gatelvl_init_ratio = 0xb0 | |
1135 | // .. .. ==> 0XF800612C[19:10] = 0x000000B0U | |
1136 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U | |
1137 | // .. .. | |
1138 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), | |
1139 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | |
1140 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | |
1141 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | |
1142 | // .. .. reg_phy_gatelvl_init_ratio = 0xb1 | |
1143 | // .. .. ==> 0XF8006130[19:10] = 0x000000B1U | |
1144 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U | |
1145 | // .. .. | |
1146 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), | |
1147 | // .. .. reg_phy_wrlvl_init_ratio = 0x3 | |
1148 | // .. .. ==> 0XF8006134[9:0] = 0x00000003U | |
1149 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U | |
1150 | // .. .. reg_phy_gatelvl_init_ratio = 0xbc | |
1151 | // .. .. ==> 0XF8006134[19:10] = 0x000000BCU | |
1152 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U | |
1153 | // .. .. | |
1154 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), | |
1155 | // .. .. reg_phy_wrlvl_init_ratio = 0x3 | |
1156 | // .. .. ==> 0XF8006138[9:0] = 0x00000003U | |
1157 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U | |
1158 | // .. .. reg_phy_gatelvl_init_ratio = 0xbb | |
1159 | // .. .. ==> 0XF8006138[19:10] = 0x000000BBU | |
1160 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U | |
1161 | // .. .. | |
1162 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), | |
1163 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
1164 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | |
1165 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
1166 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
1167 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | |
1168 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1169 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
1170 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | |
1171 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1172 | // .. .. | |
1173 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | |
1174 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
1175 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | |
1176 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
1177 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
1178 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | |
1179 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1180 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
1181 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | |
1182 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1183 | // .. .. | |
1184 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | |
1185 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
1186 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | |
1187 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
1188 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
1189 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | |
1190 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1191 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
1192 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | |
1193 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1194 | // .. .. | |
1195 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | |
1196 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
1197 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | |
1198 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
1199 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
1200 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | |
1201 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1202 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
1203 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | |
1204 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1205 | // .. .. | |
1206 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | |
1207 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | |
1208 | // .. .. ==> 0XF8006154[9:0] = 0x00000077U | |
1209 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | |
1210 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
1211 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | |
1212 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1213 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
1214 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | |
1215 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1216 | // .. .. | |
1217 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), | |
1218 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | |
1219 | // .. .. ==> 0XF8006158[9:0] = 0x00000077U | |
1220 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | |
1221 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
1222 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | |
1223 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1224 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
1225 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | |
1226 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1227 | // .. .. | |
1228 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), | |
1229 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 | |
1230 | // .. .. ==> 0XF800615C[9:0] = 0x00000083U | |
1231 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U | |
1232 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
1233 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | |
1234 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1235 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
1236 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | |
1237 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1238 | // .. .. | |
1239 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), | |
1240 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 | |
1241 | // .. .. ==> 0XF8006160[9:0] = 0x00000083U | |
1242 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U | |
1243 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
1244 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | |
1245 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1246 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
1247 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | |
1248 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1249 | // .. .. | |
1250 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), | |
1251 | // .. .. reg_phy_fifo_we_slave_ratio = 0x105 | |
1252 | // .. .. ==> 0XF8006168[10:0] = 0x00000105U | |
1253 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U | |
1254 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
1255 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | |
1256 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1257 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
1258 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | |
1259 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
1260 | // .. .. | |
1261 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), | |
1262 | // .. .. reg_phy_fifo_we_slave_ratio = 0x106 | |
1263 | // .. .. ==> 0XF800616C[10:0] = 0x00000106U | |
1264 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U | |
1265 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
1266 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | |
1267 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1268 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
1269 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | |
1270 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
1271 | // .. .. | |
1272 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), | |
1273 | // .. .. reg_phy_fifo_we_slave_ratio = 0x111 | |
1274 | // .. .. ==> 0XF8006170[10:0] = 0x00000111U | |
1275 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U | |
1276 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
1277 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | |
1278 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1279 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
1280 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | |
1281 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
1282 | // .. .. | |
1283 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), | |
1284 | // .. .. reg_phy_fifo_we_slave_ratio = 0x110 | |
1285 | // .. .. ==> 0XF8006174[10:0] = 0x00000110U | |
1286 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U | |
1287 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
1288 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | |
1289 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1290 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
1291 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | |
1292 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
1293 | // .. .. | |
1294 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), | |
1295 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | |
1296 | // .. .. ==> 0XF800617C[9:0] = 0x000000B7U | |
1297 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | |
1298 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
1299 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | |
1300 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1301 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
1302 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | |
1303 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1304 | // .. .. | |
1305 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), | |
1306 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | |
1307 | // .. .. ==> 0XF8006180[9:0] = 0x000000B7U | |
1308 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | |
1309 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
1310 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | |
1311 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1312 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
1313 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | |
1314 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1315 | // .. .. | |
1316 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), | |
1317 | // .. .. reg_phy_wr_data_slave_ratio = 0xc3 | |
1318 | // .. .. ==> 0XF8006184[9:0] = 0x000000C3U | |
1319 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U | |
1320 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
1321 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | |
1322 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1323 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
1324 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | |
1325 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1326 | // .. .. | |
1327 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), | |
1328 | // .. .. reg_phy_wr_data_slave_ratio = 0xc3 | |
1329 | // .. .. ==> 0XF8006188[9:0] = 0x000000C3U | |
1330 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U | |
1331 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
1332 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | |
1333 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
1334 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
1335 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | |
1336 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
1337 | // .. .. | |
1338 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), | |
1339 | // .. .. reg_phy_bl2 = 0x0 | |
1340 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | |
1341 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1342 | // .. .. reg_phy_at_spd_atpg = 0x0 | |
1343 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | |
1344 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1345 | // .. .. reg_phy_bist_enable = 0x0 | |
1346 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | |
1347 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1348 | // .. .. reg_phy_bist_force_err = 0x0 | |
1349 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | |
1350 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
1351 | // .. .. reg_phy_bist_mode = 0x0 | |
1352 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | |
1353 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
1354 | // .. .. reg_phy_invert_clkout = 0x1 | |
1355 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | |
1356 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
1357 | // .. .. reg_phy_sel_logic = 0x0 | |
1358 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | |
1359 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
1360 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | |
1361 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | |
1362 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | |
1363 | // .. .. reg_phy_ctrl_slave_force = 0x0 | |
1364 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | |
1365 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
1366 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | |
1367 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | |
1368 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | |
1369 | // .. .. reg_phy_lpddr = 0x0 | |
1370 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | |
1371 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | |
1372 | // .. .. reg_phy_cmd_latency = 0x0 | |
1373 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | |
1374 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | |
1375 | // .. .. | |
1376 | EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), | |
1377 | // .. .. reg_phy_wr_rl_delay = 0x2 | |
1378 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | |
1379 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | |
1380 | // .. .. reg_phy_rd_rl_delay = 0x4 | |
1381 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | |
1382 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | |
1383 | // .. .. reg_phy_dll_lock_diff = 0xf | |
1384 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | |
1385 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | |
1386 | // .. .. reg_phy_use_wr_level = 0x1 | |
1387 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | |
1388 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | |
1389 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | |
1390 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | |
1391 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | |
1392 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | |
1393 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | |
1394 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | |
1395 | // .. .. reg_phy_dis_calib_rst = 0x0 | |
1396 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | |
1397 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1398 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | |
1399 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | |
1400 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | |
1401 | // .. .. | |
1402 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | |
1403 | // .. .. reg_arb_page_addr_mask = 0x0 | |
1404 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | |
1405 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | |
1406 | // .. .. | |
1407 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | |
1408 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
1409 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | |
1410 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1411 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
1412 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | |
1413 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1414 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
1415 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | |
1416 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1417 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
1418 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | |
1419 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1420 | // .. .. | |
1421 | EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), | |
1422 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
1423 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | |
1424 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1425 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
1426 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | |
1427 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1428 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
1429 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | |
1430 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1431 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
1432 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | |
1433 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1434 | // .. .. | |
1435 | EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), | |
1436 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
1437 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | |
1438 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1439 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
1440 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | |
1441 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1442 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
1443 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | |
1444 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1445 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
1446 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | |
1447 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1448 | // .. .. | |
1449 | EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), | |
1450 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
1451 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | |
1452 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1453 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
1454 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | |
1455 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1456 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
1457 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | |
1458 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1459 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
1460 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | |
1461 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1462 | // .. .. | |
1463 | EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), | |
1464 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
1465 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | |
1466 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1467 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
1468 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | |
1469 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1470 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
1471 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | |
1472 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1473 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
1474 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | |
1475 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1476 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
1477 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | |
1478 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
1479 | // .. .. | |
1480 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | |
1481 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
1482 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | |
1483 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1484 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
1485 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | |
1486 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1487 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
1488 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | |
1489 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1490 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
1491 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | |
1492 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1493 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
1494 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | |
1495 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
1496 | // .. .. | |
1497 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | |
1498 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
1499 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | |
1500 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1501 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
1502 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | |
1503 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1504 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
1505 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | |
1506 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1507 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
1508 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | |
1509 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1510 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
1511 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | |
1512 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
1513 | // .. .. | |
1514 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | |
1515 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
1516 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | |
1517 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
1518 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
1519 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | |
1520 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1521 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
1522 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | |
1523 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
1524 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
1525 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | |
1526 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
1527 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
1528 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | |
1529 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
1530 | // .. .. | |
1531 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | |
1532 | // .. .. reg_ddrc_lpddr2 = 0x0 | |
1533 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | |
1534 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1535 | // .. .. reg_ddrc_derate_enable = 0x0 | |
1536 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | |
1537 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1538 | // .. .. reg_ddrc_mr4_margin = 0x0 | |
1539 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | |
1540 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | |
1541 | // .. .. | |
1542 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), | |
1543 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | |
1544 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | |
1545 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | |
1546 | // .. .. | |
1547 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | |
1548 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | |
1549 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | |
1550 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | |
1551 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | |
1552 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | |
1553 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | |
1554 | // .. .. reg_ddrc_t_mrw = 0x5 | |
1555 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | |
1556 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | |
1557 | // .. .. | |
1558 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | |
1559 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 | |
1560 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U | |
1561 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U | |
1562 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | |
1563 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | |
1564 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | |
1565 | // .. .. | |
1566 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), | |
1567 | // .. .. START: POLL ON DCI STATUS | |
1568 | // .. .. DONE = 1 | |
1569 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | |
1570 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | |
1571 | // .. .. | |
1572 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | |
1573 | // .. .. FINISH: POLL ON DCI STATUS | |
1574 | // .. .. START: UNLOCK DDR | |
1575 | // .. .. reg_ddrc_soft_rstb = 0x1 | |
1576 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | |
1577 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1578 | // .. .. reg_ddrc_powerdown_en = 0x0 | |
1579 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | |
1580 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
1581 | // .. .. reg_ddrc_data_bus_width = 0x0 | |
1582 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | |
1583 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | |
1584 | // .. .. reg_ddrc_burst8_refresh = 0x0 | |
1585 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | |
1586 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
1587 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | |
1588 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | |
1589 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | |
1590 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | |
1591 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | |
1592 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
1593 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | |
1594 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | |
1595 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
1596 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | |
1597 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | |
1598 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
1599 | // .. .. | |
1600 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | |
1601 | // .. .. FINISH: UNLOCK DDR | |
1602 | // .. .. START: CHECK DDR STATUS | |
1603 | // .. .. ddrc_reg_operating_mode = 1 | |
1604 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | |
1605 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | |
1606 | // .. .. | |
1607 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | |
1608 | // .. .. FINISH: CHECK DDR STATUS | |
1609 | // .. FINISH: DDR INITIALIZATION | |
1610 | // FINISH: top | |
1611 | // | |
1612 | EMIT_EXIT(), | |
1613 | ||
1614 | // | |
1615 | }; | |
1616 | ||
1617 | unsigned long ps7_mio_init_data_3_0[] = { | |
1618 | // START: top | |
1619 | // .. START: SLCR SETTINGS | |
1620 | // .. UNLOCK_KEY = 0XDF0D | |
1621 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
1622 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
1623 | // .. | |
1624 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
1625 | // .. FINISH: SLCR SETTINGS | |
1626 | // .. START: OCM REMAPPING | |
1627 | // .. FINISH: OCM REMAPPING | |
1628 | // .. START: DDRIOB SETTINGS | |
1629 | // .. reserved_INP_POWER = 0x0 | |
1630 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | |
1631 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1632 | // .. INP_TYPE = 0x0 | |
1633 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | |
1634 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
1635 | // .. DCI_UPDATE_B = 0x0 | |
1636 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | |
1637 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1638 | // .. TERM_EN = 0x0 | |
1639 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | |
1640 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
1641 | // .. DCI_TYPE = 0x0 | |
1642 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | |
1643 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
1644 | // .. IBUF_DISABLE_MODE = 0x0 | |
1645 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | |
1646 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1647 | // .. TERM_DISABLE_MODE = 0x0 | |
1648 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | |
1649 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1650 | // .. OUTPUT_EN = 0x3 | |
1651 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | |
1652 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1653 | // .. PULLUP_EN = 0x0 | |
1654 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | |
1655 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1656 | // .. | |
1657 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | |
1658 | // .. reserved_INP_POWER = 0x0 | |
1659 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | |
1660 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1661 | // .. INP_TYPE = 0x0 | |
1662 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | |
1663 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
1664 | // .. DCI_UPDATE_B = 0x0 | |
1665 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | |
1666 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1667 | // .. TERM_EN = 0x0 | |
1668 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | |
1669 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
1670 | // .. DCI_TYPE = 0x0 | |
1671 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | |
1672 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
1673 | // .. IBUF_DISABLE_MODE = 0x0 | |
1674 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | |
1675 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1676 | // .. TERM_DISABLE_MODE = 0x0 | |
1677 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | |
1678 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1679 | // .. OUTPUT_EN = 0x3 | |
1680 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | |
1681 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1682 | // .. PULLUP_EN = 0x0 | |
1683 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | |
1684 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1685 | // .. | |
1686 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | |
1687 | // .. reserved_INP_POWER = 0x0 | |
1688 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | |
1689 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1690 | // .. INP_TYPE = 0x1 | |
1691 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | |
1692 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | |
1693 | // .. DCI_UPDATE_B = 0x0 | |
1694 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | |
1695 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1696 | // .. TERM_EN = 0x1 | |
1697 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | |
1698 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
1699 | // .. DCI_TYPE = 0x3 | |
1700 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | |
1701 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
1702 | // .. IBUF_DISABLE_MODE = 0 | |
1703 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | |
1704 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1705 | // .. TERM_DISABLE_MODE = 0 | |
1706 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | |
1707 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1708 | // .. OUTPUT_EN = 0x3 | |
1709 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | |
1710 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1711 | // .. PULLUP_EN = 0x0 | |
1712 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | |
1713 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1714 | // .. | |
1715 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | |
1716 | // .. reserved_INP_POWER = 0x0 | |
1717 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | |
1718 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1719 | // .. INP_TYPE = 0x1 | |
1720 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | |
1721 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | |
1722 | // .. DCI_UPDATE_B = 0x0 | |
1723 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | |
1724 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1725 | // .. TERM_EN = 0x1 | |
1726 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | |
1727 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
1728 | // .. DCI_TYPE = 0x3 | |
1729 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | |
1730 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
1731 | // .. IBUF_DISABLE_MODE = 0 | |
1732 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | |
1733 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1734 | // .. TERM_DISABLE_MODE = 0 | |
1735 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | |
1736 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1737 | // .. OUTPUT_EN = 0x3 | |
1738 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | |
1739 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1740 | // .. PULLUP_EN = 0x0 | |
1741 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | |
1742 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1743 | // .. | |
1744 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | |
1745 | // .. reserved_INP_POWER = 0x0 | |
1746 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | |
1747 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1748 | // .. INP_TYPE = 0x2 | |
1749 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | |
1750 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | |
1751 | // .. DCI_UPDATE_B = 0x0 | |
1752 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | |
1753 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1754 | // .. TERM_EN = 0x1 | |
1755 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | |
1756 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
1757 | // .. DCI_TYPE = 0x3 | |
1758 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | |
1759 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
1760 | // .. IBUF_DISABLE_MODE = 0 | |
1761 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | |
1762 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1763 | // .. TERM_DISABLE_MODE = 0 | |
1764 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | |
1765 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1766 | // .. OUTPUT_EN = 0x3 | |
1767 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | |
1768 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1769 | // .. PULLUP_EN = 0x0 | |
1770 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | |
1771 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1772 | // .. | |
1773 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | |
1774 | // .. reserved_INP_POWER = 0x0 | |
1775 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | |
1776 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1777 | // .. INP_TYPE = 0x2 | |
1778 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | |
1779 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | |
1780 | // .. DCI_UPDATE_B = 0x0 | |
1781 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | |
1782 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1783 | // .. TERM_EN = 0x1 | |
1784 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | |
1785 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
1786 | // .. DCI_TYPE = 0x3 | |
1787 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | |
1788 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
1789 | // .. IBUF_DISABLE_MODE = 0 | |
1790 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | |
1791 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1792 | // .. TERM_DISABLE_MODE = 0 | |
1793 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | |
1794 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1795 | // .. OUTPUT_EN = 0x3 | |
1796 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | |
1797 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1798 | // .. PULLUP_EN = 0x0 | |
1799 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | |
1800 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1801 | // .. | |
1802 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | |
1803 | // .. reserved_INP_POWER = 0x0 | |
1804 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | |
1805 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1806 | // .. INP_TYPE = 0x0 | |
1807 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | |
1808 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
1809 | // .. DCI_UPDATE_B = 0x0 | |
1810 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | |
1811 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1812 | // .. TERM_EN = 0x0 | |
1813 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | |
1814 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
1815 | // .. DCI_TYPE = 0x0 | |
1816 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | |
1817 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
1818 | // .. IBUF_DISABLE_MODE = 0x0 | |
1819 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | |
1820 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
1821 | // .. TERM_DISABLE_MODE = 0x0 | |
1822 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | |
1823 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
1824 | // .. OUTPUT_EN = 0x3 | |
1825 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | |
1826 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
1827 | // .. PULLUP_EN = 0x0 | |
1828 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | |
1829 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
1830 | // .. | |
1831 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | |
1832 | // .. reserved_DRIVE_P = 0x1c | |
1833 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | |
1834 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
1835 | // .. reserved_DRIVE_N = 0xc | |
1836 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | |
1837 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
1838 | // .. reserved_SLEW_P = 0x3 | |
1839 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | |
1840 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | |
1841 | // .. reserved_SLEW_N = 0x3 | |
1842 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | |
1843 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | |
1844 | // .. reserved_GTL = 0x0 | |
1845 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | |
1846 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
1847 | // .. reserved_RTERM = 0x0 | |
1848 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | |
1849 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
1850 | // .. | |
1851 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | |
1852 | // .. reserved_DRIVE_P = 0x1c | |
1853 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | |
1854 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
1855 | // .. reserved_DRIVE_N = 0xc | |
1856 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | |
1857 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
1858 | // .. reserved_SLEW_P = 0x6 | |
1859 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | |
1860 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
1861 | // .. reserved_SLEW_N = 0x1f | |
1862 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | |
1863 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
1864 | // .. reserved_GTL = 0x0 | |
1865 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | |
1866 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
1867 | // .. reserved_RTERM = 0x0 | |
1868 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | |
1869 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
1870 | // .. | |
1871 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | |
1872 | // .. reserved_DRIVE_P = 0x1c | |
1873 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | |
1874 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
1875 | // .. reserved_DRIVE_N = 0xc | |
1876 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | |
1877 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
1878 | // .. reserved_SLEW_P = 0x6 | |
1879 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | |
1880 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
1881 | // .. reserved_SLEW_N = 0x1f | |
1882 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | |
1883 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
1884 | // .. reserved_GTL = 0x0 | |
1885 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | |
1886 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
1887 | // .. reserved_RTERM = 0x0 | |
1888 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | |
1889 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
1890 | // .. | |
1891 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | |
1892 | // .. reserved_DRIVE_P = 0x1c | |
1893 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | |
1894 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
1895 | // .. reserved_DRIVE_N = 0xc | |
1896 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | |
1897 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
1898 | // .. reserved_SLEW_P = 0x6 | |
1899 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | |
1900 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
1901 | // .. reserved_SLEW_N = 0x1f | |
1902 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | |
1903 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
1904 | // .. reserved_GTL = 0x0 | |
1905 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | |
1906 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
1907 | // .. reserved_RTERM = 0x0 | |
1908 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | |
1909 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
1910 | // .. | |
1911 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | |
1912 | // .. VREF_INT_EN = 0x1 | |
1913 | // .. ==> 0XF8000B6C[0:0] = 0x00000001U | |
1914 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1915 | // .. VREF_SEL = 0x4 | |
1916 | // .. ==> 0XF8000B6C[4:1] = 0x00000004U | |
1917 | // .. ==> MASK : 0x0000001EU VAL : 0x00000008U | |
1918 | // .. VREF_EXT_EN = 0x0 | |
1919 | // .. ==> 0XF8000B6C[6:5] = 0x00000000U | |
1920 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
1921 | // .. reserved_VREF_PULLUP_EN = 0x0 | |
1922 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | |
1923 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | |
1924 | // .. REFIO_EN = 0x1 | |
1925 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | |
1926 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | |
1927 | // .. reserved_REFIO_TEST = 0x3 | |
1928 | // .. ==> 0XF8000B6C[11:10] = 0x00000003U | |
1929 | // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U | |
1930 | // .. reserved_REFIO_PULLUP_EN = 0x0 | |
1931 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | |
1932 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
1933 | // .. reserved_DRST_B_PULLUP_EN = 0x0 | |
1934 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | |
1935 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
1936 | // .. reserved_CKE_PULLUP_EN = 0x0 | |
1937 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | |
1938 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
1939 | // .. | |
1940 | EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), | |
1941 | // .. .. START: ASSERT RESET | |
1942 | // .. .. RESET = 1 | |
1943 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | |
1944 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1945 | // .. .. | |
1946 | EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), | |
1947 | // .. .. FINISH: ASSERT RESET | |
1948 | // .. .. START: DEASSERT RESET | |
1949 | // .. .. RESET = 0 | |
1950 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | |
1951 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
1952 | // .. .. reserved_VRN_OUT = 0x1 | |
1953 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
1954 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
1955 | // .. .. | |
1956 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | |
1957 | // .. .. FINISH: DEASSERT RESET | |
1958 | // .. .. RESET = 0x1 | |
1959 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | |
1960 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
1961 | // .. .. ENABLE = 0x1 | |
1962 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | |
1963 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
1964 | // .. .. reserved_VRP_TRI = 0x0 | |
1965 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | |
1966 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
1967 | // .. .. reserved_VRN_TRI = 0x0 | |
1968 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | |
1969 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
1970 | // .. .. reserved_VRP_OUT = 0x0 | |
1971 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | |
1972 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
1973 | // .. .. reserved_VRN_OUT = 0x1 | |
1974 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
1975 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
1976 | // .. .. NREF_OPT1 = 0x0 | |
1977 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | |
1978 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | |
1979 | // .. .. NREF_OPT2 = 0x0 | |
1980 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | |
1981 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | |
1982 | // .. .. NREF_OPT4 = 0x1 | |
1983 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | |
1984 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | |
1985 | // .. .. PREF_OPT1 = 0x0 | |
1986 | // .. .. ==> 0XF8000B70[15:14] = 0x00000000U | |
1987 | // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U | |
1988 | // .. .. PREF_OPT2 = 0x0 | |
1989 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | |
1990 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | |
1991 | // .. .. UPDATE_CONTROL = 0x0 | |
1992 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | |
1993 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
1994 | // .. .. reserved_INIT_COMPLETE = 0x0 | |
1995 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | |
1996 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
1997 | // .. .. reserved_TST_CLK = 0x0 | |
1998 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | |
1999 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
2000 | // .. .. reserved_TST_HLN = 0x0 | |
2001 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | |
2002 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
2003 | // .. .. reserved_TST_HLP = 0x0 | |
2004 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | |
2005 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
2006 | // .. .. reserved_TST_RST = 0x0 | |
2007 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | |
2008 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
2009 | // .. .. reserved_INT_DCI_EN = 0x0 | |
2010 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | |
2011 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | |
2012 | // .. .. | |
2013 | EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), | |
2014 | // .. FINISH: DDRIOB SETTINGS | |
2015 | // .. START: MIO PROGRAMMING | |
2016 | // .. TRI_ENABLE = 0 | |
2017 | // .. ==> 0XF8000700[0:0] = 0x00000000U | |
2018 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2019 | // .. L0_SEL = 0 | |
2020 | // .. ==> 0XF8000700[1:1] = 0x00000000U | |
2021 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2022 | // .. L1_SEL = 0 | |
2023 | // .. ==> 0XF8000700[2:2] = 0x00000000U | |
2024 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2025 | // .. L2_SEL = 0 | |
2026 | // .. ==> 0XF8000700[4:3] = 0x00000000U | |
2027 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2028 | // .. L3_SEL = 0 | |
2029 | // .. ==> 0XF8000700[7:5] = 0x00000000U | |
2030 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2031 | // .. Speed = 0 | |
2032 | // .. ==> 0XF8000700[8:8] = 0x00000000U | |
2033 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2034 | // .. IO_Type = 3 | |
2035 | // .. ==> 0XF8000700[11:9] = 0x00000003U | |
2036 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2037 | // .. PULLUP = 0 | |
2038 | // .. ==> 0XF8000700[12:12] = 0x00000000U | |
2039 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2040 | // .. DisableRcvr = 0 | |
2041 | // .. ==> 0XF8000700[13:13] = 0x00000000U | |
2042 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2043 | // .. | |
2044 | EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), | |
2045 | // .. TRI_ENABLE = 0 | |
2046 | // .. ==> 0XF8000704[0:0] = 0x00000000U | |
2047 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2048 | // .. L0_SEL = 1 | |
2049 | // .. ==> 0XF8000704[1:1] = 0x00000001U | |
2050 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2051 | // .. L1_SEL = 0 | |
2052 | // .. ==> 0XF8000704[2:2] = 0x00000000U | |
2053 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2054 | // .. L2_SEL = 0 | |
2055 | // .. ==> 0XF8000704[4:3] = 0x00000000U | |
2056 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2057 | // .. L3_SEL = 0 | |
2058 | // .. ==> 0XF8000704[7:5] = 0x00000000U | |
2059 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2060 | // .. Speed = 0 | |
2061 | // .. ==> 0XF8000704[8:8] = 0x00000000U | |
2062 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2063 | // .. IO_Type = 3 | |
2064 | // .. ==> 0XF8000704[11:9] = 0x00000003U | |
2065 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2066 | // .. PULLUP = 0 | |
2067 | // .. ==> 0XF8000704[12:12] = 0x00000000U | |
2068 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2069 | // .. DisableRcvr = 0 | |
2070 | // .. ==> 0XF8000704[13:13] = 0x00000000U | |
2071 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2072 | // .. | |
2073 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), | |
2074 | // .. TRI_ENABLE = 0 | |
2075 | // .. ==> 0XF8000708[0:0] = 0x00000000U | |
2076 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2077 | // .. L0_SEL = 1 | |
2078 | // .. ==> 0XF8000708[1:1] = 0x00000001U | |
2079 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2080 | // .. L1_SEL = 0 | |
2081 | // .. ==> 0XF8000708[2:2] = 0x00000000U | |
2082 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2083 | // .. L2_SEL = 0 | |
2084 | // .. ==> 0XF8000708[4:3] = 0x00000000U | |
2085 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2086 | // .. L3_SEL = 0 | |
2087 | // .. ==> 0XF8000708[7:5] = 0x00000000U | |
2088 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2089 | // .. Speed = 0 | |
2090 | // .. ==> 0XF8000708[8:8] = 0x00000000U | |
2091 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2092 | // .. IO_Type = 3 | |
2093 | // .. ==> 0XF8000708[11:9] = 0x00000003U | |
2094 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2095 | // .. PULLUP = 0 | |
2096 | // .. ==> 0XF8000708[12:12] = 0x00000000U | |
2097 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2098 | // .. DisableRcvr = 0 | |
2099 | // .. ==> 0XF8000708[13:13] = 0x00000000U | |
2100 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2101 | // .. | |
2102 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), | |
2103 | // .. TRI_ENABLE = 0 | |
2104 | // .. ==> 0XF800070C[0:0] = 0x00000000U | |
2105 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2106 | // .. L0_SEL = 1 | |
2107 | // .. ==> 0XF800070C[1:1] = 0x00000001U | |
2108 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2109 | // .. L1_SEL = 0 | |
2110 | // .. ==> 0XF800070C[2:2] = 0x00000000U | |
2111 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2112 | // .. L2_SEL = 0 | |
2113 | // .. ==> 0XF800070C[4:3] = 0x00000000U | |
2114 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2115 | // .. L3_SEL = 0 | |
2116 | // .. ==> 0XF800070C[7:5] = 0x00000000U | |
2117 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2118 | // .. Speed = 0 | |
2119 | // .. ==> 0XF800070C[8:8] = 0x00000000U | |
2120 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2121 | // .. IO_Type = 3 | |
2122 | // .. ==> 0XF800070C[11:9] = 0x00000003U | |
2123 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2124 | // .. PULLUP = 0 | |
2125 | // .. ==> 0XF800070C[12:12] = 0x00000000U | |
2126 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2127 | // .. DisableRcvr = 0 | |
2128 | // .. ==> 0XF800070C[13:13] = 0x00000000U | |
2129 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2130 | // .. | |
2131 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), | |
2132 | // .. TRI_ENABLE = 0 | |
2133 | // .. ==> 0XF8000710[0:0] = 0x00000000U | |
2134 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2135 | // .. L0_SEL = 1 | |
2136 | // .. ==> 0XF8000710[1:1] = 0x00000001U | |
2137 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2138 | // .. L1_SEL = 0 | |
2139 | // .. ==> 0XF8000710[2:2] = 0x00000000U | |
2140 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2141 | // .. L2_SEL = 0 | |
2142 | // .. ==> 0XF8000710[4:3] = 0x00000000U | |
2143 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2144 | // .. L3_SEL = 0 | |
2145 | // .. ==> 0XF8000710[7:5] = 0x00000000U | |
2146 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2147 | // .. Speed = 0 | |
2148 | // .. ==> 0XF8000710[8:8] = 0x00000000U | |
2149 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2150 | // .. IO_Type = 3 | |
2151 | // .. ==> 0XF8000710[11:9] = 0x00000003U | |
2152 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2153 | // .. PULLUP = 0 | |
2154 | // .. ==> 0XF8000710[12:12] = 0x00000000U | |
2155 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2156 | // .. DisableRcvr = 0 | |
2157 | // .. ==> 0XF8000710[13:13] = 0x00000000U | |
2158 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2159 | // .. | |
2160 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), | |
2161 | // .. TRI_ENABLE = 0 | |
2162 | // .. ==> 0XF8000714[0:0] = 0x00000000U | |
2163 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2164 | // .. L0_SEL = 1 | |
2165 | // .. ==> 0XF8000714[1:1] = 0x00000001U | |
2166 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2167 | // .. L1_SEL = 0 | |
2168 | // .. ==> 0XF8000714[2:2] = 0x00000000U | |
2169 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2170 | // .. L2_SEL = 0 | |
2171 | // .. ==> 0XF8000714[4:3] = 0x00000000U | |
2172 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2173 | // .. L3_SEL = 0 | |
2174 | // .. ==> 0XF8000714[7:5] = 0x00000000U | |
2175 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2176 | // .. Speed = 0 | |
2177 | // .. ==> 0XF8000714[8:8] = 0x00000000U | |
2178 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2179 | // .. IO_Type = 3 | |
2180 | // .. ==> 0XF8000714[11:9] = 0x00000003U | |
2181 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2182 | // .. PULLUP = 0 | |
2183 | // .. ==> 0XF8000714[12:12] = 0x00000000U | |
2184 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2185 | // .. DisableRcvr = 0 | |
2186 | // .. ==> 0XF8000714[13:13] = 0x00000000U | |
2187 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2188 | // .. | |
2189 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), | |
2190 | // .. TRI_ENABLE = 0 | |
2191 | // .. ==> 0XF8000718[0:0] = 0x00000000U | |
2192 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2193 | // .. L0_SEL = 1 | |
2194 | // .. ==> 0XF8000718[1:1] = 0x00000001U | |
2195 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2196 | // .. L1_SEL = 0 | |
2197 | // .. ==> 0XF8000718[2:2] = 0x00000000U | |
2198 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2199 | // .. L2_SEL = 0 | |
2200 | // .. ==> 0XF8000718[4:3] = 0x00000000U | |
2201 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2202 | // .. L3_SEL = 0 | |
2203 | // .. ==> 0XF8000718[7:5] = 0x00000000U | |
2204 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2205 | // .. Speed = 0 | |
2206 | // .. ==> 0XF8000718[8:8] = 0x00000000U | |
2207 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2208 | // .. IO_Type = 3 | |
2209 | // .. ==> 0XF8000718[11:9] = 0x00000003U | |
2210 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2211 | // .. PULLUP = 0 | |
2212 | // .. ==> 0XF8000718[12:12] = 0x00000000U | |
2213 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2214 | // .. DisableRcvr = 0 | |
2215 | // .. ==> 0XF8000718[13:13] = 0x00000000U | |
2216 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2217 | // .. | |
2218 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), | |
2219 | // .. TRI_ENABLE = 0 | |
2220 | // .. ==> 0XF800071C[0:0] = 0x00000000U | |
2221 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2222 | // .. L0_SEL = 0 | |
2223 | // .. ==> 0XF800071C[1:1] = 0x00000000U | |
2224 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2225 | // .. L1_SEL = 0 | |
2226 | // .. ==> 0XF800071C[2:2] = 0x00000000U | |
2227 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2228 | // .. L2_SEL = 0 | |
2229 | // .. ==> 0XF800071C[4:3] = 0x00000000U | |
2230 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2231 | // .. L3_SEL = 0 | |
2232 | // .. ==> 0XF800071C[7:5] = 0x00000000U | |
2233 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2234 | // .. Speed = 0 | |
2235 | // .. ==> 0XF800071C[8:8] = 0x00000000U | |
2236 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2237 | // .. IO_Type = 3 | |
2238 | // .. ==> 0XF800071C[11:9] = 0x00000003U | |
2239 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2240 | // .. PULLUP = 0 | |
2241 | // .. ==> 0XF800071C[12:12] = 0x00000000U | |
2242 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2243 | // .. DisableRcvr = 0 | |
2244 | // .. ==> 0XF800071C[13:13] = 0x00000000U | |
2245 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2246 | // .. | |
2247 | EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), | |
2248 | // .. TRI_ENABLE = 0 | |
2249 | // .. ==> 0XF8000720[0:0] = 0x00000000U | |
2250 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2251 | // .. L0_SEL = 1 | |
2252 | // .. ==> 0XF8000720[1:1] = 0x00000001U | |
2253 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2254 | // .. L1_SEL = 0 | |
2255 | // .. ==> 0XF8000720[2:2] = 0x00000000U | |
2256 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2257 | // .. L2_SEL = 0 | |
2258 | // .. ==> 0XF8000720[4:3] = 0x00000000U | |
2259 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2260 | // .. L3_SEL = 0 | |
2261 | // .. ==> 0XF8000720[7:5] = 0x00000000U | |
2262 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2263 | // .. Speed = 0 | |
2264 | // .. ==> 0XF8000720[8:8] = 0x00000000U | |
2265 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2266 | // .. IO_Type = 3 | |
2267 | // .. ==> 0XF8000720[11:9] = 0x00000003U | |
2268 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2269 | // .. PULLUP = 0 | |
2270 | // .. ==> 0XF8000720[12:12] = 0x00000000U | |
2271 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2272 | // .. DisableRcvr = 0 | |
2273 | // .. ==> 0XF8000720[13:13] = 0x00000000U | |
2274 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2275 | // .. | |
2276 | EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), | |
2277 | // .. TRI_ENABLE = 0 | |
2278 | // .. ==> 0XF8000724[0:0] = 0x00000000U | |
2279 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2280 | // .. L0_SEL = 0 | |
2281 | // .. ==> 0XF8000724[1:1] = 0x00000000U | |
2282 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2283 | // .. L1_SEL = 0 | |
2284 | // .. ==> 0XF8000724[2:2] = 0x00000000U | |
2285 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2286 | // .. L2_SEL = 0 | |
2287 | // .. ==> 0XF8000724[4:3] = 0x00000000U | |
2288 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2289 | // .. L3_SEL = 0 | |
2290 | // .. ==> 0XF8000724[7:5] = 0x00000000U | |
2291 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2292 | // .. Speed = 0 | |
2293 | // .. ==> 0XF8000724[8:8] = 0x00000000U | |
2294 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2295 | // .. IO_Type = 3 | |
2296 | // .. ==> 0XF8000724[11:9] = 0x00000003U | |
2297 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2298 | // .. PULLUP = 0 | |
2299 | // .. ==> 0XF8000724[12:12] = 0x00000000U | |
2300 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2301 | // .. DisableRcvr = 0 | |
2302 | // .. ==> 0XF8000724[13:13] = 0x00000000U | |
2303 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2304 | // .. | |
2305 | EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), | |
2306 | // .. TRI_ENABLE = 0 | |
2307 | // .. ==> 0XF8000728[0:0] = 0x00000000U | |
2308 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2309 | // .. L0_SEL = 0 | |
2310 | // .. ==> 0XF8000728[1:1] = 0x00000000U | |
2311 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2312 | // .. L1_SEL = 0 | |
2313 | // .. ==> 0XF8000728[2:2] = 0x00000000U | |
2314 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2315 | // .. L2_SEL = 0 | |
2316 | // .. ==> 0XF8000728[4:3] = 0x00000000U | |
2317 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2318 | // .. L3_SEL = 0 | |
2319 | // .. ==> 0XF8000728[7:5] = 0x00000000U | |
2320 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2321 | // .. Speed = 0 | |
2322 | // .. ==> 0XF8000728[8:8] = 0x00000000U | |
2323 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2324 | // .. IO_Type = 3 | |
2325 | // .. ==> 0XF8000728[11:9] = 0x00000003U | |
2326 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2327 | // .. PULLUP = 0 | |
2328 | // .. ==> 0XF8000728[12:12] = 0x00000000U | |
2329 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2330 | // .. DisableRcvr = 0 | |
2331 | // .. ==> 0XF8000728[13:13] = 0x00000000U | |
2332 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2333 | // .. | |
2334 | EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), | |
2335 | // .. TRI_ENABLE = 0 | |
2336 | // .. ==> 0XF800072C[0:0] = 0x00000000U | |
2337 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2338 | // .. L0_SEL = 0 | |
2339 | // .. ==> 0XF800072C[1:1] = 0x00000000U | |
2340 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2341 | // .. L1_SEL = 0 | |
2342 | // .. ==> 0XF800072C[2:2] = 0x00000000U | |
2343 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2344 | // .. L2_SEL = 0 | |
2345 | // .. ==> 0XF800072C[4:3] = 0x00000000U | |
2346 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2347 | // .. L3_SEL = 0 | |
2348 | // .. ==> 0XF800072C[7:5] = 0x00000000U | |
2349 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2350 | // .. Speed = 0 | |
2351 | // .. ==> 0XF800072C[8:8] = 0x00000000U | |
2352 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2353 | // .. IO_Type = 3 | |
2354 | // .. ==> 0XF800072C[11:9] = 0x00000003U | |
2355 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2356 | // .. PULLUP = 0 | |
2357 | // .. ==> 0XF800072C[12:12] = 0x00000000U | |
2358 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2359 | // .. DisableRcvr = 0 | |
2360 | // .. ==> 0XF800072C[13:13] = 0x00000000U | |
2361 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2362 | // .. | |
2363 | EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), | |
2364 | // .. TRI_ENABLE = 0 | |
2365 | // .. ==> 0XF8000730[0:0] = 0x00000000U | |
2366 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2367 | // .. L0_SEL = 0 | |
2368 | // .. ==> 0XF8000730[1:1] = 0x00000000U | |
2369 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2370 | // .. L1_SEL = 0 | |
2371 | // .. ==> 0XF8000730[2:2] = 0x00000000U | |
2372 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2373 | // .. L2_SEL = 0 | |
2374 | // .. ==> 0XF8000730[4:3] = 0x00000000U | |
2375 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2376 | // .. L3_SEL = 0 | |
2377 | // .. ==> 0XF8000730[7:5] = 0x00000000U | |
2378 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2379 | // .. Speed = 0 | |
2380 | // .. ==> 0XF8000730[8:8] = 0x00000000U | |
2381 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2382 | // .. IO_Type = 3 | |
2383 | // .. ==> 0XF8000730[11:9] = 0x00000003U | |
2384 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2385 | // .. PULLUP = 0 | |
2386 | // .. ==> 0XF8000730[12:12] = 0x00000000U | |
2387 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2388 | // .. DisableRcvr = 0 | |
2389 | // .. ==> 0XF8000730[13:13] = 0x00000000U | |
2390 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2391 | // .. | |
2392 | EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), | |
2393 | // .. TRI_ENABLE = 0 | |
2394 | // .. ==> 0XF8000734[0:0] = 0x00000000U | |
2395 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2396 | // .. L0_SEL = 0 | |
2397 | // .. ==> 0XF8000734[1:1] = 0x00000000U | |
2398 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2399 | // .. L1_SEL = 0 | |
2400 | // .. ==> 0XF8000734[2:2] = 0x00000000U | |
2401 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2402 | // .. L2_SEL = 0 | |
2403 | // .. ==> 0XF8000734[4:3] = 0x00000000U | |
2404 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2405 | // .. L3_SEL = 0 | |
2406 | // .. ==> 0XF8000734[7:5] = 0x00000000U | |
2407 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2408 | // .. Speed = 0 | |
2409 | // .. ==> 0XF8000734[8:8] = 0x00000000U | |
2410 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2411 | // .. IO_Type = 3 | |
2412 | // .. ==> 0XF8000734[11:9] = 0x00000003U | |
2413 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2414 | // .. PULLUP = 0 | |
2415 | // .. ==> 0XF8000734[12:12] = 0x00000000U | |
2416 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2417 | // .. DisableRcvr = 0 | |
2418 | // .. ==> 0XF8000734[13:13] = 0x00000000U | |
2419 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2420 | // .. | |
2421 | EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), | |
2422 | // .. TRI_ENABLE = 0 | |
2423 | // .. ==> 0XF8000738[0:0] = 0x00000000U | |
2424 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2425 | // .. L0_SEL = 0 | |
2426 | // .. ==> 0XF8000738[1:1] = 0x00000000U | |
2427 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2428 | // .. L1_SEL = 0 | |
2429 | // .. ==> 0XF8000738[2:2] = 0x00000000U | |
2430 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2431 | // .. L2_SEL = 0 | |
2432 | // .. ==> 0XF8000738[4:3] = 0x00000000U | |
2433 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2434 | // .. L3_SEL = 0 | |
2435 | // .. ==> 0XF8000738[7:5] = 0x00000000U | |
2436 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2437 | // .. Speed = 0 | |
2438 | // .. ==> 0XF8000738[8:8] = 0x00000000U | |
2439 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2440 | // .. IO_Type = 3 | |
2441 | // .. ==> 0XF8000738[11:9] = 0x00000003U | |
2442 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2443 | // .. PULLUP = 0 | |
2444 | // .. ==> 0XF8000738[12:12] = 0x00000000U | |
2445 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2446 | // .. DisableRcvr = 0 | |
2447 | // .. ==> 0XF8000738[13:13] = 0x00000000U | |
2448 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2449 | // .. | |
2450 | EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), | |
2451 | // .. TRI_ENABLE = 0 | |
2452 | // .. ==> 0XF800073C[0:0] = 0x00000000U | |
2453 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2454 | // .. L0_SEL = 0 | |
2455 | // .. ==> 0XF800073C[1:1] = 0x00000000U | |
2456 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2457 | // .. L1_SEL = 0 | |
2458 | // .. ==> 0XF800073C[2:2] = 0x00000000U | |
2459 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2460 | // .. L2_SEL = 0 | |
2461 | // .. ==> 0XF800073C[4:3] = 0x00000000U | |
2462 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2463 | // .. L3_SEL = 0 | |
2464 | // .. ==> 0XF800073C[7:5] = 0x00000000U | |
2465 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2466 | // .. Speed = 0 | |
2467 | // .. ==> 0XF800073C[8:8] = 0x00000000U | |
2468 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2469 | // .. IO_Type = 3 | |
2470 | // .. ==> 0XF800073C[11:9] = 0x00000003U | |
2471 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
2472 | // .. PULLUP = 0 | |
2473 | // .. ==> 0XF800073C[12:12] = 0x00000000U | |
2474 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2475 | // .. DisableRcvr = 0 | |
2476 | // .. ==> 0XF800073C[13:13] = 0x00000000U | |
2477 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2478 | // .. | |
2479 | EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), | |
2480 | // .. TRI_ENABLE = 0 | |
2481 | // .. ==> 0XF8000740[0:0] = 0x00000000U | |
2482 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2483 | // .. L0_SEL = 1 | |
2484 | // .. ==> 0XF8000740[1:1] = 0x00000001U | |
2485 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2486 | // .. L1_SEL = 0 | |
2487 | // .. ==> 0XF8000740[2:2] = 0x00000000U | |
2488 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2489 | // .. L2_SEL = 0 | |
2490 | // .. ==> 0XF8000740[4:3] = 0x00000000U | |
2491 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2492 | // .. L3_SEL = 0 | |
2493 | // .. ==> 0XF8000740[7:5] = 0x00000000U | |
2494 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2495 | // .. Speed = 0 | |
2496 | // .. ==> 0XF8000740[8:8] = 0x00000000U | |
2497 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2498 | // .. IO_Type = 1 | |
2499 | // .. ==> 0XF8000740[11:9] = 0x00000001U | |
2500 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2501 | // .. PULLUP = 0 | |
2502 | // .. ==> 0XF8000740[12:12] = 0x00000000U | |
2503 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2504 | // .. DisableRcvr = 0 | |
2505 | // .. ==> 0XF8000740[13:13] = 0x00000000U | |
2506 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2507 | // .. | |
2508 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), | |
2509 | // .. TRI_ENABLE = 0 | |
2510 | // .. ==> 0XF8000744[0:0] = 0x00000000U | |
2511 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2512 | // .. L0_SEL = 1 | |
2513 | // .. ==> 0XF8000744[1:1] = 0x00000001U | |
2514 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2515 | // .. L1_SEL = 0 | |
2516 | // .. ==> 0XF8000744[2:2] = 0x00000000U | |
2517 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2518 | // .. L2_SEL = 0 | |
2519 | // .. ==> 0XF8000744[4:3] = 0x00000000U | |
2520 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2521 | // .. L3_SEL = 0 | |
2522 | // .. ==> 0XF8000744[7:5] = 0x00000000U | |
2523 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2524 | // .. Speed = 0 | |
2525 | // .. ==> 0XF8000744[8:8] = 0x00000000U | |
2526 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2527 | // .. IO_Type = 1 | |
2528 | // .. ==> 0XF8000744[11:9] = 0x00000001U | |
2529 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2530 | // .. PULLUP = 0 | |
2531 | // .. ==> 0XF8000744[12:12] = 0x00000000U | |
2532 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2533 | // .. DisableRcvr = 0 | |
2534 | // .. ==> 0XF8000744[13:13] = 0x00000000U | |
2535 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2536 | // .. | |
2537 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), | |
2538 | // .. TRI_ENABLE = 0 | |
2539 | // .. ==> 0XF8000748[0:0] = 0x00000000U | |
2540 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2541 | // .. L0_SEL = 1 | |
2542 | // .. ==> 0XF8000748[1:1] = 0x00000001U | |
2543 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2544 | // .. L1_SEL = 0 | |
2545 | // .. ==> 0XF8000748[2:2] = 0x00000000U | |
2546 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2547 | // .. L2_SEL = 0 | |
2548 | // .. ==> 0XF8000748[4:3] = 0x00000000U | |
2549 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2550 | // .. L3_SEL = 0 | |
2551 | // .. ==> 0XF8000748[7:5] = 0x00000000U | |
2552 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2553 | // .. Speed = 0 | |
2554 | // .. ==> 0XF8000748[8:8] = 0x00000000U | |
2555 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2556 | // .. IO_Type = 1 | |
2557 | // .. ==> 0XF8000748[11:9] = 0x00000001U | |
2558 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2559 | // .. PULLUP = 0 | |
2560 | // .. ==> 0XF8000748[12:12] = 0x00000000U | |
2561 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2562 | // .. DisableRcvr = 0 | |
2563 | // .. ==> 0XF8000748[13:13] = 0x00000000U | |
2564 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2565 | // .. | |
2566 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), | |
2567 | // .. TRI_ENABLE = 0 | |
2568 | // .. ==> 0XF800074C[0:0] = 0x00000000U | |
2569 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2570 | // .. L0_SEL = 1 | |
2571 | // .. ==> 0XF800074C[1:1] = 0x00000001U | |
2572 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2573 | // .. L1_SEL = 0 | |
2574 | // .. ==> 0XF800074C[2:2] = 0x00000000U | |
2575 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2576 | // .. L2_SEL = 0 | |
2577 | // .. ==> 0XF800074C[4:3] = 0x00000000U | |
2578 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2579 | // .. L3_SEL = 0 | |
2580 | // .. ==> 0XF800074C[7:5] = 0x00000000U | |
2581 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2582 | // .. Speed = 0 | |
2583 | // .. ==> 0XF800074C[8:8] = 0x00000000U | |
2584 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2585 | // .. IO_Type = 1 | |
2586 | // .. ==> 0XF800074C[11:9] = 0x00000001U | |
2587 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2588 | // .. PULLUP = 0 | |
2589 | // .. ==> 0XF800074C[12:12] = 0x00000000U | |
2590 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2591 | // .. DisableRcvr = 0 | |
2592 | // .. ==> 0XF800074C[13:13] = 0x00000000U | |
2593 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2594 | // .. | |
2595 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), | |
2596 | // .. TRI_ENABLE = 0 | |
2597 | // .. ==> 0XF8000750[0:0] = 0x00000000U | |
2598 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2599 | // .. L0_SEL = 1 | |
2600 | // .. ==> 0XF8000750[1:1] = 0x00000001U | |
2601 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2602 | // .. L1_SEL = 0 | |
2603 | // .. ==> 0XF8000750[2:2] = 0x00000000U | |
2604 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2605 | // .. L2_SEL = 0 | |
2606 | // .. ==> 0XF8000750[4:3] = 0x00000000U | |
2607 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2608 | // .. L3_SEL = 0 | |
2609 | // .. ==> 0XF8000750[7:5] = 0x00000000U | |
2610 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2611 | // .. Speed = 0 | |
2612 | // .. ==> 0XF8000750[8:8] = 0x00000000U | |
2613 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2614 | // .. IO_Type = 1 | |
2615 | // .. ==> 0XF8000750[11:9] = 0x00000001U | |
2616 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2617 | // .. PULLUP = 0 | |
2618 | // .. ==> 0XF8000750[12:12] = 0x00000000U | |
2619 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2620 | // .. DisableRcvr = 0 | |
2621 | // .. ==> 0XF8000750[13:13] = 0x00000000U | |
2622 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2623 | // .. | |
2624 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), | |
2625 | // .. TRI_ENABLE = 0 | |
2626 | // .. ==> 0XF8000754[0:0] = 0x00000000U | |
2627 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2628 | // .. L0_SEL = 1 | |
2629 | // .. ==> 0XF8000754[1:1] = 0x00000001U | |
2630 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2631 | // .. L1_SEL = 0 | |
2632 | // .. ==> 0XF8000754[2:2] = 0x00000000U | |
2633 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2634 | // .. L2_SEL = 0 | |
2635 | // .. ==> 0XF8000754[4:3] = 0x00000000U | |
2636 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2637 | // .. L3_SEL = 0 | |
2638 | // .. ==> 0XF8000754[7:5] = 0x00000000U | |
2639 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2640 | // .. Speed = 0 | |
2641 | // .. ==> 0XF8000754[8:8] = 0x00000000U | |
2642 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2643 | // .. IO_Type = 1 | |
2644 | // .. ==> 0XF8000754[11:9] = 0x00000001U | |
2645 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2646 | // .. PULLUP = 0 | |
2647 | // .. ==> 0XF8000754[12:12] = 0x00000000U | |
2648 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2649 | // .. DisableRcvr = 0 | |
2650 | // .. ==> 0XF8000754[13:13] = 0x00000000U | |
2651 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2652 | // .. | |
2653 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), | |
2654 | // .. TRI_ENABLE = 1 | |
2655 | // .. ==> 0XF8000758[0:0] = 0x00000001U | |
2656 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2657 | // .. L0_SEL = 1 | |
2658 | // .. ==> 0XF8000758[1:1] = 0x00000001U | |
2659 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2660 | // .. L1_SEL = 0 | |
2661 | // .. ==> 0XF8000758[2:2] = 0x00000000U | |
2662 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2663 | // .. L2_SEL = 0 | |
2664 | // .. ==> 0XF8000758[4:3] = 0x00000000U | |
2665 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2666 | // .. L3_SEL = 0 | |
2667 | // .. ==> 0XF8000758[7:5] = 0x00000000U | |
2668 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2669 | // .. Speed = 0 | |
2670 | // .. ==> 0XF8000758[8:8] = 0x00000000U | |
2671 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2672 | // .. IO_Type = 1 | |
2673 | // .. ==> 0XF8000758[11:9] = 0x00000001U | |
2674 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2675 | // .. PULLUP = 0 | |
2676 | // .. ==> 0XF8000758[12:12] = 0x00000000U | |
2677 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2678 | // .. DisableRcvr = 0 | |
2679 | // .. ==> 0XF8000758[13:13] = 0x00000000U | |
2680 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2681 | // .. | |
2682 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), | |
2683 | // .. TRI_ENABLE = 1 | |
2684 | // .. ==> 0XF800075C[0:0] = 0x00000001U | |
2685 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2686 | // .. L0_SEL = 1 | |
2687 | // .. ==> 0XF800075C[1:1] = 0x00000001U | |
2688 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2689 | // .. L1_SEL = 0 | |
2690 | // .. ==> 0XF800075C[2:2] = 0x00000000U | |
2691 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2692 | // .. L2_SEL = 0 | |
2693 | // .. ==> 0XF800075C[4:3] = 0x00000000U | |
2694 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2695 | // .. L3_SEL = 0 | |
2696 | // .. ==> 0XF800075C[7:5] = 0x00000000U | |
2697 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2698 | // .. Speed = 0 | |
2699 | // .. ==> 0XF800075C[8:8] = 0x00000000U | |
2700 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2701 | // .. IO_Type = 1 | |
2702 | // .. ==> 0XF800075C[11:9] = 0x00000001U | |
2703 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2704 | // .. PULLUP = 0 | |
2705 | // .. ==> 0XF800075C[12:12] = 0x00000000U | |
2706 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2707 | // .. DisableRcvr = 0 | |
2708 | // .. ==> 0XF800075C[13:13] = 0x00000000U | |
2709 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2710 | // .. | |
2711 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), | |
2712 | // .. TRI_ENABLE = 1 | |
2713 | // .. ==> 0XF8000760[0:0] = 0x00000001U | |
2714 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2715 | // .. L0_SEL = 1 | |
2716 | // .. ==> 0XF8000760[1:1] = 0x00000001U | |
2717 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2718 | // .. L1_SEL = 0 | |
2719 | // .. ==> 0XF8000760[2:2] = 0x00000000U | |
2720 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2721 | // .. L2_SEL = 0 | |
2722 | // .. ==> 0XF8000760[4:3] = 0x00000000U | |
2723 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2724 | // .. L3_SEL = 0 | |
2725 | // .. ==> 0XF8000760[7:5] = 0x00000000U | |
2726 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2727 | // .. Speed = 0 | |
2728 | // .. ==> 0XF8000760[8:8] = 0x00000000U | |
2729 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2730 | // .. IO_Type = 1 | |
2731 | // .. ==> 0XF8000760[11:9] = 0x00000001U | |
2732 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2733 | // .. PULLUP = 0 | |
2734 | // .. ==> 0XF8000760[12:12] = 0x00000000U | |
2735 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2736 | // .. DisableRcvr = 0 | |
2737 | // .. ==> 0XF8000760[13:13] = 0x00000000U | |
2738 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2739 | // .. | |
2740 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), | |
2741 | // .. TRI_ENABLE = 1 | |
2742 | // .. ==> 0XF8000764[0:0] = 0x00000001U | |
2743 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2744 | // .. L0_SEL = 1 | |
2745 | // .. ==> 0XF8000764[1:1] = 0x00000001U | |
2746 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2747 | // .. L1_SEL = 0 | |
2748 | // .. ==> 0XF8000764[2:2] = 0x00000000U | |
2749 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2750 | // .. L2_SEL = 0 | |
2751 | // .. ==> 0XF8000764[4:3] = 0x00000000U | |
2752 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2753 | // .. L3_SEL = 0 | |
2754 | // .. ==> 0XF8000764[7:5] = 0x00000000U | |
2755 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2756 | // .. Speed = 0 | |
2757 | // .. ==> 0XF8000764[8:8] = 0x00000000U | |
2758 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2759 | // .. IO_Type = 1 | |
2760 | // .. ==> 0XF8000764[11:9] = 0x00000001U | |
2761 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2762 | // .. PULLUP = 0 | |
2763 | // .. ==> 0XF8000764[12:12] = 0x00000000U | |
2764 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2765 | // .. DisableRcvr = 0 | |
2766 | // .. ==> 0XF8000764[13:13] = 0x00000000U | |
2767 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2768 | // .. | |
2769 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), | |
2770 | // .. TRI_ENABLE = 1 | |
2771 | // .. ==> 0XF8000768[0:0] = 0x00000001U | |
2772 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2773 | // .. L0_SEL = 1 | |
2774 | // .. ==> 0XF8000768[1:1] = 0x00000001U | |
2775 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2776 | // .. L1_SEL = 0 | |
2777 | // .. ==> 0XF8000768[2:2] = 0x00000000U | |
2778 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2779 | // .. L2_SEL = 0 | |
2780 | // .. ==> 0XF8000768[4:3] = 0x00000000U | |
2781 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2782 | // .. L3_SEL = 0 | |
2783 | // .. ==> 0XF8000768[7:5] = 0x00000000U | |
2784 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2785 | // .. Speed = 0 | |
2786 | // .. ==> 0XF8000768[8:8] = 0x00000000U | |
2787 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2788 | // .. IO_Type = 1 | |
2789 | // .. ==> 0XF8000768[11:9] = 0x00000001U | |
2790 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2791 | // .. PULLUP = 0 | |
2792 | // .. ==> 0XF8000768[12:12] = 0x00000000U | |
2793 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2794 | // .. DisableRcvr = 0 | |
2795 | // .. ==> 0XF8000768[13:13] = 0x00000000U | |
2796 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2797 | // .. | |
2798 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), | |
2799 | // .. TRI_ENABLE = 1 | |
2800 | // .. ==> 0XF800076C[0:0] = 0x00000001U | |
2801 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2802 | // .. L0_SEL = 1 | |
2803 | // .. ==> 0XF800076C[1:1] = 0x00000001U | |
2804 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
2805 | // .. L1_SEL = 0 | |
2806 | // .. ==> 0XF800076C[2:2] = 0x00000000U | |
2807 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
2808 | // .. L2_SEL = 0 | |
2809 | // .. ==> 0XF800076C[4:3] = 0x00000000U | |
2810 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2811 | // .. L3_SEL = 0 | |
2812 | // .. ==> 0XF800076C[7:5] = 0x00000000U | |
2813 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2814 | // .. Speed = 0 | |
2815 | // .. ==> 0XF800076C[8:8] = 0x00000000U | |
2816 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2817 | // .. IO_Type = 1 | |
2818 | // .. ==> 0XF800076C[11:9] = 0x00000001U | |
2819 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2820 | // .. PULLUP = 0 | |
2821 | // .. ==> 0XF800076C[12:12] = 0x00000000U | |
2822 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2823 | // .. DisableRcvr = 0 | |
2824 | // .. ==> 0XF800076C[13:13] = 0x00000000U | |
2825 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2826 | // .. | |
2827 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), | |
2828 | // .. TRI_ENABLE = 0 | |
2829 | // .. ==> 0XF8000770[0:0] = 0x00000000U | |
2830 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2831 | // .. L0_SEL = 0 | |
2832 | // .. ==> 0XF8000770[1:1] = 0x00000000U | |
2833 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2834 | // .. L1_SEL = 1 | |
2835 | // .. ==> 0XF8000770[2:2] = 0x00000001U | |
2836 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
2837 | // .. L2_SEL = 0 | |
2838 | // .. ==> 0XF8000770[4:3] = 0x00000000U | |
2839 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2840 | // .. L3_SEL = 0 | |
2841 | // .. ==> 0XF8000770[7:5] = 0x00000000U | |
2842 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2843 | // .. Speed = 0 | |
2844 | // .. ==> 0XF8000770[8:8] = 0x00000000U | |
2845 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2846 | // .. IO_Type = 1 | |
2847 | // .. ==> 0XF8000770[11:9] = 0x00000001U | |
2848 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2849 | // .. PULLUP = 0 | |
2850 | // .. ==> 0XF8000770[12:12] = 0x00000000U | |
2851 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2852 | // .. DisableRcvr = 0 | |
2853 | // .. ==> 0XF8000770[13:13] = 0x00000000U | |
2854 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2855 | // .. | |
2856 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), | |
2857 | // .. TRI_ENABLE = 1 | |
2858 | // .. ==> 0XF8000774[0:0] = 0x00000001U | |
2859 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2860 | // .. L0_SEL = 0 | |
2861 | // .. ==> 0XF8000774[1:1] = 0x00000000U | |
2862 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2863 | // .. L1_SEL = 1 | |
2864 | // .. ==> 0XF8000774[2:2] = 0x00000001U | |
2865 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
2866 | // .. L2_SEL = 0 | |
2867 | // .. ==> 0XF8000774[4:3] = 0x00000000U | |
2868 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2869 | // .. L3_SEL = 0 | |
2870 | // .. ==> 0XF8000774[7:5] = 0x00000000U | |
2871 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2872 | // .. Speed = 0 | |
2873 | // .. ==> 0XF8000774[8:8] = 0x00000000U | |
2874 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2875 | // .. IO_Type = 1 | |
2876 | // .. ==> 0XF8000774[11:9] = 0x00000001U | |
2877 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2878 | // .. PULLUP = 0 | |
2879 | // .. ==> 0XF8000774[12:12] = 0x00000000U | |
2880 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2881 | // .. DisableRcvr = 0 | |
2882 | // .. ==> 0XF8000774[13:13] = 0x00000000U | |
2883 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2884 | // .. | |
2885 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), | |
2886 | // .. TRI_ENABLE = 0 | |
2887 | // .. ==> 0XF8000778[0:0] = 0x00000000U | |
2888 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2889 | // .. L0_SEL = 0 | |
2890 | // .. ==> 0XF8000778[1:1] = 0x00000000U | |
2891 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2892 | // .. L1_SEL = 1 | |
2893 | // .. ==> 0XF8000778[2:2] = 0x00000001U | |
2894 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
2895 | // .. L2_SEL = 0 | |
2896 | // .. ==> 0XF8000778[4:3] = 0x00000000U | |
2897 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2898 | // .. L3_SEL = 0 | |
2899 | // .. ==> 0XF8000778[7:5] = 0x00000000U | |
2900 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2901 | // .. Speed = 0 | |
2902 | // .. ==> 0XF8000778[8:8] = 0x00000000U | |
2903 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2904 | // .. IO_Type = 1 | |
2905 | // .. ==> 0XF8000778[11:9] = 0x00000001U | |
2906 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2907 | // .. PULLUP = 0 | |
2908 | // .. ==> 0XF8000778[12:12] = 0x00000000U | |
2909 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2910 | // .. DisableRcvr = 0 | |
2911 | // .. ==> 0XF8000778[13:13] = 0x00000000U | |
2912 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2913 | // .. | |
2914 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), | |
2915 | // .. TRI_ENABLE = 1 | |
2916 | // .. ==> 0XF800077C[0:0] = 0x00000001U | |
2917 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
2918 | // .. L0_SEL = 0 | |
2919 | // .. ==> 0XF800077C[1:1] = 0x00000000U | |
2920 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2921 | // .. L1_SEL = 1 | |
2922 | // .. ==> 0XF800077C[2:2] = 0x00000001U | |
2923 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
2924 | // .. L2_SEL = 0 | |
2925 | // .. ==> 0XF800077C[4:3] = 0x00000000U | |
2926 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2927 | // .. L3_SEL = 0 | |
2928 | // .. ==> 0XF800077C[7:5] = 0x00000000U | |
2929 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2930 | // .. Speed = 0 | |
2931 | // .. ==> 0XF800077C[8:8] = 0x00000000U | |
2932 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2933 | // .. IO_Type = 1 | |
2934 | // .. ==> 0XF800077C[11:9] = 0x00000001U | |
2935 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2936 | // .. PULLUP = 0 | |
2937 | // .. ==> 0XF800077C[12:12] = 0x00000000U | |
2938 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2939 | // .. DisableRcvr = 0 | |
2940 | // .. ==> 0XF800077C[13:13] = 0x00000000U | |
2941 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2942 | // .. | |
2943 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), | |
2944 | // .. TRI_ENABLE = 0 | |
2945 | // .. ==> 0XF8000780[0:0] = 0x00000000U | |
2946 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2947 | // .. L0_SEL = 0 | |
2948 | // .. ==> 0XF8000780[1:1] = 0x00000000U | |
2949 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2950 | // .. L1_SEL = 1 | |
2951 | // .. ==> 0XF8000780[2:2] = 0x00000001U | |
2952 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
2953 | // .. L2_SEL = 0 | |
2954 | // .. ==> 0XF8000780[4:3] = 0x00000000U | |
2955 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2956 | // .. L3_SEL = 0 | |
2957 | // .. ==> 0XF8000780[7:5] = 0x00000000U | |
2958 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2959 | // .. Speed = 0 | |
2960 | // .. ==> 0XF8000780[8:8] = 0x00000000U | |
2961 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2962 | // .. IO_Type = 1 | |
2963 | // .. ==> 0XF8000780[11:9] = 0x00000001U | |
2964 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2965 | // .. PULLUP = 0 | |
2966 | // .. ==> 0XF8000780[12:12] = 0x00000000U | |
2967 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2968 | // .. DisableRcvr = 0 | |
2969 | // .. ==> 0XF8000780[13:13] = 0x00000000U | |
2970 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
2971 | // .. | |
2972 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), | |
2973 | // .. TRI_ENABLE = 0 | |
2974 | // .. ==> 0XF8000784[0:0] = 0x00000000U | |
2975 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
2976 | // .. L0_SEL = 0 | |
2977 | // .. ==> 0XF8000784[1:1] = 0x00000000U | |
2978 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
2979 | // .. L1_SEL = 1 | |
2980 | // .. ==> 0XF8000784[2:2] = 0x00000001U | |
2981 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
2982 | // .. L2_SEL = 0 | |
2983 | // .. ==> 0XF8000784[4:3] = 0x00000000U | |
2984 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
2985 | // .. L3_SEL = 0 | |
2986 | // .. ==> 0XF8000784[7:5] = 0x00000000U | |
2987 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
2988 | // .. Speed = 0 | |
2989 | // .. ==> 0XF8000784[8:8] = 0x00000000U | |
2990 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
2991 | // .. IO_Type = 1 | |
2992 | // .. ==> 0XF8000784[11:9] = 0x00000001U | |
2993 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
2994 | // .. PULLUP = 0 | |
2995 | // .. ==> 0XF8000784[12:12] = 0x00000000U | |
2996 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
2997 | // .. DisableRcvr = 0 | |
2998 | // .. ==> 0XF8000784[13:13] = 0x00000000U | |
2999 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3000 | // .. | |
3001 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), | |
3002 | // .. TRI_ENABLE = 0 | |
3003 | // .. ==> 0XF8000788[0:0] = 0x00000000U | |
3004 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3005 | // .. L0_SEL = 0 | |
3006 | // .. ==> 0XF8000788[1:1] = 0x00000000U | |
3007 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3008 | // .. L1_SEL = 1 | |
3009 | // .. ==> 0XF8000788[2:2] = 0x00000001U | |
3010 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3011 | // .. L2_SEL = 0 | |
3012 | // .. ==> 0XF8000788[4:3] = 0x00000000U | |
3013 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3014 | // .. L3_SEL = 0 | |
3015 | // .. ==> 0XF8000788[7:5] = 0x00000000U | |
3016 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3017 | // .. Speed = 0 | |
3018 | // .. ==> 0XF8000788[8:8] = 0x00000000U | |
3019 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3020 | // .. IO_Type = 1 | |
3021 | // .. ==> 0XF8000788[11:9] = 0x00000001U | |
3022 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3023 | // .. PULLUP = 0 | |
3024 | // .. ==> 0XF8000788[12:12] = 0x00000000U | |
3025 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3026 | // .. DisableRcvr = 0 | |
3027 | // .. ==> 0XF8000788[13:13] = 0x00000000U | |
3028 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3029 | // .. | |
3030 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), | |
3031 | // .. TRI_ENABLE = 0 | |
3032 | // .. ==> 0XF800078C[0:0] = 0x00000000U | |
3033 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3034 | // .. L0_SEL = 0 | |
3035 | // .. ==> 0XF800078C[1:1] = 0x00000000U | |
3036 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3037 | // .. L1_SEL = 1 | |
3038 | // .. ==> 0XF800078C[2:2] = 0x00000001U | |
3039 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3040 | // .. L2_SEL = 0 | |
3041 | // .. ==> 0XF800078C[4:3] = 0x00000000U | |
3042 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3043 | // .. L3_SEL = 0 | |
3044 | // .. ==> 0XF800078C[7:5] = 0x00000000U | |
3045 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3046 | // .. Speed = 0 | |
3047 | // .. ==> 0XF800078C[8:8] = 0x00000000U | |
3048 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3049 | // .. IO_Type = 1 | |
3050 | // .. ==> 0XF800078C[11:9] = 0x00000001U | |
3051 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3052 | // .. PULLUP = 0 | |
3053 | // .. ==> 0XF800078C[12:12] = 0x00000000U | |
3054 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3055 | // .. DisableRcvr = 0 | |
3056 | // .. ==> 0XF800078C[13:13] = 0x00000000U | |
3057 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3058 | // .. | |
3059 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), | |
3060 | // .. TRI_ENABLE = 1 | |
3061 | // .. ==> 0XF8000790[0:0] = 0x00000001U | |
3062 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
3063 | // .. L0_SEL = 0 | |
3064 | // .. ==> 0XF8000790[1:1] = 0x00000000U | |
3065 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3066 | // .. L1_SEL = 1 | |
3067 | // .. ==> 0XF8000790[2:2] = 0x00000001U | |
3068 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3069 | // .. L2_SEL = 0 | |
3070 | // .. ==> 0XF8000790[4:3] = 0x00000000U | |
3071 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3072 | // .. L3_SEL = 0 | |
3073 | // .. ==> 0XF8000790[7:5] = 0x00000000U | |
3074 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3075 | // .. Speed = 0 | |
3076 | // .. ==> 0XF8000790[8:8] = 0x00000000U | |
3077 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3078 | // .. IO_Type = 1 | |
3079 | // .. ==> 0XF8000790[11:9] = 0x00000001U | |
3080 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3081 | // .. PULLUP = 0 | |
3082 | // .. ==> 0XF8000790[12:12] = 0x00000000U | |
3083 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3084 | // .. DisableRcvr = 0 | |
3085 | // .. ==> 0XF8000790[13:13] = 0x00000000U | |
3086 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3087 | // .. | |
3088 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), | |
3089 | // .. TRI_ENABLE = 0 | |
3090 | // .. ==> 0XF8000794[0:0] = 0x00000000U | |
3091 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3092 | // .. L0_SEL = 0 | |
3093 | // .. ==> 0XF8000794[1:1] = 0x00000000U | |
3094 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3095 | // .. L1_SEL = 1 | |
3096 | // .. ==> 0XF8000794[2:2] = 0x00000001U | |
3097 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3098 | // .. L2_SEL = 0 | |
3099 | // .. ==> 0XF8000794[4:3] = 0x00000000U | |
3100 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3101 | // .. L3_SEL = 0 | |
3102 | // .. ==> 0XF8000794[7:5] = 0x00000000U | |
3103 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3104 | // .. Speed = 0 | |
3105 | // .. ==> 0XF8000794[8:8] = 0x00000000U | |
3106 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3107 | // .. IO_Type = 1 | |
3108 | // .. ==> 0XF8000794[11:9] = 0x00000001U | |
3109 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3110 | // .. PULLUP = 0 | |
3111 | // .. ==> 0XF8000794[12:12] = 0x00000000U | |
3112 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3113 | // .. DisableRcvr = 0 | |
3114 | // .. ==> 0XF8000794[13:13] = 0x00000000U | |
3115 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3116 | // .. | |
3117 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), | |
3118 | // .. TRI_ENABLE = 0 | |
3119 | // .. ==> 0XF8000798[0:0] = 0x00000000U | |
3120 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3121 | // .. L0_SEL = 0 | |
3122 | // .. ==> 0XF8000798[1:1] = 0x00000000U | |
3123 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3124 | // .. L1_SEL = 1 | |
3125 | // .. ==> 0XF8000798[2:2] = 0x00000001U | |
3126 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3127 | // .. L2_SEL = 0 | |
3128 | // .. ==> 0XF8000798[4:3] = 0x00000000U | |
3129 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3130 | // .. L3_SEL = 0 | |
3131 | // .. ==> 0XF8000798[7:5] = 0x00000000U | |
3132 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3133 | // .. Speed = 0 | |
3134 | // .. ==> 0XF8000798[8:8] = 0x00000000U | |
3135 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3136 | // .. IO_Type = 1 | |
3137 | // .. ==> 0XF8000798[11:9] = 0x00000001U | |
3138 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3139 | // .. PULLUP = 0 | |
3140 | // .. ==> 0XF8000798[12:12] = 0x00000000U | |
3141 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3142 | // .. DisableRcvr = 0 | |
3143 | // .. ==> 0XF8000798[13:13] = 0x00000000U | |
3144 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3145 | // .. | |
3146 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), | |
3147 | // .. TRI_ENABLE = 0 | |
3148 | // .. ==> 0XF800079C[0:0] = 0x00000000U | |
3149 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3150 | // .. L0_SEL = 0 | |
3151 | // .. ==> 0XF800079C[1:1] = 0x00000000U | |
3152 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3153 | // .. L1_SEL = 1 | |
3154 | // .. ==> 0XF800079C[2:2] = 0x00000001U | |
3155 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3156 | // .. L2_SEL = 0 | |
3157 | // .. ==> 0XF800079C[4:3] = 0x00000000U | |
3158 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3159 | // .. L3_SEL = 0 | |
3160 | // .. ==> 0XF800079C[7:5] = 0x00000000U | |
3161 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3162 | // .. Speed = 0 | |
3163 | // .. ==> 0XF800079C[8:8] = 0x00000000U | |
3164 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3165 | // .. IO_Type = 1 | |
3166 | // .. ==> 0XF800079C[11:9] = 0x00000001U | |
3167 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3168 | // .. PULLUP = 0 | |
3169 | // .. ==> 0XF800079C[12:12] = 0x00000000U | |
3170 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3171 | // .. DisableRcvr = 0 | |
3172 | // .. ==> 0XF800079C[13:13] = 0x00000000U | |
3173 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3174 | // .. | |
3175 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), | |
3176 | // .. TRI_ENABLE = 0 | |
3177 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | |
3178 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3179 | // .. L0_SEL = 0 | |
3180 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | |
3181 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3182 | // .. L1_SEL = 0 | |
3183 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | |
3184 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3185 | // .. L2_SEL = 0 | |
3186 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | |
3187 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3188 | // .. L3_SEL = 4 | |
3189 | // .. ==> 0XF80007A0[7:5] = 0x00000004U | |
3190 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3191 | // .. Speed = 0 | |
3192 | // .. ==> 0XF80007A0[8:8] = 0x00000000U | |
3193 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3194 | // .. IO_Type = 1 | |
3195 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | |
3196 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3197 | // .. PULLUP = 0 | |
3198 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | |
3199 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3200 | // .. DisableRcvr = 0 | |
3201 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | |
3202 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3203 | // .. | |
3204 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), | |
3205 | // .. TRI_ENABLE = 0 | |
3206 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | |
3207 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3208 | // .. L0_SEL = 0 | |
3209 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | |
3210 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3211 | // .. L1_SEL = 0 | |
3212 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | |
3213 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3214 | // .. L2_SEL = 0 | |
3215 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | |
3216 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3217 | // .. L3_SEL = 4 | |
3218 | // .. ==> 0XF80007A4[7:5] = 0x00000004U | |
3219 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3220 | // .. Speed = 0 | |
3221 | // .. ==> 0XF80007A4[8:8] = 0x00000000U | |
3222 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3223 | // .. IO_Type = 1 | |
3224 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | |
3225 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3226 | // .. PULLUP = 0 | |
3227 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | |
3228 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3229 | // .. DisableRcvr = 0 | |
3230 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | |
3231 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3232 | // .. | |
3233 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), | |
3234 | // .. TRI_ENABLE = 0 | |
3235 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | |
3236 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3237 | // .. L0_SEL = 0 | |
3238 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | |
3239 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3240 | // .. L1_SEL = 0 | |
3241 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | |
3242 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3243 | // .. L2_SEL = 0 | |
3244 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | |
3245 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3246 | // .. L3_SEL = 4 | |
3247 | // .. ==> 0XF80007A8[7:5] = 0x00000004U | |
3248 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3249 | // .. Speed = 0 | |
3250 | // .. ==> 0XF80007A8[8:8] = 0x00000000U | |
3251 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3252 | // .. IO_Type = 1 | |
3253 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | |
3254 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3255 | // .. PULLUP = 0 | |
3256 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | |
3257 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3258 | // .. DisableRcvr = 0 | |
3259 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | |
3260 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3261 | // .. | |
3262 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), | |
3263 | // .. TRI_ENABLE = 0 | |
3264 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | |
3265 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3266 | // .. L0_SEL = 0 | |
3267 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | |
3268 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3269 | // .. L1_SEL = 0 | |
3270 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | |
3271 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3272 | // .. L2_SEL = 0 | |
3273 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | |
3274 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3275 | // .. L3_SEL = 4 | |
3276 | // .. ==> 0XF80007AC[7:5] = 0x00000004U | |
3277 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3278 | // .. Speed = 0 | |
3279 | // .. ==> 0XF80007AC[8:8] = 0x00000000U | |
3280 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3281 | // .. IO_Type = 1 | |
3282 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | |
3283 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3284 | // .. PULLUP = 0 | |
3285 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | |
3286 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3287 | // .. DisableRcvr = 0 | |
3288 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | |
3289 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3290 | // .. | |
3291 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), | |
3292 | // .. TRI_ENABLE = 0 | |
3293 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | |
3294 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3295 | // .. L0_SEL = 0 | |
3296 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | |
3297 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3298 | // .. L1_SEL = 0 | |
3299 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | |
3300 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3301 | // .. L2_SEL = 0 | |
3302 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | |
3303 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3304 | // .. L3_SEL = 4 | |
3305 | // .. ==> 0XF80007B0[7:5] = 0x00000004U | |
3306 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3307 | // .. Speed = 0 | |
3308 | // .. ==> 0XF80007B0[8:8] = 0x00000000U | |
3309 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3310 | // .. IO_Type = 1 | |
3311 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | |
3312 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3313 | // .. PULLUP = 0 | |
3314 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | |
3315 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3316 | // .. DisableRcvr = 0 | |
3317 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | |
3318 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3319 | // .. | |
3320 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), | |
3321 | // .. TRI_ENABLE = 0 | |
3322 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | |
3323 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3324 | // .. L0_SEL = 0 | |
3325 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | |
3326 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3327 | // .. L1_SEL = 0 | |
3328 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | |
3329 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3330 | // .. L2_SEL = 0 | |
3331 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | |
3332 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3333 | // .. L3_SEL = 4 | |
3334 | // .. ==> 0XF80007B4[7:5] = 0x00000004U | |
3335 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3336 | // .. Speed = 0 | |
3337 | // .. ==> 0XF80007B4[8:8] = 0x00000000U | |
3338 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3339 | // .. IO_Type = 1 | |
3340 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | |
3341 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3342 | // .. PULLUP = 0 | |
3343 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | |
3344 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3345 | // .. DisableRcvr = 0 | |
3346 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | |
3347 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3348 | // .. | |
3349 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), | |
3350 | // .. TRI_ENABLE = 1 | |
3351 | // .. ==> 0XF80007B8[0:0] = 0x00000001U | |
3352 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
3353 | // .. Speed = 0 | |
3354 | // .. ==> 0XF80007B8[8:8] = 0x00000000U | |
3355 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3356 | // .. IO_Type = 1 | |
3357 | // .. ==> 0XF80007B8[11:9] = 0x00000001U | |
3358 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3359 | // .. PULLUP = 0 | |
3360 | // .. ==> 0XF80007B8[12:12] = 0x00000000U | |
3361 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3362 | // .. DisableRcvr = 0 | |
3363 | // .. ==> 0XF80007B8[13:13] = 0x00000000U | |
3364 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3365 | // .. | |
3366 | EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), | |
3367 | // .. TRI_ENABLE = 0 | |
3368 | // .. ==> 0XF80007BC[0:0] = 0x00000000U | |
3369 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3370 | // .. L0_SEL = 0 | |
3371 | // .. ==> 0XF80007BC[1:1] = 0x00000000U | |
3372 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3373 | // .. L1_SEL = 0 | |
3374 | // .. ==> 0XF80007BC[2:2] = 0x00000000U | |
3375 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3376 | // .. L2_SEL = 0 | |
3377 | // .. ==> 0XF80007BC[4:3] = 0x00000000U | |
3378 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3379 | // .. L3_SEL = 0 | |
3380 | // .. ==> 0XF80007BC[7:5] = 0x00000000U | |
3381 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3382 | // .. Speed = 0 | |
3383 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | |
3384 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3385 | // .. IO_Type = 1 | |
3386 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | |
3387 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3388 | // .. PULLUP = 0 | |
3389 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | |
3390 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3391 | // .. DisableRcvr = 0 | |
3392 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | |
3393 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3394 | // .. | |
3395 | EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), | |
3396 | // .. TRI_ENABLE = 0 | |
3397 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | |
3398 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3399 | // .. L0_SEL = 0 | |
3400 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | |
3401 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3402 | // .. L1_SEL = 0 | |
3403 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | |
3404 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3405 | // .. L2_SEL = 0 | |
3406 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | |
3407 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3408 | // .. L3_SEL = 7 | |
3409 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | |
3410 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | |
3411 | // .. Speed = 0 | |
3412 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | |
3413 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3414 | // .. IO_Type = 1 | |
3415 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | |
3416 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3417 | // .. PULLUP = 0 | |
3418 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | |
3419 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3420 | // .. DisableRcvr = 0 | |
3421 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | |
3422 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3423 | // .. | |
3424 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | |
3425 | // .. TRI_ENABLE = 1 | |
3426 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | |
3427 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
3428 | // .. L0_SEL = 0 | |
3429 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | |
3430 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3431 | // .. L1_SEL = 0 | |
3432 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | |
3433 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3434 | // .. L2_SEL = 0 | |
3435 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | |
3436 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3437 | // .. L3_SEL = 7 | |
3438 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | |
3439 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | |
3440 | // .. Speed = 0 | |
3441 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | |
3442 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3443 | // .. IO_Type = 1 | |
3444 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | |
3445 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3446 | // .. PULLUP = 0 | |
3447 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | |
3448 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3449 | // .. DisableRcvr = 0 | |
3450 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | |
3451 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3452 | // .. | |
3453 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | |
3454 | // .. TRI_ENABLE = 1 | |
3455 | // .. ==> 0XF80007C8[0:0] = 0x00000001U | |
3456 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
3457 | // .. Speed = 0 | |
3458 | // .. ==> 0XF80007C8[8:8] = 0x00000000U | |
3459 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3460 | // .. IO_Type = 1 | |
3461 | // .. ==> 0XF80007C8[11:9] = 0x00000001U | |
3462 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3463 | // .. PULLUP = 0 | |
3464 | // .. ==> 0XF80007C8[12:12] = 0x00000000U | |
3465 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3466 | // .. DisableRcvr = 0 | |
3467 | // .. ==> 0XF80007C8[13:13] = 0x00000000U | |
3468 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3469 | // .. | |
3470 | EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), | |
3471 | // .. TRI_ENABLE = 0 | |
3472 | // .. ==> 0XF80007CC[0:0] = 0x00000000U | |
3473 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3474 | // .. L0_SEL = 0 | |
3475 | // .. ==> 0XF80007CC[1:1] = 0x00000000U | |
3476 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3477 | // .. L1_SEL = 0 | |
3478 | // .. ==> 0XF80007CC[2:2] = 0x00000000U | |
3479 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3480 | // .. L2_SEL = 0 | |
3481 | // .. ==> 0XF80007CC[4:3] = 0x00000000U | |
3482 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3483 | // .. L3_SEL = 0 | |
3484 | // .. ==> 0XF80007CC[7:5] = 0x00000000U | |
3485 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
3486 | // .. Speed = 0 | |
3487 | // .. ==> 0XF80007CC[8:8] = 0x00000000U | |
3488 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3489 | // .. IO_Type = 1 | |
3490 | // .. ==> 0XF80007CC[11:9] = 0x00000001U | |
3491 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3492 | // .. PULLUP = 0 | |
3493 | // .. ==> 0XF80007CC[12:12] = 0x00000000U | |
3494 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3495 | // .. DisableRcvr = 0 | |
3496 | // .. ==> 0XF80007CC[13:13] = 0x00000000U | |
3497 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3498 | // .. | |
3499 | EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), | |
3500 | // .. TRI_ENABLE = 0 | |
3501 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | |
3502 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3503 | // .. L0_SEL = 0 | |
3504 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | |
3505 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3506 | // .. L1_SEL = 0 | |
3507 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | |
3508 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3509 | // .. L2_SEL = 0 | |
3510 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | |
3511 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3512 | // .. L3_SEL = 4 | |
3513 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | |
3514 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3515 | // .. Speed = 0 | |
3516 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | |
3517 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3518 | // .. IO_Type = 1 | |
3519 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | |
3520 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3521 | // .. PULLUP = 0 | |
3522 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | |
3523 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3524 | // .. DisableRcvr = 0 | |
3525 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | |
3526 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3527 | // .. | |
3528 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | |
3529 | // .. TRI_ENABLE = 0 | |
3530 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | |
3531 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3532 | // .. L0_SEL = 0 | |
3533 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | |
3534 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
3535 | // .. L1_SEL = 0 | |
3536 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | |
3537 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
3538 | // .. L2_SEL = 0 | |
3539 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | |
3540 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
3541 | // .. L3_SEL = 4 | |
3542 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | |
3543 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
3544 | // .. Speed = 0 | |
3545 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | |
3546 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3547 | // .. IO_Type = 1 | |
3548 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | |
3549 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
3550 | // .. PULLUP = 0 | |
3551 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | |
3552 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
3553 | // .. DisableRcvr = 0 | |
3554 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | |
3555 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
3556 | // .. | |
3557 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | |
3558 | // .. SDIO0_WP_SEL = 50 | |
3559 | // .. ==> 0XF8000830[5:0] = 0x00000032U | |
3560 | // .. ==> MASK : 0x0000003FU VAL : 0x00000032U | |
3561 | // .. SDIO0_CD_SEL = 46 | |
3562 | // .. ==> 0XF8000830[21:16] = 0x0000002EU | |
3563 | // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U | |
3564 | // .. | |
3565 | EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), | |
3566 | // .. FINISH: MIO PROGRAMMING | |
3567 | // .. START: LOCK IT BACK | |
3568 | // .. LOCK_KEY = 0X767B | |
3569 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
3570 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
3571 | // .. | |
3572 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
3573 | // .. FINISH: LOCK IT BACK | |
3574 | // FINISH: top | |
3575 | // | |
3576 | EMIT_EXIT(), | |
3577 | ||
3578 | // | |
3579 | }; | |
3580 | ||
3581 | unsigned long ps7_peripherals_init_data_3_0[] = { | |
3582 | // START: top | |
3583 | // .. START: SLCR SETTINGS | |
3584 | // .. UNLOCK_KEY = 0XDF0D | |
3585 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
3586 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
3587 | // .. | |
3588 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
3589 | // .. FINISH: SLCR SETTINGS | |
3590 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | |
3591 | // .. IBUF_DISABLE_MODE = 0x1 | |
3592 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | |
3593 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
3594 | // .. TERM_DISABLE_MODE = 0x1 | |
3595 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | |
3596 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
3597 | // .. | |
3598 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | |
3599 | // .. IBUF_DISABLE_MODE = 0x1 | |
3600 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | |
3601 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
3602 | // .. TERM_DISABLE_MODE = 0x1 | |
3603 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | |
3604 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
3605 | // .. | |
3606 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | |
3607 | // .. IBUF_DISABLE_MODE = 0x1 | |
3608 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | |
3609 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
3610 | // .. TERM_DISABLE_MODE = 0x1 | |
3611 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | |
3612 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
3613 | // .. | |
3614 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | |
3615 | // .. IBUF_DISABLE_MODE = 0x1 | |
3616 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | |
3617 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
3618 | // .. TERM_DISABLE_MODE = 0x1 | |
3619 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | |
3620 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
3621 | // .. | |
3622 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | |
3623 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | |
3624 | // .. START: LOCK IT BACK | |
3625 | // .. LOCK_KEY = 0X767B | |
3626 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
3627 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
3628 | // .. | |
3629 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
3630 | // .. FINISH: LOCK IT BACK | |
3631 | // .. START: SRAM/NOR SET OPMODE | |
3632 | // .. FINISH: SRAM/NOR SET OPMODE | |
3633 | // .. START: UART REGISTERS | |
3634 | // .. BDIV = 0x6 | |
3635 | // .. ==> 0XE0001034[7:0] = 0x00000006U | |
3636 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | |
3637 | // .. | |
3638 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | |
3639 | // .. CD = 0x3e | |
3640 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | |
3641 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | |
3642 | // .. | |
3643 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | |
3644 | // .. STPBRK = 0x0 | |
3645 | // .. ==> 0XE0001000[8:8] = 0x00000000U | |
3646 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
3647 | // .. STTBRK = 0x0 | |
3648 | // .. ==> 0XE0001000[7:7] = 0x00000000U | |
3649 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
3650 | // .. RSTTO = 0x0 | |
3651 | // .. ==> 0XE0001000[6:6] = 0x00000000U | |
3652 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
3653 | // .. TXDIS = 0x0 | |
3654 | // .. ==> 0XE0001000[5:5] = 0x00000000U | |
3655 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
3656 | // .. TXEN = 0x1 | |
3657 | // .. ==> 0XE0001000[4:4] = 0x00000001U | |
3658 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
3659 | // .. RXDIS = 0x0 | |
3660 | // .. ==> 0XE0001000[3:3] = 0x00000000U | |
3661 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
3662 | // .. RXEN = 0x1 | |
3663 | // .. ==> 0XE0001000[2:2] = 0x00000001U | |
3664 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
3665 | // .. TXRES = 0x1 | |
3666 | // .. ==> 0XE0001000[1:1] = 0x00000001U | |
3667 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
3668 | // .. RXRES = 0x1 | |
3669 | // .. ==> 0XE0001000[0:0] = 0x00000001U | |
3670 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
3671 | // .. | |
3672 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | |
3673 | // .. CHMODE = 0x0 | |
3674 | // .. ==> 0XE0001004[9:8] = 0x00000000U | |
3675 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | |
3676 | // .. NBSTOP = 0x0 | |
3677 | // .. ==> 0XE0001004[7:6] = 0x00000000U | |
3678 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | |
3679 | // .. PAR = 0x4 | |
3680 | // .. ==> 0XE0001004[5:3] = 0x00000004U | |
3681 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | |
3682 | // .. CHRL = 0x0 | |
3683 | // .. ==> 0XE0001004[2:1] = 0x00000000U | |
3684 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
3685 | // .. CLKS = 0x0 | |
3686 | // .. ==> 0XE0001004[0:0] = 0x00000000U | |
3687 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
3688 | // .. | |
3689 | EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), | |
3690 | // .. FINISH: UART REGISTERS | |
3691 | // .. START: QSPI REGISTERS | |
3692 | // .. Holdb_dr = 1 | |
3693 | // .. ==> 0XE000D000[19:19] = 0x00000001U | |
3694 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
3695 | // .. | |
3696 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | |
3697 | // .. FINISH: QSPI REGISTERS | |
3698 | // .. START: PL POWER ON RESET REGISTERS | |
3699 | // .. PCFG_POR_CNT_4K = 0 | |
3700 | // .. ==> 0XF8007000[29:29] = 0x00000000U | |
3701 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | |
3702 | // .. | |
3703 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | |
3704 | // .. FINISH: PL POWER ON RESET REGISTERS | |
3705 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | |
3706 | // .. .. START: NAND SET CYCLE | |
3707 | // .. .. FINISH: NAND SET CYCLE | |
3708 | // .. .. START: OPMODE | |
3709 | // .. .. FINISH: OPMODE | |
3710 | // .. .. START: DIRECT COMMAND | |
3711 | // .. .. FINISH: DIRECT COMMAND | |
3712 | // .. .. START: SRAM/NOR CS0 SET CYCLE | |
3713 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | |
3714 | // .. .. START: DIRECT COMMAND | |
3715 | // .. .. FINISH: DIRECT COMMAND | |
3716 | // .. .. START: NOR CS0 BASE ADDRESS | |
3717 | // .. .. FINISH: NOR CS0 BASE ADDRESS | |
3718 | // .. .. START: SRAM/NOR CS1 SET CYCLE | |
3719 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | |
3720 | // .. .. START: DIRECT COMMAND | |
3721 | // .. .. FINISH: DIRECT COMMAND | |
3722 | // .. .. START: NOR CS1 BASE ADDRESS | |
3723 | // .. .. FINISH: NOR CS1 BASE ADDRESS | |
3724 | // .. .. START: USB RESET | |
3725 | // .. .. .. START: USB0 RESET | |
3726 | // .. .. .. .. START: DIR MODE BANK 0 | |
3727 | // .. .. .. .. DIRECTION_0 = 0x80 | |
3728 | // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U | |
3729 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | |
3730 | // .. .. .. .. | |
3731 | EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), | |
3732 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
3733 | // .. .. .. .. START: DIR MODE BANK 1 | |
3734 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
3735 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3736 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
3737 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
3738 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
3739 | // .. .. .. .. DATA_0_LSW = 0x80 | |
3740 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | |
3741 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | |
3742 | // .. .. .. .. | |
3743 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | |
3744 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3745 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3746 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3747 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3748 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3749 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3750 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3751 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
3752 | // .. .. .. .. OP_ENABLE_0 = 0x80 | |
3753 | // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U | |
3754 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | |
3755 | // .. .. .. .. | |
3756 | EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), | |
3757 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
3758 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
3759 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
3760 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
3761 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
3762 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
3763 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
3764 | // .. .. .. .. DATA_0_LSW = 0x0 | |
3765 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U | |
3766 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U | |
3767 | // .. .. .. .. | |
3768 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), | |
3769 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
3770 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
3771 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
3772 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
3773 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
3774 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
3775 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
3776 | // .. .. .. .. START: ADD 1 MS DELAY | |
3777 | // .. .. .. .. | |
3778 | EMIT_MASKDELAY(0XF8F00200, 1), | |
3779 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
3780 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3781 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
3782 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
3783 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
3784 | // .. .. .. .. DATA_0_LSW = 0x80 | |
3785 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | |
3786 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | |
3787 | // .. .. .. .. | |
3788 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | |
3789 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3790 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3791 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3792 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3793 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3794 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3795 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3796 | // .. .. .. FINISH: USB0 RESET | |
3797 | // .. .. .. START: USB1 RESET | |
3798 | // .. .. .. .. START: DIR MODE BANK 0 | |
3799 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
3800 | // .. .. .. .. START: DIR MODE BANK 1 | |
3801 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
3802 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3803 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3804 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3805 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3806 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3807 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3808 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3809 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3810 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
3811 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
3812 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
3813 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
3814 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
3815 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
3816 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
3817 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
3818 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
3819 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
3820 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
3821 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
3822 | // .. .. .. .. START: ADD 1 MS DELAY | |
3823 | // .. .. .. .. | |
3824 | EMIT_MASKDELAY(0XF8F00200, 1), | |
3825 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
3826 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3827 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3828 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3829 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3830 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3831 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3832 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3833 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3834 | // .. .. .. FINISH: USB1 RESET | |
3835 | // .. .. FINISH: USB RESET | |
3836 | // .. .. START: ENET RESET | |
3837 | // .. .. .. START: ENET0 RESET | |
3838 | // .. .. .. .. START: DIR MODE BANK 0 | |
3839 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
3840 | // .. .. .. .. START: DIR MODE BANK 1 | |
3841 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
3842 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3843 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3844 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3845 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3846 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3847 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3848 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3849 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3850 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
3851 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
3852 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
3853 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
3854 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
3855 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
3856 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
3857 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
3858 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
3859 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
3860 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
3861 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
3862 | // .. .. .. .. START: ADD 1 MS DELAY | |
3863 | // .. .. .. .. | |
3864 | EMIT_MASKDELAY(0XF8F00200, 1), | |
3865 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
3866 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3867 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3868 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3869 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3870 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3871 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3872 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3873 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3874 | // .. .. .. FINISH: ENET0 RESET | |
3875 | // .. .. .. START: ENET1 RESET | |
3876 | // .. .. .. .. START: DIR MODE BANK 0 | |
3877 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
3878 | // .. .. .. .. START: DIR MODE BANK 1 | |
3879 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
3880 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3881 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3882 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3883 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3884 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3885 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3886 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3887 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3888 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
3889 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
3890 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
3891 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
3892 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
3893 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
3894 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
3895 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
3896 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
3897 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
3898 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
3899 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
3900 | // .. .. .. .. START: ADD 1 MS DELAY | |
3901 | // .. .. .. .. | |
3902 | EMIT_MASKDELAY(0XF8F00200, 1), | |
3903 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
3904 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3905 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3906 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3907 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3908 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3909 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3910 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3911 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3912 | // .. .. .. FINISH: ENET1 RESET | |
3913 | // .. .. FINISH: ENET RESET | |
3914 | // .. .. START: I2C RESET | |
3915 | // .. .. .. START: I2C0 RESET | |
3916 | // .. .. .. .. START: DIR MODE GPIO BANK0 | |
3917 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | |
3918 | // .. .. .. .. START: DIR MODE GPIO BANK1 | |
3919 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | |
3920 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3921 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3922 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3923 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3924 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3925 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3926 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3927 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3928 | // .. .. .. .. START: OUTPUT ENABLE | |
3929 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
3930 | // .. .. .. .. START: OUTPUT ENABLE | |
3931 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
3932 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
3933 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
3934 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
3935 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
3936 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
3937 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
3938 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
3939 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
3940 | // .. .. .. .. START: ADD 1 MS DELAY | |
3941 | // .. .. .. .. | |
3942 | EMIT_MASKDELAY(0XF8F00200, 1), | |
3943 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
3944 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3945 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3946 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3947 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3948 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3949 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3950 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3951 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3952 | // .. .. .. FINISH: I2C0 RESET | |
3953 | // .. .. .. START: I2C1 RESET | |
3954 | // .. .. .. .. START: DIR MODE GPIO BANK0 | |
3955 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | |
3956 | // .. .. .. .. START: DIR MODE GPIO BANK1 | |
3957 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | |
3958 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3959 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3960 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3961 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3962 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3963 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3964 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3965 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3966 | // .. .. .. .. START: OUTPUT ENABLE | |
3967 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
3968 | // .. .. .. .. START: OUTPUT ENABLE | |
3969 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
3970 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
3971 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
3972 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
3973 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
3974 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
3975 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
3976 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
3977 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
3978 | // .. .. .. .. START: ADD 1 MS DELAY | |
3979 | // .. .. .. .. | |
3980 | EMIT_MASKDELAY(0XF8F00200, 1), | |
3981 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
3982 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3983 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3984 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3985 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
3986 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3987 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
3988 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3989 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
3990 | // .. .. .. FINISH: I2C1 RESET | |
3991 | // .. .. FINISH: I2C RESET | |
3992 | // .. .. START: NOR CHIP SELECT | |
3993 | // .. .. .. START: DIR MODE BANK 0 | |
3994 | // .. .. .. FINISH: DIR MODE BANK 0 | |
3995 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3996 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
3997 | // .. .. .. START: OUTPUT ENABLE BANK 0 | |
3998 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
3999 | // .. .. FINISH: NOR CHIP SELECT | |
4000 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | |
4001 | // FINISH: top | |
4002 | // | |
4003 | EMIT_EXIT(), | |
4004 | ||
4005 | // | |
4006 | }; | |
4007 | ||
4008 | unsigned long ps7_post_config_3_0[] = { | |
4009 | // START: top | |
4010 | // .. START: SLCR SETTINGS | |
4011 | // .. UNLOCK_KEY = 0XDF0D | |
4012 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
4013 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
4014 | // .. | |
4015 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
4016 | // .. FINISH: SLCR SETTINGS | |
4017 | // .. START: ENABLING LEVEL SHIFTER | |
4018 | // .. USER_LVL_INP_EN_0 = 1 | |
4019 | // .. ==> 0XF8000900[3:3] = 0x00000001U | |
4020 | // .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
4021 | // .. USER_LVL_OUT_EN_0 = 1 | |
4022 | // .. ==> 0XF8000900[2:2] = 0x00000001U | |
4023 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
4024 | // .. USER_LVL_INP_EN_1 = 1 | |
4025 | // .. ==> 0XF8000900[1:1] = 0x00000001U | |
4026 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
4027 | // .. USER_LVL_OUT_EN_1 = 1 | |
4028 | // .. ==> 0XF8000900[0:0] = 0x00000001U | |
4029 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4030 | // .. | |
4031 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | |
4032 | // .. FINISH: ENABLING LEVEL SHIFTER | |
4033 | // .. START: FPGA RESETS TO 0 | |
4034 | // .. reserved_3 = 0 | |
4035 | // .. ==> 0XF8000240[31:25] = 0x00000000U | |
4036 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | |
4037 | // .. reserved_FPGA_ACP_RST = 0 | |
4038 | // .. ==> 0XF8000240[24:24] = 0x00000000U | |
4039 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
4040 | // .. reserved_FPGA_AXDS3_RST = 0 | |
4041 | // .. ==> 0XF8000240[23:23] = 0x00000000U | |
4042 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
4043 | // .. reserved_FPGA_AXDS2_RST = 0 | |
4044 | // .. ==> 0XF8000240[22:22] = 0x00000000U | |
4045 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
4046 | // .. reserved_FPGA_AXDS1_RST = 0 | |
4047 | // .. ==> 0XF8000240[21:21] = 0x00000000U | |
4048 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
4049 | // .. reserved_FPGA_AXDS0_RST = 0 | |
4050 | // .. ==> 0XF8000240[20:20] = 0x00000000U | |
4051 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
4052 | // .. reserved_2 = 0 | |
4053 | // .. ==> 0XF8000240[19:18] = 0x00000000U | |
4054 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | |
4055 | // .. reserved_FSSW1_FPGA_RST = 0 | |
4056 | // .. ==> 0XF8000240[17:17] = 0x00000000U | |
4057 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
4058 | // .. reserved_FSSW0_FPGA_RST = 0 | |
4059 | // .. ==> 0XF8000240[16:16] = 0x00000000U | |
4060 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
4061 | // .. reserved_1 = 0 | |
4062 | // .. ==> 0XF8000240[15:14] = 0x00000000U | |
4063 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | |
4064 | // .. reserved_FPGA_FMSW1_RST = 0 | |
4065 | // .. ==> 0XF8000240[13:13] = 0x00000000U | |
4066 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
4067 | // .. reserved_FPGA_FMSW0_RST = 0 | |
4068 | // .. ==> 0XF8000240[12:12] = 0x00000000U | |
4069 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
4070 | // .. reserved_FPGA_DMA3_RST = 0 | |
4071 | // .. ==> 0XF8000240[11:11] = 0x00000000U | |
4072 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
4073 | // .. reserved_FPGA_DMA2_RST = 0 | |
4074 | // .. ==> 0XF8000240[10:10] = 0x00000000U | |
4075 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
4076 | // .. reserved_FPGA_DMA1_RST = 0 | |
4077 | // .. ==> 0XF8000240[9:9] = 0x00000000U | |
4078 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
4079 | // .. reserved_FPGA_DMA0_RST = 0 | |
4080 | // .. ==> 0XF8000240[8:8] = 0x00000000U | |
4081 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
4082 | // .. reserved = 0 | |
4083 | // .. ==> 0XF8000240[7:4] = 0x00000000U | |
4084 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
4085 | // .. FPGA3_OUT_RST = 0 | |
4086 | // .. ==> 0XF8000240[3:3] = 0x00000000U | |
4087 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
4088 | // .. FPGA2_OUT_RST = 0 | |
4089 | // .. ==> 0XF8000240[2:2] = 0x00000000U | |
4090 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
4091 | // .. FPGA1_OUT_RST = 0 | |
4092 | // .. ==> 0XF8000240[1:1] = 0x00000000U | |
4093 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
4094 | // .. FPGA0_OUT_RST = 0 | |
4095 | // .. ==> 0XF8000240[0:0] = 0x00000000U | |
4096 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4097 | // .. | |
4098 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | |
4099 | // .. FINISH: FPGA RESETS TO 0 | |
4100 | // .. START: AFI REGISTERS | |
4101 | // .. .. START: AFI0 REGISTERS | |
4102 | // .. .. FINISH: AFI0 REGISTERS | |
4103 | // .. .. START: AFI1 REGISTERS | |
4104 | // .. .. FINISH: AFI1 REGISTERS | |
4105 | // .. .. START: AFI2 REGISTERS | |
4106 | // .. .. FINISH: AFI2 REGISTERS | |
4107 | // .. .. START: AFI3 REGISTERS | |
4108 | // .. .. FINISH: AFI3 REGISTERS | |
4109 | // .. FINISH: AFI REGISTERS | |
4110 | // .. START: LOCK IT BACK | |
4111 | // .. LOCK_KEY = 0X767B | |
4112 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
4113 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
4114 | // .. | |
4115 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
4116 | // .. FINISH: LOCK IT BACK | |
4117 | // FINISH: top | |
4118 | // | |
4119 | EMIT_EXIT(), | |
4120 | ||
4121 | // | |
4122 | }; | |
4123 | ||
95b237ec MY |
4124 | |
4125 | unsigned long ps7_pll_init_data_2_0[] = { | |
4126 | // START: top | |
4127 | // .. START: SLCR SETTINGS | |
4128 | // .. UNLOCK_KEY = 0XDF0D | |
4129 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
4130 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
4131 | // .. | |
4132 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
4133 | // .. FINISH: SLCR SETTINGS | |
4134 | // .. START: PLL SLCR REGISTERS | |
4135 | // .. .. START: ARM PLL INIT | |
4136 | // .. .. PLL_RES = 0x2 | |
4137 | // .. .. ==> 0XF8000110[7:4] = 0x00000002U | |
4138 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
4139 | // .. .. PLL_CP = 0x2 | |
4140 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | |
4141 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
4142 | // .. .. LOCK_CNT = 0xfa | |
4143 | // .. .. ==> 0XF8000110[21:12] = 0x000000FAU | |
4144 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | |
4145 | // .. .. | |
4146 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), | |
4147 | // .. .. .. START: UPDATE FB_DIV | |
4148 | // .. .. .. PLL_FDIV = 0x28 | |
4149 | // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U | |
4150 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U | |
4151 | // .. .. .. | |
4152 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), | |
4153 | // .. .. .. FINISH: UPDATE FB_DIV | |
4154 | // .. .. .. START: BY PASS PLL | |
4155 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
4156 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | |
4157 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
4158 | // .. .. .. | |
4159 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | |
4160 | // .. .. .. FINISH: BY PASS PLL | |
4161 | // .. .. .. START: ASSERT RESET | |
4162 | // .. .. .. PLL_RESET = 1 | |
4163 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | |
4164 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4165 | // .. .. .. | |
4166 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | |
4167 | // .. .. .. FINISH: ASSERT RESET | |
4168 | // .. .. .. START: DEASSERT RESET | |
4169 | // .. .. .. PLL_RESET = 0 | |
4170 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | |
4171 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4172 | // .. .. .. | |
4173 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | |
4174 | // .. .. .. FINISH: DEASSERT RESET | |
4175 | // .. .. .. START: CHECK PLL STATUS | |
4176 | // .. .. .. ARM_PLL_LOCK = 1 | |
4177 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | |
4178 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4179 | // .. .. .. | |
4180 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | |
4181 | // .. .. .. FINISH: CHECK PLL STATUS | |
4182 | // .. .. .. START: REMOVE PLL BY PASS | |
4183 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
4184 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | |
4185 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
4186 | // .. .. .. | |
4187 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | |
4188 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
4189 | // .. .. .. SRCSEL = 0x0 | |
4190 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | |
4191 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4192 | // .. .. .. DIVISOR = 0x2 | |
4193 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U | |
4194 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U | |
4195 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | |
4196 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | |
4197 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | |
4198 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | |
4199 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | |
4200 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | |
4201 | // .. .. .. CPU_2XCLKACT = 0x1 | |
4202 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | |
4203 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | |
4204 | // .. .. .. CPU_1XCLKACT = 0x1 | |
4205 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | |
4206 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | |
4207 | // .. .. .. CPU_PERI_CLKACT = 0x1 | |
4208 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | |
4209 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
4210 | // .. .. .. | |
4211 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), | |
4212 | // .. .. FINISH: ARM PLL INIT | |
4213 | // .. .. START: DDR PLL INIT | |
4214 | // .. .. PLL_RES = 0x2 | |
4215 | // .. .. ==> 0XF8000114[7:4] = 0x00000002U | |
4216 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
4217 | // .. .. PLL_CP = 0x2 | |
4218 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | |
4219 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
4220 | // .. .. LOCK_CNT = 0x12c | |
4221 | // .. .. ==> 0XF8000114[21:12] = 0x0000012CU | |
4222 | // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U | |
4223 | // .. .. | |
4224 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), | |
4225 | // .. .. .. START: UPDATE FB_DIV | |
4226 | // .. .. .. PLL_FDIV = 0x20 | |
4227 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U | |
4228 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U | |
4229 | // .. .. .. | |
4230 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), | |
4231 | // .. .. .. FINISH: UPDATE FB_DIV | |
4232 | // .. .. .. START: BY PASS PLL | |
4233 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
4234 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | |
4235 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
4236 | // .. .. .. | |
4237 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | |
4238 | // .. .. .. FINISH: BY PASS PLL | |
4239 | // .. .. .. START: ASSERT RESET | |
4240 | // .. .. .. PLL_RESET = 1 | |
4241 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | |
4242 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4243 | // .. .. .. | |
4244 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | |
4245 | // .. .. .. FINISH: ASSERT RESET | |
4246 | // .. .. .. START: DEASSERT RESET | |
4247 | // .. .. .. PLL_RESET = 0 | |
4248 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | |
4249 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4250 | // .. .. .. | |
4251 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | |
4252 | // .. .. .. FINISH: DEASSERT RESET | |
4253 | // .. .. .. START: CHECK PLL STATUS | |
4254 | // .. .. .. DDR_PLL_LOCK = 1 | |
4255 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | |
4256 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
4257 | // .. .. .. | |
4258 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | |
4259 | // .. .. .. FINISH: CHECK PLL STATUS | |
4260 | // .. .. .. START: REMOVE PLL BY PASS | |
4261 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
4262 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | |
4263 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
4264 | // .. .. .. | |
4265 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | |
4266 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
4267 | // .. .. .. DDR_3XCLKACT = 0x1 | |
4268 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | |
4269 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4270 | // .. .. .. DDR_2XCLKACT = 0x1 | |
4271 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | |
4272 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
4273 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | |
4274 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | |
4275 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | |
4276 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | |
4277 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | |
4278 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | |
4279 | // .. .. .. | |
4280 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | |
4281 | // .. .. FINISH: DDR PLL INIT | |
4282 | // .. .. START: IO PLL INIT | |
4283 | // .. .. PLL_RES = 0xc | |
4284 | // .. .. ==> 0XF8000118[7:4] = 0x0000000CU | |
4285 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | |
4286 | // .. .. PLL_CP = 0x2 | |
4287 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | |
4288 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
4289 | // .. .. LOCK_CNT = 0x145 | |
4290 | // .. .. ==> 0XF8000118[21:12] = 0x00000145U | |
4291 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U | |
4292 | // .. .. | |
4293 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), | |
4294 | // .. .. .. START: UPDATE FB_DIV | |
4295 | // .. .. .. PLL_FDIV = 0x1e | |
4296 | // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU | |
4297 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U | |
4298 | // .. .. .. | |
4299 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), | |
4300 | // .. .. .. FINISH: UPDATE FB_DIV | |
4301 | // .. .. .. START: BY PASS PLL | |
4302 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
4303 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | |
4304 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
4305 | // .. .. .. | |
4306 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | |
4307 | // .. .. .. FINISH: BY PASS PLL | |
4308 | // .. .. .. START: ASSERT RESET | |
4309 | // .. .. .. PLL_RESET = 1 | |
4310 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | |
4311 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4312 | // .. .. .. | |
4313 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | |
4314 | // .. .. .. FINISH: ASSERT RESET | |
4315 | // .. .. .. START: DEASSERT RESET | |
4316 | // .. .. .. PLL_RESET = 0 | |
4317 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | |
4318 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4319 | // .. .. .. | |
4320 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | |
4321 | // .. .. .. FINISH: DEASSERT RESET | |
4322 | // .. .. .. START: CHECK PLL STATUS | |
4323 | // .. .. .. IO_PLL_LOCK = 1 | |
4324 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | |
4325 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
4326 | // .. .. .. | |
4327 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | |
4328 | // .. .. .. FINISH: CHECK PLL STATUS | |
4329 | // .. .. .. START: REMOVE PLL BY PASS | |
4330 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
4331 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | |
4332 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
4333 | // .. .. .. | |
4334 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | |
4335 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
4336 | // .. .. FINISH: IO PLL INIT | |
4337 | // .. FINISH: PLL SLCR REGISTERS | |
4338 | // .. START: LOCK IT BACK | |
4339 | // .. LOCK_KEY = 0X767B | |
4340 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
4341 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
4342 | // .. | |
4343 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
4344 | // .. FINISH: LOCK IT BACK | |
4345 | // FINISH: top | |
4346 | // | |
4347 | EMIT_EXIT(), | |
4348 | ||
4349 | // | |
4350 | }; | |
4351 | ||
4352 | unsigned long ps7_clock_init_data_2_0[] = { | |
4353 | // START: top | |
4354 | // .. START: SLCR SETTINGS | |
4355 | // .. UNLOCK_KEY = 0XDF0D | |
4356 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
4357 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
4358 | // .. | |
4359 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
4360 | // .. FINISH: SLCR SETTINGS | |
4361 | // .. START: CLOCK CONTROL SLCR REGISTERS | |
4362 | // .. CLKACT = 0x1 | |
4363 | // .. ==> 0XF8000128[0:0] = 0x00000001U | |
4364 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4365 | // .. DIVISOR0 = 0x23 | |
4366 | // .. ==> 0XF8000128[13:8] = 0x00000023U | |
4367 | // .. ==> MASK : 0x00003F00U VAL : 0x00002300U | |
4368 | // .. DIVISOR1 = 0x3 | |
4369 | // .. ==> 0XF8000128[25:20] = 0x00000003U | |
4370 | // .. ==> MASK : 0x03F00000U VAL : 0x00300000U | |
4371 | // .. | |
4372 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), | |
4373 | // .. CLKACT = 0x1 | |
4374 | // .. ==> 0XF8000138[0:0] = 0x00000001U | |
4375 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4376 | // .. SRCSEL = 0x0 | |
4377 | // .. ==> 0XF8000138[4:4] = 0x00000000U | |
4378 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
4379 | // .. | |
4380 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | |
4381 | // .. CLKACT = 0x1 | |
4382 | // .. ==> 0XF8000140[0:0] = 0x00000001U | |
4383 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4384 | // .. SRCSEL = 0x0 | |
4385 | // .. ==> 0XF8000140[6:4] = 0x00000000U | |
4386 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
4387 | // .. DIVISOR = 0x8 | |
4388 | // .. ==> 0XF8000140[13:8] = 0x00000008U | |
4389 | // .. ==> MASK : 0x00003F00U VAL : 0x00000800U | |
4390 | // .. DIVISOR1 = 0x1 | |
4391 | // .. ==> 0XF8000140[25:20] = 0x00000001U | |
4392 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
4393 | // .. | |
4394 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), | |
4395 | // .. CLKACT = 0x1 | |
4396 | // .. ==> 0XF800014C[0:0] = 0x00000001U | |
4397 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4398 | // .. SRCSEL = 0x0 | |
4399 | // .. ==> 0XF800014C[5:4] = 0x00000000U | |
4400 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4401 | // .. DIVISOR = 0x5 | |
4402 | // .. ==> 0XF800014C[13:8] = 0x00000005U | |
4403 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | |
4404 | // .. | |
4405 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), | |
4406 | // .. CLKACT0 = 0x1 | |
4407 | // .. ==> 0XF8000150[0:0] = 0x00000001U | |
4408 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4409 | // .. CLKACT1 = 0x0 | |
4410 | // .. ==> 0XF8000150[1:1] = 0x00000000U | |
4411 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
4412 | // .. SRCSEL = 0x0 | |
4413 | // .. ==> 0XF8000150[5:4] = 0x00000000U | |
4414 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4415 | // .. DIVISOR = 0x14 | |
4416 | // .. ==> 0XF8000150[13:8] = 0x00000014U | |
4417 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
4418 | // .. | |
4419 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), | |
4420 | // .. CLKACT0 = 0x0 | |
4421 | // .. ==> 0XF8000154[0:0] = 0x00000000U | |
4422 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4423 | // .. CLKACT1 = 0x1 | |
4424 | // .. ==> 0XF8000154[1:1] = 0x00000001U | |
4425 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
4426 | // .. SRCSEL = 0x0 | |
4427 | // .. ==> 0XF8000154[5:4] = 0x00000000U | |
4428 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4429 | // .. DIVISOR = 0x14 | |
4430 | // .. ==> 0XF8000154[13:8] = 0x00000014U | |
4431 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
4432 | // .. | |
4433 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), | |
4434 | // .. CLKACT = 0x1 | |
4435 | // .. ==> 0XF8000168[0:0] = 0x00000001U | |
4436 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4437 | // .. SRCSEL = 0x0 | |
4438 | // .. ==> 0XF8000168[5:4] = 0x00000000U | |
4439 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4440 | // .. DIVISOR = 0x5 | |
4441 | // .. ==> 0XF8000168[13:8] = 0x00000005U | |
4442 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | |
4443 | // .. | |
4444 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), | |
4445 | // .. SRCSEL = 0x0 | |
4446 | // .. ==> 0XF8000170[5:4] = 0x00000000U | |
4447 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4448 | // .. DIVISOR0 = 0xa | |
4449 | // .. ==> 0XF8000170[13:8] = 0x0000000AU | |
4450 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | |
4451 | // .. DIVISOR1 = 0x1 | |
4452 | // .. ==> 0XF8000170[25:20] = 0x00000001U | |
4453 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
4454 | // .. | |
4455 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), | |
4456 | // .. SRCSEL = 0x0 | |
4457 | // .. ==> 0XF8000180[5:4] = 0x00000000U | |
4458 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4459 | // .. DIVISOR0 = 0xa | |
4460 | // .. ==> 0XF8000180[13:8] = 0x0000000AU | |
4461 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | |
4462 | // .. DIVISOR1 = 0x1 | |
4463 | // .. ==> 0XF8000180[25:20] = 0x00000001U | |
4464 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
4465 | // .. | |
4466 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), | |
4467 | // .. SRCSEL = 0x0 | |
4468 | // .. ==> 0XF8000190[5:4] = 0x00000000U | |
4469 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4470 | // .. DIVISOR0 = 0x1e | |
4471 | // .. ==> 0XF8000190[13:8] = 0x0000001EU | |
4472 | // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U | |
4473 | // .. DIVISOR1 = 0x1 | |
4474 | // .. ==> 0XF8000190[25:20] = 0x00000001U | |
4475 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
4476 | // .. | |
4477 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), | |
4478 | // .. SRCSEL = 0x0 | |
4479 | // .. ==> 0XF80001A0[5:4] = 0x00000000U | |
4480 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
4481 | // .. DIVISOR0 = 0x14 | |
4482 | // .. ==> 0XF80001A0[13:8] = 0x00000014U | |
4483 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
4484 | // .. DIVISOR1 = 0x1 | |
4485 | // .. ==> 0XF80001A0[25:20] = 0x00000001U | |
4486 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
4487 | // .. | |
4488 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), | |
4489 | // .. CLK_621_TRUE = 0x1 | |
4490 | // .. ==> 0XF80001C4[0:0] = 0x00000001U | |
4491 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4492 | // .. | |
4493 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | |
4494 | // .. DMA_CPU_2XCLKACT = 0x1 | |
4495 | // .. ==> 0XF800012C[0:0] = 0x00000001U | |
4496 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
4497 | // .. USB0_CPU_1XCLKACT = 0x1 | |
4498 | // .. ==> 0XF800012C[2:2] = 0x00000001U | |
4499 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
4500 | // .. USB1_CPU_1XCLKACT = 0x1 | |
4501 | // .. ==> 0XF800012C[3:3] = 0x00000001U | |
4502 | // .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
4503 | // .. GEM0_CPU_1XCLKACT = 0x1 | |
4504 | // .. ==> 0XF800012C[6:6] = 0x00000001U | |
4505 | // .. ==> MASK : 0x00000040U VAL : 0x00000040U | |
4506 | // .. GEM1_CPU_1XCLKACT = 0x0 | |
4507 | // .. ==> 0XF800012C[7:7] = 0x00000000U | |
4508 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
4509 | // .. SDI0_CPU_1XCLKACT = 0x1 | |
4510 | // .. ==> 0XF800012C[10:10] = 0x00000001U | |
4511 | // .. ==> MASK : 0x00000400U VAL : 0x00000400U | |
4512 | // .. SDI1_CPU_1XCLKACT = 0x0 | |
4513 | // .. ==> 0XF800012C[11:11] = 0x00000000U | |
4514 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
4515 | // .. SPI0_CPU_1XCLKACT = 0x0 | |
4516 | // .. ==> 0XF800012C[14:14] = 0x00000000U | |
4517 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
4518 | // .. SPI1_CPU_1XCLKACT = 0x0 | |
4519 | // .. ==> 0XF800012C[15:15] = 0x00000000U | |
4520 | // .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
4521 | // .. CAN0_CPU_1XCLKACT = 0x0 | |
4522 | // .. ==> 0XF800012C[16:16] = 0x00000000U | |
4523 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
4524 | // .. CAN1_CPU_1XCLKACT = 0x0 | |
4525 | // .. ==> 0XF800012C[17:17] = 0x00000000U | |
4526 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
4527 | // .. I2C0_CPU_1XCLKACT = 0x1 | |
4528 | // .. ==> 0XF800012C[18:18] = 0x00000001U | |
4529 | // .. ==> MASK : 0x00040000U VAL : 0x00040000U | |
4530 | // .. I2C1_CPU_1XCLKACT = 0x1 | |
4531 | // .. ==> 0XF800012C[19:19] = 0x00000001U | |
4532 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
4533 | // .. UART0_CPU_1XCLKACT = 0x0 | |
4534 | // .. ==> 0XF800012C[20:20] = 0x00000000U | |
4535 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
4536 | // .. UART1_CPU_1XCLKACT = 0x1 | |
4537 | // .. ==> 0XF800012C[21:21] = 0x00000001U | |
4538 | // .. ==> MASK : 0x00200000U VAL : 0x00200000U | |
4539 | // .. GPIO_CPU_1XCLKACT = 0x1 | |
4540 | // .. ==> 0XF800012C[22:22] = 0x00000001U | |
4541 | // .. ==> MASK : 0x00400000U VAL : 0x00400000U | |
4542 | // .. LQSPI_CPU_1XCLKACT = 0x1 | |
4543 | // .. ==> 0XF800012C[23:23] = 0x00000001U | |
4544 | // .. ==> MASK : 0x00800000U VAL : 0x00800000U | |
4545 | // .. SMC_CPU_1XCLKACT = 0x1 | |
4546 | // .. ==> 0XF800012C[24:24] = 0x00000001U | |
4547 | // .. ==> MASK : 0x01000000U VAL : 0x01000000U | |
4548 | // .. | |
4549 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), | |
4550 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | |
4551 | // .. START: THIS SHOULD BE BLANK | |
4552 | // .. FINISH: THIS SHOULD BE BLANK | |
4553 | // .. START: LOCK IT BACK | |
4554 | // .. LOCK_KEY = 0X767B | |
4555 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
4556 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
4557 | // .. | |
4558 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
4559 | // .. FINISH: LOCK IT BACK | |
4560 | // FINISH: top | |
4561 | // | |
4562 | EMIT_EXIT(), | |
4563 | ||
4564 | // | |
4565 | }; | |
4566 | ||
4567 | unsigned long ps7_ddr_init_data_2_0[] = { | |
4568 | // START: top | |
4569 | // .. START: DDR INITIALIZATION | |
4570 | // .. .. START: LOCK DDR | |
4571 | // .. .. reg_ddrc_soft_rstb = 0 | |
4572 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | |
4573 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4574 | // .. .. reg_ddrc_powerdown_en = 0x0 | |
4575 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | |
4576 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
4577 | // .. .. reg_ddrc_data_bus_width = 0x0 | |
4578 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | |
4579 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | |
4580 | // .. .. reg_ddrc_burst8_refresh = 0x0 | |
4581 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | |
4582 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
4583 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | |
4584 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | |
4585 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | |
4586 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | |
4587 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | |
4588 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
4589 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | |
4590 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | |
4591 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
4592 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | |
4593 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | |
4594 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
4595 | // .. .. | |
4596 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | |
4597 | // .. .. FINISH: LOCK DDR | |
4598 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 | |
4599 | // .. .. ==> 0XF8006004[11:0] = 0x00000081U | |
4600 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U | |
4601 | // .. .. reg_ddrc_active_ranks = 0x1 | |
4602 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | |
4603 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | |
4604 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | |
4605 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | |
4606 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | |
4607 | // .. .. reg_ddrc_wr_odt_block = 0x1 | |
4608 | // .. .. ==> 0XF8006004[20:19] = 0x00000001U | |
4609 | // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U | |
4610 | // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 | |
4611 | // .. .. ==> 0XF8006004[21:21] = 0x00000000U | |
4612 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
4613 | // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 | |
4614 | // .. .. ==> 0XF8006004[26:22] = 0x00000000U | |
4615 | // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U | |
4616 | // .. .. reg_ddrc_addrmap_open_bank = 0x0 | |
4617 | // .. .. ==> 0XF8006004[27:27] = 0x00000000U | |
4618 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | |
4619 | // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 | |
4620 | // .. .. ==> 0XF8006004[28:28] = 0x00000000U | |
4621 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | |
4622 | // .. .. | |
4623 | EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), | |
4624 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | |
4625 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | |
4626 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | |
4627 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | |
4628 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | |
4629 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | |
4630 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | |
4631 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | |
4632 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | |
4633 | // .. .. | |
4634 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | |
4635 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | |
4636 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | |
4637 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | |
4638 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | |
4639 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | |
4640 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | |
4641 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | |
4642 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | |
4643 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | |
4644 | // .. .. | |
4645 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | |
4646 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | |
4647 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | |
4648 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | |
4649 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | |
4650 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | |
4651 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | |
4652 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | |
4653 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | |
4654 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | |
4655 | // .. .. | |
4656 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | |
4657 | // .. .. reg_ddrc_t_rc = 0x1a | |
4658 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | |
4659 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | |
4660 | // .. .. reg_ddrc_t_rfc_min = 0xa0 | |
4661 | // .. .. ==> 0XF8006014[13:6] = 0x000000A0U | |
4662 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U | |
4663 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | |
4664 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | |
4665 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | |
4666 | // .. .. | |
4667 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), | |
4668 | // .. .. reg_ddrc_wr2pre = 0x12 | |
4669 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | |
4670 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | |
4671 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | |
4672 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | |
4673 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | |
4674 | // .. .. reg_ddrc_t_faw = 0x16 | |
4675 | // .. .. ==> 0XF8006018[15:10] = 0x00000016U | |
4676 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U | |
4677 | // .. .. reg_ddrc_t_ras_max = 0x24 | |
4678 | // .. .. ==> 0XF8006018[21:16] = 0x00000024U | |
4679 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U | |
4680 | // .. .. reg_ddrc_t_ras_min = 0x13 | |
4681 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | |
4682 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | |
4683 | // .. .. reg_ddrc_t_cke = 0x4 | |
4684 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | |
4685 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | |
4686 | // .. .. | |
4687 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), | |
4688 | // .. .. reg_ddrc_write_latency = 0x5 | |
4689 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | |
4690 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | |
4691 | // .. .. reg_ddrc_rd2wr = 0x7 | |
4692 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | |
4693 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | |
4694 | // .. .. reg_ddrc_wr2rd = 0xe | |
4695 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | |
4696 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | |
4697 | // .. .. reg_ddrc_t_xp = 0x4 | |
4698 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | |
4699 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | |
4700 | // .. .. reg_ddrc_pad_pd = 0x0 | |
4701 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | |
4702 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | |
4703 | // .. .. reg_ddrc_rd2pre = 0x4 | |
4704 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | |
4705 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | |
4706 | // .. .. reg_ddrc_t_rcd = 0x7 | |
4707 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | |
4708 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | |
4709 | // .. .. | |
4710 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | |
4711 | // .. .. reg_ddrc_t_ccd = 0x4 | |
4712 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | |
4713 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | |
4714 | // .. .. reg_ddrc_t_rrd = 0x6 | |
4715 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | |
4716 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | |
4717 | // .. .. reg_ddrc_refresh_margin = 0x2 | |
4718 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | |
4719 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
4720 | // .. .. reg_ddrc_t_rp = 0x7 | |
4721 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | |
4722 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | |
4723 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | |
4724 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | |
4725 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | |
4726 | // .. .. reg_ddrc_sdram = 0x1 | |
4727 | // .. .. ==> 0XF8006020[21:21] = 0x00000001U | |
4728 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | |
4729 | // .. .. reg_ddrc_mobile = 0x0 | |
4730 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | |
4731 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
4732 | // .. .. reg_ddrc_clock_stop_en = 0x0 | |
4733 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | |
4734 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
4735 | // .. .. reg_ddrc_read_latency = 0x7 | |
4736 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | |
4737 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | |
4738 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | |
4739 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | |
4740 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | |
4741 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | |
4742 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | |
4743 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | |
4744 | // .. .. reg_ddrc_loopback = 0x0 | |
4745 | // .. .. ==> 0XF8006020[31:31] = 0x00000000U | |
4746 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | |
4747 | // .. .. | |
4748 | EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), | |
4749 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | |
4750 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | |
4751 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4752 | // .. .. reg_ddrc_prefer_write = 0x0 | |
4753 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | |
4754 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
4755 | // .. .. reg_ddrc_max_rank_rd = 0xf | |
4756 | // .. .. ==> 0XF8006024[5:2] = 0x0000000FU | |
4757 | // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU | |
4758 | // .. .. reg_ddrc_mr_wr = 0x0 | |
4759 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | |
4760 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
4761 | // .. .. reg_ddrc_mr_addr = 0x0 | |
4762 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | |
4763 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | |
4764 | // .. .. reg_ddrc_mr_data = 0x0 | |
4765 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | |
4766 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | |
4767 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | |
4768 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | |
4769 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
4770 | // .. .. reg_ddrc_mr_type = 0x0 | |
4771 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | |
4772 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | |
4773 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | |
4774 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | |
4775 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | |
4776 | // .. .. | |
4777 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), | |
4778 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | |
4779 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | |
4780 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | |
4781 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | |
4782 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | |
4783 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | |
4784 | // .. .. reg_ddrc_t_mrd = 0x4 | |
4785 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | |
4786 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | |
4787 | // .. .. | |
4788 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | |
4789 | // .. .. reg_ddrc_emr2 = 0x8 | |
4790 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | |
4791 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | |
4792 | // .. .. reg_ddrc_emr3 = 0x0 | |
4793 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | |
4794 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | |
4795 | // .. .. | |
4796 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | |
4797 | // .. .. reg_ddrc_mr = 0x930 | |
4798 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | |
4799 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | |
4800 | // .. .. reg_ddrc_emr = 0x4 | |
4801 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | |
4802 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | |
4803 | // .. .. | |
4804 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | |
4805 | // .. .. reg_ddrc_burst_rdwr = 0x4 | |
4806 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | |
4807 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | |
4808 | // .. .. reg_ddrc_pre_cke_x1024 = 0x105 | |
4809 | // .. .. ==> 0XF8006034[13:4] = 0x00000105U | |
4810 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U | |
4811 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | |
4812 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | |
4813 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | |
4814 | // .. .. reg_ddrc_burstchop = 0x0 | |
4815 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | |
4816 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | |
4817 | // .. .. | |
4818 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), | |
4819 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | |
4820 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | |
4821 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
4822 | // .. .. reg_ddrc_dis_dq = 0x0 | |
4823 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | |
4824 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
4825 | // .. .. reg_phy_debug_mode = 0x0 | |
4826 | // .. .. ==> 0XF8006038[6:6] = 0x00000000U | |
4827 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
4828 | // .. .. reg_phy_wr_level_start = 0x0 | |
4829 | // .. .. ==> 0XF8006038[7:7] = 0x00000000U | |
4830 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
4831 | // .. .. reg_phy_rd_level_start = 0x0 | |
4832 | // .. .. ==> 0XF8006038[8:8] = 0x00000000U | |
4833 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
4834 | // .. .. reg_phy_dq0_wait_t = 0x0 | |
4835 | // .. .. ==> 0XF8006038[12:9] = 0x00000000U | |
4836 | // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U | |
4837 | // .. .. | |
4838 | EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), | |
4839 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | |
4840 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | |
4841 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | |
4842 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | |
4843 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | |
4844 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | |
4845 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | |
4846 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | |
4847 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | |
4848 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | |
4849 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | |
4850 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | |
4851 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | |
4852 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | |
4853 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | |
4854 | // .. .. | |
4855 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | |
4856 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | |
4857 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | |
4858 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
4859 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | |
4860 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | |
4861 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
4862 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | |
4863 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | |
4864 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | |
4865 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | |
4866 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | |
4867 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | |
4868 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | |
4869 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | |
4870 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | |
4871 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | |
4872 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | |
4873 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | |
4874 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | |
4875 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | |
4876 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | |
4877 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | |
4878 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | |
4879 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | |
4880 | // .. .. | |
4881 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | |
4882 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | |
4883 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | |
4884 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | |
4885 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | |
4886 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | |
4887 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | |
4888 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | |
4889 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | |
4890 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | |
4891 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | |
4892 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | |
4893 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | |
4894 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | |
4895 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | |
4896 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | |
4897 | // .. .. reg_ddrc_addrmap_row_b14 = 0x6 | |
4898 | // .. .. ==> 0XF8006044[23:20] = 0x00000006U | |
4899 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U | |
4900 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | |
4901 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | |
4902 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | |
4903 | // .. .. | |
4904 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), | |
4905 | // .. .. reg_ddrc_rank0_rd_odt = 0x0 | |
4906 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | |
4907 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | |
4908 | // .. .. reg_ddrc_rank0_wr_odt = 0x1 | |
4909 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | |
4910 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | |
4911 | // .. .. reg_ddrc_rank1_rd_odt = 0x1 | |
4912 | // .. .. ==> 0XF8006048[8:6] = 0x00000001U | |
4913 | // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U | |
4914 | // .. .. reg_ddrc_rank1_wr_odt = 0x1 | |
4915 | // .. .. ==> 0XF8006048[11:9] = 0x00000001U | |
4916 | // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
4917 | // .. .. reg_phy_rd_local_odt = 0x0 | |
4918 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | |
4919 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | |
4920 | // .. .. reg_phy_wr_local_odt = 0x3 | |
4921 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | |
4922 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | |
4923 | // .. .. reg_phy_idle_local_odt = 0x3 | |
4924 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | |
4925 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | |
4926 | // .. .. reg_ddrc_rank2_rd_odt = 0x0 | |
4927 | // .. .. ==> 0XF8006048[20:18] = 0x00000000U | |
4928 | // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U | |
4929 | // .. .. reg_ddrc_rank2_wr_odt = 0x0 | |
4930 | // .. .. ==> 0XF8006048[23:21] = 0x00000000U | |
4931 | // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U | |
4932 | // .. .. reg_ddrc_rank3_rd_odt = 0x0 | |
4933 | // .. .. ==> 0XF8006048[26:24] = 0x00000000U | |
4934 | // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
4935 | // .. .. reg_ddrc_rank3_wr_odt = 0x0 | |
4936 | // .. .. ==> 0XF8006048[29:27] = 0x00000000U | |
4937 | // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U | |
4938 | // .. .. | |
4939 | EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), | |
4940 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | |
4941 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | |
4942 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
4943 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | |
4944 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | |
4945 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
4946 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | |
4947 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | |
4948 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | |
4949 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | |
4950 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | |
4951 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
4952 | // .. .. reg_phy_use_fixed_re = 0x1 | |
4953 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | |
4954 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | |
4955 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | |
4956 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | |
4957 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
4958 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | |
4959 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | |
4960 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
4961 | // .. .. reg_phy_clk_stall_level = 0x0 | |
4962 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | |
4963 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
4964 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | |
4965 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | |
4966 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | |
4967 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | |
4968 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | |
4969 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | |
4970 | // .. .. | |
4971 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | |
4972 | // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 | |
4973 | // .. .. ==> 0XF8006058[7:0] = 0x00000001U | |
4974 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U | |
4975 | // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 | |
4976 | // .. .. ==> 0XF8006058[15:8] = 0x00000001U | |
4977 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U | |
4978 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | |
4979 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | |
4980 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
4981 | // .. .. | |
4982 | EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), | |
4983 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | |
4984 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | |
4985 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | |
4986 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | |
4987 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | |
4988 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
4989 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | |
4990 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | |
4991 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | |
4992 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | |
4993 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | |
4994 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | |
4995 | // .. .. | |
4996 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | |
4997 | // .. .. reg_ddrc_pageclose = 0x0 | |
4998 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | |
4999 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5000 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | |
5001 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | |
5002 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | |
5003 | // .. .. reg_ddrc_auto_pre_en = 0x0 | |
5004 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | |
5005 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
5006 | // .. .. reg_ddrc_refresh_update_level = 0x0 | |
5007 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | |
5008 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
5009 | // .. .. reg_ddrc_dis_wc = 0x0 | |
5010 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | |
5011 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
5012 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | |
5013 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | |
5014 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5015 | // .. .. reg_ddrc_selfref_en = 0x0 | |
5016 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | |
5017 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
5018 | // .. .. | |
5019 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | |
5020 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | |
5021 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | |
5022 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | |
5023 | // .. .. reg_arb_go2critical_en = 0x1 | |
5024 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | |
5025 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | |
5026 | // .. .. | |
5027 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | |
5028 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | |
5029 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | |
5030 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | |
5031 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | |
5032 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | |
5033 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | |
5034 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | |
5035 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | |
5036 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | |
5037 | // .. .. | |
5038 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | |
5039 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | |
5040 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | |
5041 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | |
5042 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | |
5043 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | |
5044 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | |
5045 | // .. .. | |
5046 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | |
5047 | // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 | |
5048 | // .. .. ==> 0XF8006078[3:0] = 0x00000001U | |
5049 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U | |
5050 | // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 | |
5051 | // .. .. ==> 0XF8006078[7:4] = 0x00000001U | |
5052 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U | |
5053 | // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 | |
5054 | // .. .. ==> 0XF8006078[11:8] = 0x00000001U | |
5055 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U | |
5056 | // .. .. reg_ddrc_t_cksre = 0x6 | |
5057 | // .. .. ==> 0XF8006078[15:12] = 0x00000006U | |
5058 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | |
5059 | // .. .. reg_ddrc_t_cksrx = 0x6 | |
5060 | // .. .. ==> 0XF8006078[19:16] = 0x00000006U | |
5061 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | |
5062 | // .. .. reg_ddrc_t_ckesr = 0x4 | |
5063 | // .. .. ==> 0XF8006078[25:20] = 0x00000004U | |
5064 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U | |
5065 | // .. .. | |
5066 | EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), | |
5067 | // .. .. reg_ddrc_t_ckpde = 0x2 | |
5068 | // .. .. ==> 0XF800607C[3:0] = 0x00000002U | |
5069 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U | |
5070 | // .. .. reg_ddrc_t_ckpdx = 0x2 | |
5071 | // .. .. ==> 0XF800607C[7:4] = 0x00000002U | |
5072 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
5073 | // .. .. reg_ddrc_t_ckdpde = 0x2 | |
5074 | // .. .. ==> 0XF800607C[11:8] = 0x00000002U | |
5075 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
5076 | // .. .. reg_ddrc_t_ckdpdx = 0x2 | |
5077 | // .. .. ==> 0XF800607C[15:12] = 0x00000002U | |
5078 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U | |
5079 | // .. .. reg_ddrc_t_ckcsx = 0x3 | |
5080 | // .. .. ==> 0XF800607C[19:16] = 0x00000003U | |
5081 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U | |
5082 | // .. .. | |
5083 | EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), | |
5084 | // .. .. refresh_timer0_start_value_x32 = 0x0 | |
5085 | // .. .. ==> 0XF80060A0[11:0] = 0x00000000U | |
5086 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U | |
5087 | // .. .. refresh_timer1_start_value_x32 = 0x8 | |
5088 | // .. .. ==> 0XF80060A0[23:12] = 0x00000008U | |
5089 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U | |
5090 | // .. .. | |
5091 | EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), | |
5092 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | |
5093 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | |
5094 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5095 | // .. .. reg_ddrc_ddr3 = 0x1 | |
5096 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | |
5097 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
5098 | // .. .. reg_ddrc_t_mod = 0x200 | |
5099 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | |
5100 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | |
5101 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | |
5102 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | |
5103 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | |
5104 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | |
5105 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | |
5106 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | |
5107 | // .. .. | |
5108 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | |
5109 | // .. .. t_zq_short_interval_x1024 = 0xcb73 | |
5110 | // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U | |
5111 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U | |
5112 | // .. .. dram_rstn_x1024 = 0x69 | |
5113 | // .. .. ==> 0XF80060A8[27:20] = 0x00000069U | |
5114 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U | |
5115 | // .. .. | |
5116 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), | |
5117 | // .. .. deeppowerdown_en = 0x0 | |
5118 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | |
5119 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5120 | // .. .. deeppowerdown_to_x1024 = 0xff | |
5121 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | |
5122 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | |
5123 | // .. .. | |
5124 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | |
5125 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | |
5126 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | |
5127 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | |
5128 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | |
5129 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | |
5130 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | |
5131 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | |
5132 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | |
5133 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
5134 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | |
5135 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | |
5136 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
5137 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | |
5138 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | |
5139 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | |
5140 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | |
5141 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | |
5142 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | |
5143 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | |
5144 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | |
5145 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
5146 | // .. .. | |
5147 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | |
5148 | // .. .. reg_ddrc_2t_delay = 0x0 | |
5149 | // .. .. ==> 0XF80060B4[8:0] = 0x00000000U | |
5150 | // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U | |
5151 | // .. .. reg_ddrc_skip_ocd = 0x1 | |
5152 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | |
5153 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | |
5154 | // .. .. reg_ddrc_dis_pre_bypass = 0x0 | |
5155 | // .. .. ==> 0XF80060B4[10:10] = 0x00000000U | |
5156 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5157 | // .. .. | |
5158 | EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), | |
5159 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | |
5160 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | |
5161 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | |
5162 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | |
5163 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | |
5164 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | |
5165 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | |
5166 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | |
5167 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | |
5168 | // .. .. | |
5169 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | |
5170 | // .. .. START: RESET ECC ERROR | |
5171 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | |
5172 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | |
5173 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5174 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | |
5175 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | |
5176 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
5177 | // .. .. | |
5178 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | |
5179 | // .. .. FINISH: RESET ECC ERROR | |
5180 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | |
5181 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | |
5182 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5183 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | |
5184 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | |
5185 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5186 | // .. .. | |
5187 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | |
5188 | // .. .. CORR_ECC_LOG_VALID = 0x0 | |
5189 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | |
5190 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5191 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | |
5192 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | |
5193 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | |
5194 | // .. .. | |
5195 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | |
5196 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | |
5197 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | |
5198 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5199 | // .. .. | |
5200 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | |
5201 | // .. .. STAT_NUM_CORR_ERR = 0x0 | |
5202 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | |
5203 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | |
5204 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | |
5205 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | |
5206 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | |
5207 | // .. .. | |
5208 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | |
5209 | // .. .. reg_ddrc_ecc_mode = 0x0 | |
5210 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | |
5211 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | |
5212 | // .. .. reg_ddrc_dis_scrub = 0x1 | |
5213 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | |
5214 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
5215 | // .. .. | |
5216 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | |
5217 | // .. .. reg_phy_dif_on = 0x0 | |
5218 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | |
5219 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
5220 | // .. .. reg_phy_dif_off = 0x0 | |
5221 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | |
5222 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
5223 | // .. .. | |
5224 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | |
5225 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
5226 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | |
5227 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5228 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
5229 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | |
5230 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5231 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
5232 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | |
5233 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5234 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
5235 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | |
5236 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5237 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
5238 | // .. .. ==> 0XF8006118[4:4] = 0x00000000U | |
5239 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5240 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
5241 | // .. .. ==> 0XF8006118[5:5] = 0x00000000U | |
5242 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
5243 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
5244 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | |
5245 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
5246 | // .. .. reg_phy_bist_err_clr = 0x0 | |
5247 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | |
5248 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
5249 | // .. .. reg_phy_dq_offset = 0x40 | |
5250 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | |
5251 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
5252 | // .. .. | |
5253 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), | |
5254 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
5255 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | |
5256 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5257 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
5258 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | |
5259 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5260 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
5261 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | |
5262 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5263 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
5264 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | |
5265 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5266 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
5267 | // .. .. ==> 0XF800611C[4:4] = 0x00000000U | |
5268 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5269 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
5270 | // .. .. ==> 0XF800611C[5:5] = 0x00000000U | |
5271 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
5272 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
5273 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | |
5274 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
5275 | // .. .. reg_phy_bist_err_clr = 0x0 | |
5276 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | |
5277 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
5278 | // .. .. reg_phy_dq_offset = 0x40 | |
5279 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | |
5280 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
5281 | // .. .. | |
5282 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), | |
5283 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
5284 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | |
5285 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5286 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
5287 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | |
5288 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5289 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
5290 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | |
5291 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5292 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
5293 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | |
5294 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5295 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
5296 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | |
5297 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5298 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
5299 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | |
5300 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
5301 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
5302 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | |
5303 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
5304 | // .. .. reg_phy_bist_err_clr = 0x0 | |
5305 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | |
5306 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
5307 | // .. .. reg_phy_dq_offset = 0x40 | |
5308 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | |
5309 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
5310 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
5311 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | |
5312 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5313 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
5314 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | |
5315 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5316 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
5317 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | |
5318 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5319 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
5320 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | |
5321 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5322 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
5323 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | |
5324 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5325 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
5326 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | |
5327 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
5328 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
5329 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | |
5330 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
5331 | // .. .. reg_phy_bist_err_clr = 0x0 | |
5332 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | |
5333 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
5334 | // .. .. reg_phy_dq_offset = 0x40 | |
5335 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | |
5336 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
5337 | // .. .. | |
5338 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), | |
5339 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
5340 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | |
5341 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5342 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
5343 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | |
5344 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5345 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
5346 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | |
5347 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5348 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
5349 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | |
5350 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5351 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
5352 | // .. .. ==> 0XF8006124[4:4] = 0x00000000U | |
5353 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5354 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
5355 | // .. .. ==> 0XF8006124[5:5] = 0x00000000U | |
5356 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
5357 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
5358 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | |
5359 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
5360 | // .. .. reg_phy_bist_err_clr = 0x0 | |
5361 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | |
5362 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
5363 | // .. .. reg_phy_dq_offset = 0x40 | |
5364 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | |
5365 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
5366 | // .. .. | |
5367 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), | |
5368 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | |
5369 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | |
5370 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | |
5371 | // .. .. reg_phy_gatelvl_init_ratio = 0xb0 | |
5372 | // .. .. ==> 0XF800612C[19:10] = 0x000000B0U | |
5373 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U | |
5374 | // .. .. | |
5375 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), | |
5376 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | |
5377 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | |
5378 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | |
5379 | // .. .. reg_phy_gatelvl_init_ratio = 0xb1 | |
5380 | // .. .. ==> 0XF8006130[19:10] = 0x000000B1U | |
5381 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U | |
5382 | // .. .. | |
5383 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), | |
5384 | // .. .. reg_phy_wrlvl_init_ratio = 0x3 | |
5385 | // .. .. ==> 0XF8006134[9:0] = 0x00000003U | |
5386 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U | |
5387 | // .. .. reg_phy_gatelvl_init_ratio = 0xbc | |
5388 | // .. .. ==> 0XF8006134[19:10] = 0x000000BCU | |
5389 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U | |
5390 | // .. .. | |
5391 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), | |
5392 | // .. .. reg_phy_wrlvl_init_ratio = 0x3 | |
5393 | // .. .. ==> 0XF8006138[9:0] = 0x00000003U | |
5394 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U | |
5395 | // .. .. reg_phy_gatelvl_init_ratio = 0xbb | |
5396 | // .. .. ==> 0XF8006138[19:10] = 0x000000BBU | |
5397 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U | |
5398 | // .. .. | |
5399 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), | |
5400 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
5401 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | |
5402 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
5403 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
5404 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | |
5405 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5406 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
5407 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | |
5408 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5409 | // .. .. | |
5410 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | |
5411 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
5412 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | |
5413 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
5414 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
5415 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | |
5416 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5417 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
5418 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | |
5419 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5420 | // .. .. | |
5421 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | |
5422 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
5423 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | |
5424 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
5425 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
5426 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | |
5427 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5428 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
5429 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | |
5430 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5431 | // .. .. | |
5432 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | |
5433 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
5434 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | |
5435 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
5436 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
5437 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | |
5438 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5439 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
5440 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | |
5441 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5442 | // .. .. | |
5443 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | |
5444 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | |
5445 | // .. .. ==> 0XF8006154[9:0] = 0x00000077U | |
5446 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | |
5447 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
5448 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | |
5449 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5450 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
5451 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | |
5452 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5453 | // .. .. | |
5454 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), | |
5455 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | |
5456 | // .. .. ==> 0XF8006158[9:0] = 0x00000077U | |
5457 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | |
5458 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
5459 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | |
5460 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5461 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
5462 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | |
5463 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5464 | // .. .. | |
5465 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), | |
5466 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 | |
5467 | // .. .. ==> 0XF800615C[9:0] = 0x00000083U | |
5468 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U | |
5469 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
5470 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | |
5471 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5472 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
5473 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | |
5474 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5475 | // .. .. | |
5476 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), | |
5477 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 | |
5478 | // .. .. ==> 0XF8006160[9:0] = 0x00000083U | |
5479 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U | |
5480 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
5481 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | |
5482 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5483 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
5484 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | |
5485 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5486 | // .. .. | |
5487 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), | |
5488 | // .. .. reg_phy_fifo_we_slave_ratio = 0x105 | |
5489 | // .. .. ==> 0XF8006168[10:0] = 0x00000105U | |
5490 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U | |
5491 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
5492 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | |
5493 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5494 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
5495 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | |
5496 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
5497 | // .. .. | |
5498 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), | |
5499 | // .. .. reg_phy_fifo_we_slave_ratio = 0x106 | |
5500 | // .. .. ==> 0XF800616C[10:0] = 0x00000106U | |
5501 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U | |
5502 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
5503 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | |
5504 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5505 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
5506 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | |
5507 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
5508 | // .. .. | |
5509 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), | |
5510 | // .. .. reg_phy_fifo_we_slave_ratio = 0x111 | |
5511 | // .. .. ==> 0XF8006170[10:0] = 0x00000111U | |
5512 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U | |
5513 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
5514 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | |
5515 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5516 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
5517 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | |
5518 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
5519 | // .. .. | |
5520 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), | |
5521 | // .. .. reg_phy_fifo_we_slave_ratio = 0x110 | |
5522 | // .. .. ==> 0XF8006174[10:0] = 0x00000110U | |
5523 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U | |
5524 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
5525 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | |
5526 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5527 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
5528 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | |
5529 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
5530 | // .. .. | |
5531 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), | |
5532 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | |
5533 | // .. .. ==> 0XF800617C[9:0] = 0x000000B7U | |
5534 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | |
5535 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
5536 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | |
5537 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5538 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
5539 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | |
5540 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5541 | // .. .. | |
5542 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), | |
5543 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | |
5544 | // .. .. ==> 0XF8006180[9:0] = 0x000000B7U | |
5545 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | |
5546 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
5547 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | |
5548 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5549 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
5550 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | |
5551 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5552 | // .. .. | |
5553 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), | |
5554 | // .. .. reg_phy_wr_data_slave_ratio = 0xc3 | |
5555 | // .. .. ==> 0XF8006184[9:0] = 0x000000C3U | |
5556 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U | |
5557 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
5558 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | |
5559 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5560 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
5561 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | |
5562 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5563 | // .. .. | |
5564 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), | |
5565 | // .. .. reg_phy_wr_data_slave_ratio = 0xc3 | |
5566 | // .. .. ==> 0XF8006188[9:0] = 0x000000C3U | |
5567 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U | |
5568 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
5569 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | |
5570 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
5571 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
5572 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | |
5573 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
5574 | // .. .. | |
5575 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), | |
5576 | // .. .. reg_phy_loopback = 0x0 | |
5577 | // .. .. ==> 0XF8006190[0:0] = 0x00000000U | |
5578 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5579 | // .. .. reg_phy_bl2 = 0x0 | |
5580 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | |
5581 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5582 | // .. .. reg_phy_at_spd_atpg = 0x0 | |
5583 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | |
5584 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5585 | // .. .. reg_phy_bist_enable = 0x0 | |
5586 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | |
5587 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5588 | // .. .. reg_phy_bist_force_err = 0x0 | |
5589 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | |
5590 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5591 | // .. .. reg_phy_bist_mode = 0x0 | |
5592 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | |
5593 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
5594 | // .. .. reg_phy_invert_clkout = 0x1 | |
5595 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | |
5596 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
5597 | // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 | |
5598 | // .. .. ==> 0XF8006190[8:8] = 0x00000000U | |
5599 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
5600 | // .. .. reg_phy_sel_logic = 0x0 | |
5601 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | |
5602 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
5603 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | |
5604 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | |
5605 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | |
5606 | // .. .. reg_phy_ctrl_slave_force = 0x0 | |
5607 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | |
5608 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
5609 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | |
5610 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | |
5611 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | |
5612 | // .. .. reg_phy_use_rank0_delays = 0x1 | |
5613 | // .. .. ==> 0XF8006190[28:28] = 0x00000001U | |
5614 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
5615 | // .. .. reg_phy_lpddr = 0x0 | |
5616 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | |
5617 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | |
5618 | // .. .. reg_phy_cmd_latency = 0x0 | |
5619 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | |
5620 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | |
5621 | // .. .. reg_phy_int_lpbk = 0x0 | |
5622 | // .. .. ==> 0XF8006190[31:31] = 0x00000000U | |
5623 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | |
5624 | // .. .. | |
5625 | EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), | |
5626 | // .. .. reg_phy_wr_rl_delay = 0x2 | |
5627 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | |
5628 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | |
5629 | // .. .. reg_phy_rd_rl_delay = 0x4 | |
5630 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | |
5631 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | |
5632 | // .. .. reg_phy_dll_lock_diff = 0xf | |
5633 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | |
5634 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | |
5635 | // .. .. reg_phy_use_wr_level = 0x1 | |
5636 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | |
5637 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | |
5638 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | |
5639 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | |
5640 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | |
5641 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | |
5642 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | |
5643 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | |
5644 | // .. .. reg_phy_dis_calib_rst = 0x0 | |
5645 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | |
5646 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5647 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | |
5648 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | |
5649 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | |
5650 | // .. .. | |
5651 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | |
5652 | // .. .. reg_arb_page_addr_mask = 0x0 | |
5653 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | |
5654 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | |
5655 | // .. .. | |
5656 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | |
5657 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
5658 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | |
5659 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5660 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
5661 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | |
5662 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5663 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
5664 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | |
5665 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5666 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
5667 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | |
5668 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5669 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
5670 | // .. .. ==> 0XF8006208[19:19] = 0x00000001U | |
5671 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
5672 | // .. .. | |
5673 | EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), | |
5674 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
5675 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | |
5676 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5677 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
5678 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | |
5679 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5680 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
5681 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | |
5682 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5683 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
5684 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | |
5685 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5686 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
5687 | // .. .. ==> 0XF800620C[19:19] = 0x00000001U | |
5688 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
5689 | // .. .. | |
5690 | EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), | |
5691 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
5692 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | |
5693 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5694 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
5695 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | |
5696 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5697 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
5698 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | |
5699 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5700 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
5701 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | |
5702 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5703 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
5704 | // .. .. ==> 0XF8006210[19:19] = 0x00000001U | |
5705 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
5706 | // .. .. | |
5707 | EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), | |
5708 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
5709 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | |
5710 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5711 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
5712 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | |
5713 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5714 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
5715 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | |
5716 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5717 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
5718 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | |
5719 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5720 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
5721 | // .. .. ==> 0XF8006214[19:19] = 0x00000001U | |
5722 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
5723 | // .. .. | |
5724 | EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), | |
5725 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
5726 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | |
5727 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5728 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
5729 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | |
5730 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5731 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
5732 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | |
5733 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5734 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
5735 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | |
5736 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5737 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
5738 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | |
5739 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
5740 | // .. .. | |
5741 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | |
5742 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
5743 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | |
5744 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5745 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
5746 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | |
5747 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5748 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
5749 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | |
5750 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5751 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
5752 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | |
5753 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5754 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
5755 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | |
5756 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
5757 | // .. .. | |
5758 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | |
5759 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
5760 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | |
5761 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5762 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
5763 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | |
5764 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5765 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
5766 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | |
5767 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5768 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
5769 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | |
5770 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5771 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
5772 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | |
5773 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
5774 | // .. .. | |
5775 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | |
5776 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
5777 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | |
5778 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
5779 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
5780 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | |
5781 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5782 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
5783 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | |
5784 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
5785 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
5786 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | |
5787 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
5788 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
5789 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | |
5790 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
5791 | // .. .. | |
5792 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | |
5793 | // .. .. reg_ddrc_lpddr2 = 0x0 | |
5794 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | |
5795 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5796 | // .. .. reg_ddrc_per_bank_refresh = 0x0 | |
5797 | // .. .. ==> 0XF80062A8[1:1] = 0x00000000U | |
5798 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5799 | // .. .. reg_ddrc_derate_enable = 0x0 | |
5800 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | |
5801 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
5802 | // .. .. reg_ddrc_mr4_margin = 0x0 | |
5803 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | |
5804 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | |
5805 | // .. .. | |
5806 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), | |
5807 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | |
5808 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | |
5809 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | |
5810 | // .. .. | |
5811 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | |
5812 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | |
5813 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | |
5814 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | |
5815 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | |
5816 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | |
5817 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | |
5818 | // .. .. reg_ddrc_t_mrw = 0x5 | |
5819 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | |
5820 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | |
5821 | // .. .. | |
5822 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | |
5823 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 | |
5824 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U | |
5825 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U | |
5826 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | |
5827 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | |
5828 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | |
5829 | // .. .. | |
5830 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), | |
5831 | // .. .. START: POLL ON DCI STATUS | |
5832 | // .. .. DONE = 1 | |
5833 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | |
5834 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | |
5835 | // .. .. | |
5836 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | |
5837 | // .. .. FINISH: POLL ON DCI STATUS | |
5838 | // .. .. START: UNLOCK DDR | |
5839 | // .. .. reg_ddrc_soft_rstb = 0x1 | |
5840 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | |
5841 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
5842 | // .. .. reg_ddrc_powerdown_en = 0x0 | |
5843 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | |
5844 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
5845 | // .. .. reg_ddrc_data_bus_width = 0x0 | |
5846 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | |
5847 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | |
5848 | // .. .. reg_ddrc_burst8_refresh = 0x0 | |
5849 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | |
5850 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
5851 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | |
5852 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | |
5853 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | |
5854 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | |
5855 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | |
5856 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
5857 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | |
5858 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | |
5859 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
5860 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | |
5861 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | |
5862 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
5863 | // .. .. | |
5864 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | |
5865 | // .. .. FINISH: UNLOCK DDR | |
5866 | // .. .. START: CHECK DDR STATUS | |
5867 | // .. .. ddrc_reg_operating_mode = 1 | |
5868 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | |
5869 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | |
5870 | // .. .. | |
5871 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | |
5872 | // .. .. FINISH: CHECK DDR STATUS | |
5873 | // .. FINISH: DDR INITIALIZATION | |
5874 | // FINISH: top | |
5875 | // | |
5876 | EMIT_EXIT(), | |
5877 | ||
5878 | // | |
5879 | }; | |
5880 | ||
5881 | unsigned long ps7_mio_init_data_2_0[] = { | |
5882 | // START: top | |
5883 | // .. START: SLCR SETTINGS | |
5884 | // .. UNLOCK_KEY = 0XDF0D | |
5885 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
5886 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
5887 | // .. | |
5888 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
5889 | // .. FINISH: SLCR SETTINGS | |
5890 | // .. START: OCM REMAPPING | |
5891 | // .. FINISH: OCM REMAPPING | |
5892 | // .. START: DDRIOB SETTINGS | |
5893 | // .. INP_POWER = 0x0 | |
5894 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | |
5895 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5896 | // .. INP_TYPE = 0x0 | |
5897 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | |
5898 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
5899 | // .. DCI_UPDATE = 0x0 | |
5900 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | |
5901 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5902 | // .. TERM_EN = 0x0 | |
5903 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | |
5904 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5905 | // .. DCR_TYPE = 0x0 | |
5906 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | |
5907 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
5908 | // .. IBUF_DISABLE_MODE = 0x0 | |
5909 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | |
5910 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
5911 | // .. TERM_DISABLE_MODE = 0x0 | |
5912 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | |
5913 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
5914 | // .. OUTPUT_EN = 0x3 | |
5915 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | |
5916 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
5917 | // .. PULLUP_EN = 0x0 | |
5918 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | |
5919 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5920 | // .. | |
5921 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | |
5922 | // .. INP_POWER = 0x0 | |
5923 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | |
5924 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5925 | // .. INP_TYPE = 0x0 | |
5926 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | |
5927 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
5928 | // .. DCI_UPDATE = 0x0 | |
5929 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | |
5930 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5931 | // .. TERM_EN = 0x0 | |
5932 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | |
5933 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
5934 | // .. DCR_TYPE = 0x0 | |
5935 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | |
5936 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
5937 | // .. IBUF_DISABLE_MODE = 0x0 | |
5938 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | |
5939 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
5940 | // .. TERM_DISABLE_MODE = 0x0 | |
5941 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | |
5942 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
5943 | // .. OUTPUT_EN = 0x3 | |
5944 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | |
5945 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
5946 | // .. PULLUP_EN = 0x0 | |
5947 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | |
5948 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5949 | // .. | |
5950 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | |
5951 | // .. INP_POWER = 0x0 | |
5952 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | |
5953 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5954 | // .. INP_TYPE = 0x1 | |
5955 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | |
5956 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | |
5957 | // .. DCI_UPDATE = 0x0 | |
5958 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | |
5959 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5960 | // .. TERM_EN = 0x1 | |
5961 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | |
5962 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
5963 | // .. DCR_TYPE = 0x3 | |
5964 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | |
5965 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
5966 | // .. IBUF_DISABLE_MODE = 0 | |
5967 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | |
5968 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
5969 | // .. TERM_DISABLE_MODE = 0 | |
5970 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | |
5971 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
5972 | // .. OUTPUT_EN = 0x3 | |
5973 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | |
5974 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
5975 | // .. PULLUP_EN = 0x0 | |
5976 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | |
5977 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
5978 | // .. | |
5979 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | |
5980 | // .. INP_POWER = 0x0 | |
5981 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | |
5982 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
5983 | // .. INP_TYPE = 0x1 | |
5984 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | |
5985 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | |
5986 | // .. DCI_UPDATE = 0x0 | |
5987 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | |
5988 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
5989 | // .. TERM_EN = 0x1 | |
5990 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | |
5991 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
5992 | // .. DCR_TYPE = 0x3 | |
5993 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | |
5994 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
5995 | // .. IBUF_DISABLE_MODE = 0 | |
5996 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | |
5997 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
5998 | // .. TERM_DISABLE_MODE = 0 | |
5999 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | |
6000 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6001 | // .. OUTPUT_EN = 0x3 | |
6002 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | |
6003 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
6004 | // .. PULLUP_EN = 0x0 | |
6005 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | |
6006 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
6007 | // .. | |
6008 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | |
6009 | // .. INP_POWER = 0x0 | |
6010 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | |
6011 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6012 | // .. INP_TYPE = 0x2 | |
6013 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | |
6014 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | |
6015 | // .. DCI_UPDATE = 0x0 | |
6016 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | |
6017 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
6018 | // .. TERM_EN = 0x1 | |
6019 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | |
6020 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
6021 | // .. DCR_TYPE = 0x3 | |
6022 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | |
6023 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
6024 | // .. IBUF_DISABLE_MODE = 0 | |
6025 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | |
6026 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
6027 | // .. TERM_DISABLE_MODE = 0 | |
6028 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | |
6029 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6030 | // .. OUTPUT_EN = 0x3 | |
6031 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | |
6032 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
6033 | // .. PULLUP_EN = 0x0 | |
6034 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | |
6035 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
6036 | // .. | |
6037 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | |
6038 | // .. INP_POWER = 0x0 | |
6039 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | |
6040 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6041 | // .. INP_TYPE = 0x2 | |
6042 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | |
6043 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | |
6044 | // .. DCI_UPDATE = 0x0 | |
6045 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | |
6046 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
6047 | // .. TERM_EN = 0x1 | |
6048 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | |
6049 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
6050 | // .. DCR_TYPE = 0x3 | |
6051 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | |
6052 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
6053 | // .. IBUF_DISABLE_MODE = 0 | |
6054 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | |
6055 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
6056 | // .. TERM_DISABLE_MODE = 0 | |
6057 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | |
6058 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6059 | // .. OUTPUT_EN = 0x3 | |
6060 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | |
6061 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
6062 | // .. PULLUP_EN = 0x0 | |
6063 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | |
6064 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
6065 | // .. | |
6066 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | |
6067 | // .. INP_POWER = 0x0 | |
6068 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | |
6069 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6070 | // .. INP_TYPE = 0x0 | |
6071 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | |
6072 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
6073 | // .. DCI_UPDATE = 0x0 | |
6074 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | |
6075 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
6076 | // .. TERM_EN = 0x0 | |
6077 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | |
6078 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
6079 | // .. DCR_TYPE = 0x0 | |
6080 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | |
6081 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
6082 | // .. IBUF_DISABLE_MODE = 0x0 | |
6083 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | |
6084 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
6085 | // .. TERM_DISABLE_MODE = 0x0 | |
6086 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | |
6087 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6088 | // .. OUTPUT_EN = 0x3 | |
6089 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | |
6090 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
6091 | // .. PULLUP_EN = 0x0 | |
6092 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | |
6093 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
6094 | // .. | |
6095 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | |
6096 | // .. DRIVE_P = 0x1c | |
6097 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | |
6098 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
6099 | // .. DRIVE_N = 0xc | |
6100 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | |
6101 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
6102 | // .. SLEW_P = 0x3 | |
6103 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | |
6104 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | |
6105 | // .. SLEW_N = 0x3 | |
6106 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | |
6107 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | |
6108 | // .. GTL = 0x0 | |
6109 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | |
6110 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
6111 | // .. RTERM = 0x0 | |
6112 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | |
6113 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
6114 | // .. | |
6115 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | |
6116 | // .. DRIVE_P = 0x1c | |
6117 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | |
6118 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
6119 | // .. DRIVE_N = 0xc | |
6120 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | |
6121 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
6122 | // .. SLEW_P = 0x6 | |
6123 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | |
6124 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
6125 | // .. SLEW_N = 0x1f | |
6126 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | |
6127 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
6128 | // .. GTL = 0x0 | |
6129 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | |
6130 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
6131 | // .. RTERM = 0x0 | |
6132 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | |
6133 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
6134 | // .. | |
6135 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | |
6136 | // .. DRIVE_P = 0x1c | |
6137 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | |
6138 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
6139 | // .. DRIVE_N = 0xc | |
6140 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | |
6141 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
6142 | // .. SLEW_P = 0x6 | |
6143 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | |
6144 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
6145 | // .. SLEW_N = 0x1f | |
6146 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | |
6147 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
6148 | // .. GTL = 0x0 | |
6149 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | |
6150 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
6151 | // .. RTERM = 0x0 | |
6152 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | |
6153 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
6154 | // .. | |
6155 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | |
6156 | // .. DRIVE_P = 0x1c | |
6157 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | |
6158 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
6159 | // .. DRIVE_N = 0xc | |
6160 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | |
6161 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
6162 | // .. SLEW_P = 0x6 | |
6163 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | |
6164 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
6165 | // .. SLEW_N = 0x1f | |
6166 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | |
6167 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
6168 | // .. GTL = 0x0 | |
6169 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | |
6170 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
6171 | // .. RTERM = 0x0 | |
6172 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | |
6173 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
6174 | // .. | |
6175 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | |
6176 | // .. VREF_INT_EN = 0x1 | |
6177 | // .. ==> 0XF8000B6C[0:0] = 0x00000001U | |
6178 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
6179 | // .. VREF_SEL = 0x4 | |
6180 | // .. ==> 0XF8000B6C[4:1] = 0x00000004U | |
6181 | // .. ==> MASK : 0x0000001EU VAL : 0x00000008U | |
6182 | // .. VREF_EXT_EN = 0x0 | |
6183 | // .. ==> 0XF8000B6C[6:5] = 0x00000000U | |
6184 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
6185 | // .. VREF_PULLUP_EN = 0x0 | |
6186 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | |
6187 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | |
6188 | // .. REFIO_EN = 0x1 | |
6189 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | |
6190 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | |
6191 | // .. REFIO_TEST = 0x3 | |
6192 | // .. ==> 0XF8000B6C[11:10] = 0x00000003U | |
6193 | // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U | |
6194 | // .. REFIO_PULLUP_EN = 0x0 | |
6195 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | |
6196 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6197 | // .. DRST_B_PULLUP_EN = 0x0 | |
6198 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | |
6199 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6200 | // .. CKE_PULLUP_EN = 0x0 | |
6201 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | |
6202 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
6203 | // .. | |
6204 | EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), | |
6205 | // .. .. START: ASSERT RESET | |
6206 | // .. .. RESET = 1 | |
6207 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | |
6208 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
6209 | // .. .. VRN_OUT = 0x1 | |
6210 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
6211 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
6212 | // .. .. | |
6213 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), | |
6214 | // .. .. FINISH: ASSERT RESET | |
6215 | // .. .. START: DEASSERT RESET | |
6216 | // .. .. RESET = 0 | |
6217 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | |
6218 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6219 | // .. .. VRN_OUT = 0x1 | |
6220 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
6221 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
6222 | // .. .. | |
6223 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | |
6224 | // .. .. FINISH: DEASSERT RESET | |
6225 | // .. .. RESET = 0x1 | |
6226 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | |
6227 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
6228 | // .. .. ENABLE = 0x1 | |
6229 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | |
6230 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6231 | // .. .. VRP_TRI = 0x0 | |
6232 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | |
6233 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6234 | // .. .. VRN_TRI = 0x0 | |
6235 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | |
6236 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
6237 | // .. .. VRP_OUT = 0x0 | |
6238 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | |
6239 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
6240 | // .. .. VRN_OUT = 0x1 | |
6241 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
6242 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
6243 | // .. .. NREF_OPT1 = 0x0 | |
6244 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | |
6245 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | |
6246 | // .. .. NREF_OPT2 = 0x0 | |
6247 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | |
6248 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | |
6249 | // .. .. NREF_OPT4 = 0x1 | |
6250 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | |
6251 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | |
6252 | // .. .. PREF_OPT1 = 0x0 | |
6253 | // .. .. ==> 0XF8000B70[16:14] = 0x00000000U | |
6254 | // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U | |
6255 | // .. .. PREF_OPT2 = 0x0 | |
6256 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | |
6257 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | |
6258 | // .. .. UPDATE_CONTROL = 0x0 | |
6259 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | |
6260 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
6261 | // .. .. INIT_COMPLETE = 0x0 | |
6262 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | |
6263 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
6264 | // .. .. TST_CLK = 0x0 | |
6265 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | |
6266 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
6267 | // .. .. TST_HLN = 0x0 | |
6268 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | |
6269 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
6270 | // .. .. TST_HLP = 0x0 | |
6271 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | |
6272 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
6273 | // .. .. TST_RST = 0x0 | |
6274 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | |
6275 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
6276 | // .. .. INT_DCI_EN = 0x0 | |
6277 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | |
6278 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | |
6279 | // .. .. | |
6280 | EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), | |
6281 | // .. FINISH: DDRIOB SETTINGS | |
6282 | // .. START: MIO PROGRAMMING | |
6283 | // .. TRI_ENABLE = 0 | |
6284 | // .. ==> 0XF8000700[0:0] = 0x00000000U | |
6285 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6286 | // .. L0_SEL = 0 | |
6287 | // .. ==> 0XF8000700[1:1] = 0x00000000U | |
6288 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6289 | // .. L1_SEL = 0 | |
6290 | // .. ==> 0XF8000700[2:2] = 0x00000000U | |
6291 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6292 | // .. L2_SEL = 0 | |
6293 | // .. ==> 0XF8000700[4:3] = 0x00000000U | |
6294 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6295 | // .. L3_SEL = 0 | |
6296 | // .. ==> 0XF8000700[7:5] = 0x00000000U | |
6297 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6298 | // .. Speed = 0 | |
6299 | // .. ==> 0XF8000700[8:8] = 0x00000000U | |
6300 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6301 | // .. IO_Type = 3 | |
6302 | // .. ==> 0XF8000700[11:9] = 0x00000003U | |
6303 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6304 | // .. PULLUP = 0 | |
6305 | // .. ==> 0XF8000700[12:12] = 0x00000000U | |
6306 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6307 | // .. DisableRcvr = 0 | |
6308 | // .. ==> 0XF8000700[13:13] = 0x00000000U | |
6309 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6310 | // .. | |
6311 | EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), | |
6312 | // .. TRI_ENABLE = 0 | |
6313 | // .. ==> 0XF8000704[0:0] = 0x00000000U | |
6314 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6315 | // .. L0_SEL = 1 | |
6316 | // .. ==> 0XF8000704[1:1] = 0x00000001U | |
6317 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6318 | // .. L1_SEL = 0 | |
6319 | // .. ==> 0XF8000704[2:2] = 0x00000000U | |
6320 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6321 | // .. L2_SEL = 0 | |
6322 | // .. ==> 0XF8000704[4:3] = 0x00000000U | |
6323 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6324 | // .. L3_SEL = 0 | |
6325 | // .. ==> 0XF8000704[7:5] = 0x00000000U | |
6326 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6327 | // .. Speed = 0 | |
6328 | // .. ==> 0XF8000704[8:8] = 0x00000000U | |
6329 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6330 | // .. IO_Type = 3 | |
6331 | // .. ==> 0XF8000704[11:9] = 0x00000003U | |
6332 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6333 | // .. PULLUP = 0 | |
6334 | // .. ==> 0XF8000704[12:12] = 0x00000000U | |
6335 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6336 | // .. DisableRcvr = 0 | |
6337 | // .. ==> 0XF8000704[13:13] = 0x00000000U | |
6338 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6339 | // .. | |
6340 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), | |
6341 | // .. TRI_ENABLE = 0 | |
6342 | // .. ==> 0XF8000708[0:0] = 0x00000000U | |
6343 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6344 | // .. L0_SEL = 1 | |
6345 | // .. ==> 0XF8000708[1:1] = 0x00000001U | |
6346 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6347 | // .. L1_SEL = 0 | |
6348 | // .. ==> 0XF8000708[2:2] = 0x00000000U | |
6349 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6350 | // .. L2_SEL = 0 | |
6351 | // .. ==> 0XF8000708[4:3] = 0x00000000U | |
6352 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6353 | // .. L3_SEL = 0 | |
6354 | // .. ==> 0XF8000708[7:5] = 0x00000000U | |
6355 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6356 | // .. Speed = 0 | |
6357 | // .. ==> 0XF8000708[8:8] = 0x00000000U | |
6358 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6359 | // .. IO_Type = 3 | |
6360 | // .. ==> 0XF8000708[11:9] = 0x00000003U | |
6361 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6362 | // .. PULLUP = 0 | |
6363 | // .. ==> 0XF8000708[12:12] = 0x00000000U | |
6364 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6365 | // .. DisableRcvr = 0 | |
6366 | // .. ==> 0XF8000708[13:13] = 0x00000000U | |
6367 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6368 | // .. | |
6369 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), | |
6370 | // .. TRI_ENABLE = 0 | |
6371 | // .. ==> 0XF800070C[0:0] = 0x00000000U | |
6372 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6373 | // .. L0_SEL = 1 | |
6374 | // .. ==> 0XF800070C[1:1] = 0x00000001U | |
6375 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6376 | // .. L1_SEL = 0 | |
6377 | // .. ==> 0XF800070C[2:2] = 0x00000000U | |
6378 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6379 | // .. L2_SEL = 0 | |
6380 | // .. ==> 0XF800070C[4:3] = 0x00000000U | |
6381 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6382 | // .. L3_SEL = 0 | |
6383 | // .. ==> 0XF800070C[7:5] = 0x00000000U | |
6384 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6385 | // .. Speed = 0 | |
6386 | // .. ==> 0XF800070C[8:8] = 0x00000000U | |
6387 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6388 | // .. IO_Type = 3 | |
6389 | // .. ==> 0XF800070C[11:9] = 0x00000003U | |
6390 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6391 | // .. PULLUP = 0 | |
6392 | // .. ==> 0XF800070C[12:12] = 0x00000000U | |
6393 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6394 | // .. DisableRcvr = 0 | |
6395 | // .. ==> 0XF800070C[13:13] = 0x00000000U | |
6396 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6397 | // .. | |
6398 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), | |
6399 | // .. TRI_ENABLE = 0 | |
6400 | // .. ==> 0XF8000710[0:0] = 0x00000000U | |
6401 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6402 | // .. L0_SEL = 1 | |
6403 | // .. ==> 0XF8000710[1:1] = 0x00000001U | |
6404 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6405 | // .. L1_SEL = 0 | |
6406 | // .. ==> 0XF8000710[2:2] = 0x00000000U | |
6407 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6408 | // .. L2_SEL = 0 | |
6409 | // .. ==> 0XF8000710[4:3] = 0x00000000U | |
6410 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6411 | // .. L3_SEL = 0 | |
6412 | // .. ==> 0XF8000710[7:5] = 0x00000000U | |
6413 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6414 | // .. Speed = 0 | |
6415 | // .. ==> 0XF8000710[8:8] = 0x00000000U | |
6416 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6417 | // .. IO_Type = 3 | |
6418 | // .. ==> 0XF8000710[11:9] = 0x00000003U | |
6419 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6420 | // .. PULLUP = 0 | |
6421 | // .. ==> 0XF8000710[12:12] = 0x00000000U | |
6422 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6423 | // .. DisableRcvr = 0 | |
6424 | // .. ==> 0XF8000710[13:13] = 0x00000000U | |
6425 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6426 | // .. | |
6427 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), | |
6428 | // .. TRI_ENABLE = 0 | |
6429 | // .. ==> 0XF8000714[0:0] = 0x00000000U | |
6430 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6431 | // .. L0_SEL = 1 | |
6432 | // .. ==> 0XF8000714[1:1] = 0x00000001U | |
6433 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6434 | // .. L1_SEL = 0 | |
6435 | // .. ==> 0XF8000714[2:2] = 0x00000000U | |
6436 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6437 | // .. L2_SEL = 0 | |
6438 | // .. ==> 0XF8000714[4:3] = 0x00000000U | |
6439 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6440 | // .. L3_SEL = 0 | |
6441 | // .. ==> 0XF8000714[7:5] = 0x00000000U | |
6442 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6443 | // .. Speed = 0 | |
6444 | // .. ==> 0XF8000714[8:8] = 0x00000000U | |
6445 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6446 | // .. IO_Type = 3 | |
6447 | // .. ==> 0XF8000714[11:9] = 0x00000003U | |
6448 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6449 | // .. PULLUP = 0 | |
6450 | // .. ==> 0XF8000714[12:12] = 0x00000000U | |
6451 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6452 | // .. DisableRcvr = 0 | |
6453 | // .. ==> 0XF8000714[13:13] = 0x00000000U | |
6454 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6455 | // .. | |
6456 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), | |
6457 | // .. TRI_ENABLE = 0 | |
6458 | // .. ==> 0XF8000718[0:0] = 0x00000000U | |
6459 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6460 | // .. L0_SEL = 1 | |
6461 | // .. ==> 0XF8000718[1:1] = 0x00000001U | |
6462 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6463 | // .. L1_SEL = 0 | |
6464 | // .. ==> 0XF8000718[2:2] = 0x00000000U | |
6465 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6466 | // .. L2_SEL = 0 | |
6467 | // .. ==> 0XF8000718[4:3] = 0x00000000U | |
6468 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6469 | // .. L3_SEL = 0 | |
6470 | // .. ==> 0XF8000718[7:5] = 0x00000000U | |
6471 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6472 | // .. Speed = 0 | |
6473 | // .. ==> 0XF8000718[8:8] = 0x00000000U | |
6474 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6475 | // .. IO_Type = 3 | |
6476 | // .. ==> 0XF8000718[11:9] = 0x00000003U | |
6477 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6478 | // .. PULLUP = 0 | |
6479 | // .. ==> 0XF8000718[12:12] = 0x00000000U | |
6480 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6481 | // .. DisableRcvr = 0 | |
6482 | // .. ==> 0XF8000718[13:13] = 0x00000000U | |
6483 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6484 | // .. | |
6485 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), | |
6486 | // .. TRI_ENABLE = 0 | |
6487 | // .. ==> 0XF800071C[0:0] = 0x00000000U | |
6488 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6489 | // .. L0_SEL = 0 | |
6490 | // .. ==> 0XF800071C[1:1] = 0x00000000U | |
6491 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6492 | // .. L1_SEL = 0 | |
6493 | // .. ==> 0XF800071C[2:2] = 0x00000000U | |
6494 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6495 | // .. L2_SEL = 0 | |
6496 | // .. ==> 0XF800071C[4:3] = 0x00000000U | |
6497 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6498 | // .. L3_SEL = 0 | |
6499 | // .. ==> 0XF800071C[7:5] = 0x00000000U | |
6500 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6501 | // .. Speed = 0 | |
6502 | // .. ==> 0XF800071C[8:8] = 0x00000000U | |
6503 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6504 | // .. IO_Type = 3 | |
6505 | // .. ==> 0XF800071C[11:9] = 0x00000003U | |
6506 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6507 | // .. PULLUP = 0 | |
6508 | // .. ==> 0XF800071C[12:12] = 0x00000000U | |
6509 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6510 | // .. DisableRcvr = 0 | |
6511 | // .. ==> 0XF800071C[13:13] = 0x00000000U | |
6512 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6513 | // .. | |
6514 | EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), | |
6515 | // .. TRI_ENABLE = 0 | |
6516 | // .. ==> 0XF8000720[0:0] = 0x00000000U | |
6517 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6518 | // .. L0_SEL = 1 | |
6519 | // .. ==> 0XF8000720[1:1] = 0x00000001U | |
6520 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6521 | // .. L1_SEL = 0 | |
6522 | // .. ==> 0XF8000720[2:2] = 0x00000000U | |
6523 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6524 | // .. L2_SEL = 0 | |
6525 | // .. ==> 0XF8000720[4:3] = 0x00000000U | |
6526 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6527 | // .. L3_SEL = 0 | |
6528 | // .. ==> 0XF8000720[7:5] = 0x00000000U | |
6529 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6530 | // .. Speed = 0 | |
6531 | // .. ==> 0XF8000720[8:8] = 0x00000000U | |
6532 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6533 | // .. IO_Type = 3 | |
6534 | // .. ==> 0XF8000720[11:9] = 0x00000003U | |
6535 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6536 | // .. PULLUP = 0 | |
6537 | // .. ==> 0XF8000720[12:12] = 0x00000000U | |
6538 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6539 | // .. DisableRcvr = 0 | |
6540 | // .. ==> 0XF8000720[13:13] = 0x00000000U | |
6541 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6542 | // .. | |
6543 | EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), | |
6544 | // .. TRI_ENABLE = 0 | |
6545 | // .. ==> 0XF8000724[0:0] = 0x00000000U | |
6546 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6547 | // .. L0_SEL = 0 | |
6548 | // .. ==> 0XF8000724[1:1] = 0x00000000U | |
6549 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6550 | // .. L1_SEL = 0 | |
6551 | // .. ==> 0XF8000724[2:2] = 0x00000000U | |
6552 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6553 | // .. L2_SEL = 0 | |
6554 | // .. ==> 0XF8000724[4:3] = 0x00000000U | |
6555 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6556 | // .. L3_SEL = 0 | |
6557 | // .. ==> 0XF8000724[7:5] = 0x00000000U | |
6558 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6559 | // .. Speed = 0 | |
6560 | // .. ==> 0XF8000724[8:8] = 0x00000000U | |
6561 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6562 | // .. IO_Type = 3 | |
6563 | // .. ==> 0XF8000724[11:9] = 0x00000003U | |
6564 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6565 | // .. PULLUP = 0 | |
6566 | // .. ==> 0XF8000724[12:12] = 0x00000000U | |
6567 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6568 | // .. DisableRcvr = 0 | |
6569 | // .. ==> 0XF8000724[13:13] = 0x00000000U | |
6570 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6571 | // .. | |
6572 | EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), | |
6573 | // .. TRI_ENABLE = 0 | |
6574 | // .. ==> 0XF8000728[0:0] = 0x00000000U | |
6575 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6576 | // .. L0_SEL = 0 | |
6577 | // .. ==> 0XF8000728[1:1] = 0x00000000U | |
6578 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6579 | // .. L1_SEL = 0 | |
6580 | // .. ==> 0XF8000728[2:2] = 0x00000000U | |
6581 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6582 | // .. L2_SEL = 0 | |
6583 | // .. ==> 0XF8000728[4:3] = 0x00000000U | |
6584 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6585 | // .. L3_SEL = 0 | |
6586 | // .. ==> 0XF8000728[7:5] = 0x00000000U | |
6587 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6588 | // .. Speed = 0 | |
6589 | // .. ==> 0XF8000728[8:8] = 0x00000000U | |
6590 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6591 | // .. IO_Type = 3 | |
6592 | // .. ==> 0XF8000728[11:9] = 0x00000003U | |
6593 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6594 | // .. PULLUP = 0 | |
6595 | // .. ==> 0XF8000728[12:12] = 0x00000000U | |
6596 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6597 | // .. DisableRcvr = 0 | |
6598 | // .. ==> 0XF8000728[13:13] = 0x00000000U | |
6599 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6600 | // .. | |
6601 | EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), | |
6602 | // .. TRI_ENABLE = 0 | |
6603 | // .. ==> 0XF800072C[0:0] = 0x00000000U | |
6604 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6605 | // .. L0_SEL = 0 | |
6606 | // .. ==> 0XF800072C[1:1] = 0x00000000U | |
6607 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6608 | // .. L1_SEL = 0 | |
6609 | // .. ==> 0XF800072C[2:2] = 0x00000000U | |
6610 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6611 | // .. L2_SEL = 0 | |
6612 | // .. ==> 0XF800072C[4:3] = 0x00000000U | |
6613 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6614 | // .. L3_SEL = 0 | |
6615 | // .. ==> 0XF800072C[7:5] = 0x00000000U | |
6616 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6617 | // .. Speed = 0 | |
6618 | // .. ==> 0XF800072C[8:8] = 0x00000000U | |
6619 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6620 | // .. IO_Type = 3 | |
6621 | // .. ==> 0XF800072C[11:9] = 0x00000003U | |
6622 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6623 | // .. PULLUP = 0 | |
6624 | // .. ==> 0XF800072C[12:12] = 0x00000000U | |
6625 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6626 | // .. DisableRcvr = 0 | |
6627 | // .. ==> 0XF800072C[13:13] = 0x00000000U | |
6628 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6629 | // .. | |
6630 | EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), | |
6631 | // .. TRI_ENABLE = 0 | |
6632 | // .. ==> 0XF8000730[0:0] = 0x00000000U | |
6633 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6634 | // .. L0_SEL = 0 | |
6635 | // .. ==> 0XF8000730[1:1] = 0x00000000U | |
6636 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6637 | // .. L1_SEL = 0 | |
6638 | // .. ==> 0XF8000730[2:2] = 0x00000000U | |
6639 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6640 | // .. L2_SEL = 0 | |
6641 | // .. ==> 0XF8000730[4:3] = 0x00000000U | |
6642 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6643 | // .. L3_SEL = 0 | |
6644 | // .. ==> 0XF8000730[7:5] = 0x00000000U | |
6645 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6646 | // .. Speed = 0 | |
6647 | // .. ==> 0XF8000730[8:8] = 0x00000000U | |
6648 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6649 | // .. IO_Type = 3 | |
6650 | // .. ==> 0XF8000730[11:9] = 0x00000003U | |
6651 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6652 | // .. PULLUP = 0 | |
6653 | // .. ==> 0XF8000730[12:12] = 0x00000000U | |
6654 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6655 | // .. DisableRcvr = 0 | |
6656 | // .. ==> 0XF8000730[13:13] = 0x00000000U | |
6657 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6658 | // .. | |
6659 | EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), | |
6660 | // .. TRI_ENABLE = 0 | |
6661 | // .. ==> 0XF8000734[0:0] = 0x00000000U | |
6662 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6663 | // .. L0_SEL = 0 | |
6664 | // .. ==> 0XF8000734[1:1] = 0x00000000U | |
6665 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6666 | // .. L1_SEL = 0 | |
6667 | // .. ==> 0XF8000734[2:2] = 0x00000000U | |
6668 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6669 | // .. L2_SEL = 0 | |
6670 | // .. ==> 0XF8000734[4:3] = 0x00000000U | |
6671 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6672 | // .. L3_SEL = 0 | |
6673 | // .. ==> 0XF8000734[7:5] = 0x00000000U | |
6674 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6675 | // .. Speed = 0 | |
6676 | // .. ==> 0XF8000734[8:8] = 0x00000000U | |
6677 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6678 | // .. IO_Type = 3 | |
6679 | // .. ==> 0XF8000734[11:9] = 0x00000003U | |
6680 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6681 | // .. PULLUP = 0 | |
6682 | // .. ==> 0XF8000734[12:12] = 0x00000000U | |
6683 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6684 | // .. DisableRcvr = 0 | |
6685 | // .. ==> 0XF8000734[13:13] = 0x00000000U | |
6686 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6687 | // .. | |
6688 | EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), | |
6689 | // .. TRI_ENABLE = 0 | |
6690 | // .. ==> 0XF8000738[0:0] = 0x00000000U | |
6691 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6692 | // .. L0_SEL = 0 | |
6693 | // .. ==> 0XF8000738[1:1] = 0x00000000U | |
6694 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6695 | // .. L1_SEL = 0 | |
6696 | // .. ==> 0XF8000738[2:2] = 0x00000000U | |
6697 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6698 | // .. L2_SEL = 0 | |
6699 | // .. ==> 0XF8000738[4:3] = 0x00000000U | |
6700 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6701 | // .. L3_SEL = 0 | |
6702 | // .. ==> 0XF8000738[7:5] = 0x00000000U | |
6703 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6704 | // .. Speed = 0 | |
6705 | // .. ==> 0XF8000738[8:8] = 0x00000000U | |
6706 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6707 | // .. IO_Type = 3 | |
6708 | // .. ==> 0XF8000738[11:9] = 0x00000003U | |
6709 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6710 | // .. PULLUP = 0 | |
6711 | // .. ==> 0XF8000738[12:12] = 0x00000000U | |
6712 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6713 | // .. DisableRcvr = 0 | |
6714 | // .. ==> 0XF8000738[13:13] = 0x00000000U | |
6715 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6716 | // .. | |
6717 | EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), | |
6718 | // .. TRI_ENABLE = 0 | |
6719 | // .. ==> 0XF800073C[0:0] = 0x00000000U | |
6720 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6721 | // .. L0_SEL = 0 | |
6722 | // .. ==> 0XF800073C[1:1] = 0x00000000U | |
6723 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
6724 | // .. L1_SEL = 0 | |
6725 | // .. ==> 0XF800073C[2:2] = 0x00000000U | |
6726 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6727 | // .. L2_SEL = 0 | |
6728 | // .. ==> 0XF800073C[4:3] = 0x00000000U | |
6729 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6730 | // .. L3_SEL = 0 | |
6731 | // .. ==> 0XF800073C[7:5] = 0x00000000U | |
6732 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6733 | // .. Speed = 0 | |
6734 | // .. ==> 0XF800073C[8:8] = 0x00000000U | |
6735 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6736 | // .. IO_Type = 3 | |
6737 | // .. ==> 0XF800073C[11:9] = 0x00000003U | |
6738 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
6739 | // .. PULLUP = 0 | |
6740 | // .. ==> 0XF800073C[12:12] = 0x00000000U | |
6741 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6742 | // .. DisableRcvr = 0 | |
6743 | // .. ==> 0XF800073C[13:13] = 0x00000000U | |
6744 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6745 | // .. | |
6746 | EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), | |
6747 | // .. TRI_ENABLE = 0 | |
6748 | // .. ==> 0XF8000740[0:0] = 0x00000000U | |
6749 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6750 | // .. L0_SEL = 1 | |
6751 | // .. ==> 0XF8000740[1:1] = 0x00000001U | |
6752 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6753 | // .. L1_SEL = 0 | |
6754 | // .. ==> 0XF8000740[2:2] = 0x00000000U | |
6755 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6756 | // .. L2_SEL = 0 | |
6757 | // .. ==> 0XF8000740[4:3] = 0x00000000U | |
6758 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6759 | // .. L3_SEL = 0 | |
6760 | // .. ==> 0XF8000740[7:5] = 0x00000000U | |
6761 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6762 | // .. Speed = 0 | |
6763 | // .. ==> 0XF8000740[8:8] = 0x00000000U | |
6764 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6765 | // .. IO_Type = 1 | |
6766 | // .. ==> 0XF8000740[11:9] = 0x00000001U | |
6767 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6768 | // .. PULLUP = 0 | |
6769 | // .. ==> 0XF8000740[12:12] = 0x00000000U | |
6770 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6771 | // .. DisableRcvr = 0 | |
6772 | // .. ==> 0XF8000740[13:13] = 0x00000000U | |
6773 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6774 | // .. | |
6775 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), | |
6776 | // .. TRI_ENABLE = 0 | |
6777 | // .. ==> 0XF8000744[0:0] = 0x00000000U | |
6778 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6779 | // .. L0_SEL = 1 | |
6780 | // .. ==> 0XF8000744[1:1] = 0x00000001U | |
6781 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6782 | // .. L1_SEL = 0 | |
6783 | // .. ==> 0XF8000744[2:2] = 0x00000000U | |
6784 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6785 | // .. L2_SEL = 0 | |
6786 | // .. ==> 0XF8000744[4:3] = 0x00000000U | |
6787 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6788 | // .. L3_SEL = 0 | |
6789 | // .. ==> 0XF8000744[7:5] = 0x00000000U | |
6790 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6791 | // .. Speed = 0 | |
6792 | // .. ==> 0XF8000744[8:8] = 0x00000000U | |
6793 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6794 | // .. IO_Type = 1 | |
6795 | // .. ==> 0XF8000744[11:9] = 0x00000001U | |
6796 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6797 | // .. PULLUP = 0 | |
6798 | // .. ==> 0XF8000744[12:12] = 0x00000000U | |
6799 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6800 | // .. DisableRcvr = 0 | |
6801 | // .. ==> 0XF8000744[13:13] = 0x00000000U | |
6802 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6803 | // .. | |
6804 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), | |
6805 | // .. TRI_ENABLE = 0 | |
6806 | // .. ==> 0XF8000748[0:0] = 0x00000000U | |
6807 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6808 | // .. L0_SEL = 1 | |
6809 | // .. ==> 0XF8000748[1:1] = 0x00000001U | |
6810 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6811 | // .. L1_SEL = 0 | |
6812 | // .. ==> 0XF8000748[2:2] = 0x00000000U | |
6813 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6814 | // .. L2_SEL = 0 | |
6815 | // .. ==> 0XF8000748[4:3] = 0x00000000U | |
6816 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6817 | // .. L3_SEL = 0 | |
6818 | // .. ==> 0XF8000748[7:5] = 0x00000000U | |
6819 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6820 | // .. Speed = 0 | |
6821 | // .. ==> 0XF8000748[8:8] = 0x00000000U | |
6822 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6823 | // .. IO_Type = 1 | |
6824 | // .. ==> 0XF8000748[11:9] = 0x00000001U | |
6825 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6826 | // .. PULLUP = 0 | |
6827 | // .. ==> 0XF8000748[12:12] = 0x00000000U | |
6828 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6829 | // .. DisableRcvr = 0 | |
6830 | // .. ==> 0XF8000748[13:13] = 0x00000000U | |
6831 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6832 | // .. | |
6833 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), | |
6834 | // .. TRI_ENABLE = 0 | |
6835 | // .. ==> 0XF800074C[0:0] = 0x00000000U | |
6836 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6837 | // .. L0_SEL = 1 | |
6838 | // .. ==> 0XF800074C[1:1] = 0x00000001U | |
6839 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6840 | // .. L1_SEL = 0 | |
6841 | // .. ==> 0XF800074C[2:2] = 0x00000000U | |
6842 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6843 | // .. L2_SEL = 0 | |
6844 | // .. ==> 0XF800074C[4:3] = 0x00000000U | |
6845 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6846 | // .. L3_SEL = 0 | |
6847 | // .. ==> 0XF800074C[7:5] = 0x00000000U | |
6848 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6849 | // .. Speed = 0 | |
6850 | // .. ==> 0XF800074C[8:8] = 0x00000000U | |
6851 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6852 | // .. IO_Type = 1 | |
6853 | // .. ==> 0XF800074C[11:9] = 0x00000001U | |
6854 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6855 | // .. PULLUP = 0 | |
6856 | // .. ==> 0XF800074C[12:12] = 0x00000000U | |
6857 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6858 | // .. DisableRcvr = 0 | |
6859 | // .. ==> 0XF800074C[13:13] = 0x00000000U | |
6860 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6861 | // .. | |
6862 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), | |
6863 | // .. TRI_ENABLE = 0 | |
6864 | // .. ==> 0XF8000750[0:0] = 0x00000000U | |
6865 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6866 | // .. L0_SEL = 1 | |
6867 | // .. ==> 0XF8000750[1:1] = 0x00000001U | |
6868 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6869 | // .. L1_SEL = 0 | |
6870 | // .. ==> 0XF8000750[2:2] = 0x00000000U | |
6871 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6872 | // .. L2_SEL = 0 | |
6873 | // .. ==> 0XF8000750[4:3] = 0x00000000U | |
6874 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6875 | // .. L3_SEL = 0 | |
6876 | // .. ==> 0XF8000750[7:5] = 0x00000000U | |
6877 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6878 | // .. Speed = 0 | |
6879 | // .. ==> 0XF8000750[8:8] = 0x00000000U | |
6880 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6881 | // .. IO_Type = 1 | |
6882 | // .. ==> 0XF8000750[11:9] = 0x00000001U | |
6883 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6884 | // .. PULLUP = 0 | |
6885 | // .. ==> 0XF8000750[12:12] = 0x00000000U | |
6886 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6887 | // .. DisableRcvr = 0 | |
6888 | // .. ==> 0XF8000750[13:13] = 0x00000000U | |
6889 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6890 | // .. | |
6891 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), | |
6892 | // .. TRI_ENABLE = 0 | |
6893 | // .. ==> 0XF8000754[0:0] = 0x00000000U | |
6894 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
6895 | // .. L0_SEL = 1 | |
6896 | // .. ==> 0XF8000754[1:1] = 0x00000001U | |
6897 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6898 | // .. L1_SEL = 0 | |
6899 | // .. ==> 0XF8000754[2:2] = 0x00000000U | |
6900 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6901 | // .. L2_SEL = 0 | |
6902 | // .. ==> 0XF8000754[4:3] = 0x00000000U | |
6903 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6904 | // .. L3_SEL = 0 | |
6905 | // .. ==> 0XF8000754[7:5] = 0x00000000U | |
6906 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6907 | // .. Speed = 0 | |
6908 | // .. ==> 0XF8000754[8:8] = 0x00000000U | |
6909 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6910 | // .. IO_Type = 1 | |
6911 | // .. ==> 0XF8000754[11:9] = 0x00000001U | |
6912 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6913 | // .. PULLUP = 0 | |
6914 | // .. ==> 0XF8000754[12:12] = 0x00000000U | |
6915 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6916 | // .. DisableRcvr = 0 | |
6917 | // .. ==> 0XF8000754[13:13] = 0x00000000U | |
6918 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6919 | // .. | |
6920 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), | |
6921 | // .. TRI_ENABLE = 1 | |
6922 | // .. ==> 0XF8000758[0:0] = 0x00000001U | |
6923 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
6924 | // .. L0_SEL = 1 | |
6925 | // .. ==> 0XF8000758[1:1] = 0x00000001U | |
6926 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6927 | // .. L1_SEL = 0 | |
6928 | // .. ==> 0XF8000758[2:2] = 0x00000000U | |
6929 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6930 | // .. L2_SEL = 0 | |
6931 | // .. ==> 0XF8000758[4:3] = 0x00000000U | |
6932 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6933 | // .. L3_SEL = 0 | |
6934 | // .. ==> 0XF8000758[7:5] = 0x00000000U | |
6935 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6936 | // .. Speed = 0 | |
6937 | // .. ==> 0XF8000758[8:8] = 0x00000000U | |
6938 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6939 | // .. IO_Type = 1 | |
6940 | // .. ==> 0XF8000758[11:9] = 0x00000001U | |
6941 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6942 | // .. PULLUP = 0 | |
6943 | // .. ==> 0XF8000758[12:12] = 0x00000000U | |
6944 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6945 | // .. DisableRcvr = 0 | |
6946 | // .. ==> 0XF8000758[13:13] = 0x00000000U | |
6947 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6948 | // .. | |
6949 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), | |
6950 | // .. TRI_ENABLE = 1 | |
6951 | // .. ==> 0XF800075C[0:0] = 0x00000001U | |
6952 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
6953 | // .. L0_SEL = 1 | |
6954 | // .. ==> 0XF800075C[1:1] = 0x00000001U | |
6955 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6956 | // .. L1_SEL = 0 | |
6957 | // .. ==> 0XF800075C[2:2] = 0x00000000U | |
6958 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6959 | // .. L2_SEL = 0 | |
6960 | // .. ==> 0XF800075C[4:3] = 0x00000000U | |
6961 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6962 | // .. L3_SEL = 0 | |
6963 | // .. ==> 0XF800075C[7:5] = 0x00000000U | |
6964 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6965 | // .. Speed = 0 | |
6966 | // .. ==> 0XF800075C[8:8] = 0x00000000U | |
6967 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6968 | // .. IO_Type = 1 | |
6969 | // .. ==> 0XF800075C[11:9] = 0x00000001U | |
6970 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
6971 | // .. PULLUP = 0 | |
6972 | // .. ==> 0XF800075C[12:12] = 0x00000000U | |
6973 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
6974 | // .. DisableRcvr = 0 | |
6975 | // .. ==> 0XF800075C[13:13] = 0x00000000U | |
6976 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
6977 | // .. | |
6978 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), | |
6979 | // .. TRI_ENABLE = 1 | |
6980 | // .. ==> 0XF8000760[0:0] = 0x00000001U | |
6981 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
6982 | // .. L0_SEL = 1 | |
6983 | // .. ==> 0XF8000760[1:1] = 0x00000001U | |
6984 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
6985 | // .. L1_SEL = 0 | |
6986 | // .. ==> 0XF8000760[2:2] = 0x00000000U | |
6987 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
6988 | // .. L2_SEL = 0 | |
6989 | // .. ==> 0XF8000760[4:3] = 0x00000000U | |
6990 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
6991 | // .. L3_SEL = 0 | |
6992 | // .. ==> 0XF8000760[7:5] = 0x00000000U | |
6993 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
6994 | // .. Speed = 0 | |
6995 | // .. ==> 0XF8000760[8:8] = 0x00000000U | |
6996 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
6997 | // .. IO_Type = 1 | |
6998 | // .. ==> 0XF8000760[11:9] = 0x00000001U | |
6999 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7000 | // .. PULLUP = 0 | |
7001 | // .. ==> 0XF8000760[12:12] = 0x00000000U | |
7002 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7003 | // .. DisableRcvr = 0 | |
7004 | // .. ==> 0XF8000760[13:13] = 0x00000000U | |
7005 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7006 | // .. | |
7007 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), | |
7008 | // .. TRI_ENABLE = 1 | |
7009 | // .. ==> 0XF8000764[0:0] = 0x00000001U | |
7010 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7011 | // .. L0_SEL = 1 | |
7012 | // .. ==> 0XF8000764[1:1] = 0x00000001U | |
7013 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
7014 | // .. L1_SEL = 0 | |
7015 | // .. ==> 0XF8000764[2:2] = 0x00000000U | |
7016 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7017 | // .. L2_SEL = 0 | |
7018 | // .. ==> 0XF8000764[4:3] = 0x00000000U | |
7019 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7020 | // .. L3_SEL = 0 | |
7021 | // .. ==> 0XF8000764[7:5] = 0x00000000U | |
7022 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7023 | // .. Speed = 0 | |
7024 | // .. ==> 0XF8000764[8:8] = 0x00000000U | |
7025 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7026 | // .. IO_Type = 1 | |
7027 | // .. ==> 0XF8000764[11:9] = 0x00000001U | |
7028 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7029 | // .. PULLUP = 0 | |
7030 | // .. ==> 0XF8000764[12:12] = 0x00000000U | |
7031 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7032 | // .. DisableRcvr = 0 | |
7033 | // .. ==> 0XF8000764[13:13] = 0x00000000U | |
7034 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7035 | // .. | |
7036 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), | |
7037 | // .. TRI_ENABLE = 1 | |
7038 | // .. ==> 0XF8000768[0:0] = 0x00000001U | |
7039 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7040 | // .. L0_SEL = 1 | |
7041 | // .. ==> 0XF8000768[1:1] = 0x00000001U | |
7042 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
7043 | // .. L1_SEL = 0 | |
7044 | // .. ==> 0XF8000768[2:2] = 0x00000000U | |
7045 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7046 | // .. L2_SEL = 0 | |
7047 | // .. ==> 0XF8000768[4:3] = 0x00000000U | |
7048 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7049 | // .. L3_SEL = 0 | |
7050 | // .. ==> 0XF8000768[7:5] = 0x00000000U | |
7051 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7052 | // .. Speed = 0 | |
7053 | // .. ==> 0XF8000768[8:8] = 0x00000000U | |
7054 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7055 | // .. IO_Type = 1 | |
7056 | // .. ==> 0XF8000768[11:9] = 0x00000001U | |
7057 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7058 | // .. PULLUP = 0 | |
7059 | // .. ==> 0XF8000768[12:12] = 0x00000000U | |
7060 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7061 | // .. DisableRcvr = 0 | |
7062 | // .. ==> 0XF8000768[13:13] = 0x00000000U | |
7063 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7064 | // .. | |
7065 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), | |
7066 | // .. TRI_ENABLE = 1 | |
7067 | // .. ==> 0XF800076C[0:0] = 0x00000001U | |
7068 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7069 | // .. L0_SEL = 1 | |
7070 | // .. ==> 0XF800076C[1:1] = 0x00000001U | |
7071 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
7072 | // .. L1_SEL = 0 | |
7073 | // .. ==> 0XF800076C[2:2] = 0x00000000U | |
7074 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7075 | // .. L2_SEL = 0 | |
7076 | // .. ==> 0XF800076C[4:3] = 0x00000000U | |
7077 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7078 | // .. L3_SEL = 0 | |
7079 | // .. ==> 0XF800076C[7:5] = 0x00000000U | |
7080 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7081 | // .. Speed = 0 | |
7082 | // .. ==> 0XF800076C[8:8] = 0x00000000U | |
7083 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7084 | // .. IO_Type = 1 | |
7085 | // .. ==> 0XF800076C[11:9] = 0x00000001U | |
7086 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7087 | // .. PULLUP = 0 | |
7088 | // .. ==> 0XF800076C[12:12] = 0x00000000U | |
7089 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7090 | // .. DisableRcvr = 0 | |
7091 | // .. ==> 0XF800076C[13:13] = 0x00000000U | |
7092 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7093 | // .. | |
7094 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), | |
7095 | // .. TRI_ENABLE = 0 | |
7096 | // .. ==> 0XF8000770[0:0] = 0x00000000U | |
7097 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7098 | // .. L0_SEL = 0 | |
7099 | // .. ==> 0XF8000770[1:1] = 0x00000000U | |
7100 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7101 | // .. L1_SEL = 1 | |
7102 | // .. ==> 0XF8000770[2:2] = 0x00000001U | |
7103 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7104 | // .. L2_SEL = 0 | |
7105 | // .. ==> 0XF8000770[4:3] = 0x00000000U | |
7106 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7107 | // .. L3_SEL = 0 | |
7108 | // .. ==> 0XF8000770[7:5] = 0x00000000U | |
7109 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7110 | // .. Speed = 0 | |
7111 | // .. ==> 0XF8000770[8:8] = 0x00000000U | |
7112 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7113 | // .. IO_Type = 1 | |
7114 | // .. ==> 0XF8000770[11:9] = 0x00000001U | |
7115 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7116 | // .. PULLUP = 0 | |
7117 | // .. ==> 0XF8000770[12:12] = 0x00000000U | |
7118 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7119 | // .. DisableRcvr = 0 | |
7120 | // .. ==> 0XF8000770[13:13] = 0x00000000U | |
7121 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7122 | // .. | |
7123 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), | |
7124 | // .. TRI_ENABLE = 1 | |
7125 | // .. ==> 0XF8000774[0:0] = 0x00000001U | |
7126 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7127 | // .. L0_SEL = 0 | |
7128 | // .. ==> 0XF8000774[1:1] = 0x00000000U | |
7129 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7130 | // .. L1_SEL = 1 | |
7131 | // .. ==> 0XF8000774[2:2] = 0x00000001U | |
7132 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7133 | // .. L2_SEL = 0 | |
7134 | // .. ==> 0XF8000774[4:3] = 0x00000000U | |
7135 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7136 | // .. L3_SEL = 0 | |
7137 | // .. ==> 0XF8000774[7:5] = 0x00000000U | |
7138 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7139 | // .. Speed = 0 | |
7140 | // .. ==> 0XF8000774[8:8] = 0x00000000U | |
7141 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7142 | // .. IO_Type = 1 | |
7143 | // .. ==> 0XF8000774[11:9] = 0x00000001U | |
7144 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7145 | // .. PULLUP = 0 | |
7146 | // .. ==> 0XF8000774[12:12] = 0x00000000U | |
7147 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7148 | // .. DisableRcvr = 0 | |
7149 | // .. ==> 0XF8000774[13:13] = 0x00000000U | |
7150 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7151 | // .. | |
7152 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), | |
7153 | // .. TRI_ENABLE = 0 | |
7154 | // .. ==> 0XF8000778[0:0] = 0x00000000U | |
7155 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7156 | // .. L0_SEL = 0 | |
7157 | // .. ==> 0XF8000778[1:1] = 0x00000000U | |
7158 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7159 | // .. L1_SEL = 1 | |
7160 | // .. ==> 0XF8000778[2:2] = 0x00000001U | |
7161 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7162 | // .. L2_SEL = 0 | |
7163 | // .. ==> 0XF8000778[4:3] = 0x00000000U | |
7164 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7165 | // .. L3_SEL = 0 | |
7166 | // .. ==> 0XF8000778[7:5] = 0x00000000U | |
7167 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7168 | // .. Speed = 0 | |
7169 | // .. ==> 0XF8000778[8:8] = 0x00000000U | |
7170 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7171 | // .. IO_Type = 1 | |
7172 | // .. ==> 0XF8000778[11:9] = 0x00000001U | |
7173 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7174 | // .. PULLUP = 0 | |
7175 | // .. ==> 0XF8000778[12:12] = 0x00000000U | |
7176 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7177 | // .. DisableRcvr = 0 | |
7178 | // .. ==> 0XF8000778[13:13] = 0x00000000U | |
7179 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7180 | // .. | |
7181 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), | |
7182 | // .. TRI_ENABLE = 1 | |
7183 | // .. ==> 0XF800077C[0:0] = 0x00000001U | |
7184 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7185 | // .. L0_SEL = 0 | |
7186 | // .. ==> 0XF800077C[1:1] = 0x00000000U | |
7187 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7188 | // .. L1_SEL = 1 | |
7189 | // .. ==> 0XF800077C[2:2] = 0x00000001U | |
7190 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7191 | // .. L2_SEL = 0 | |
7192 | // .. ==> 0XF800077C[4:3] = 0x00000000U | |
7193 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7194 | // .. L3_SEL = 0 | |
7195 | // .. ==> 0XF800077C[7:5] = 0x00000000U | |
7196 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7197 | // .. Speed = 0 | |
7198 | // .. ==> 0XF800077C[8:8] = 0x00000000U | |
7199 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7200 | // .. IO_Type = 1 | |
7201 | // .. ==> 0XF800077C[11:9] = 0x00000001U | |
7202 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7203 | // .. PULLUP = 0 | |
7204 | // .. ==> 0XF800077C[12:12] = 0x00000000U | |
7205 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7206 | // .. DisableRcvr = 0 | |
7207 | // .. ==> 0XF800077C[13:13] = 0x00000000U | |
7208 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7209 | // .. | |
7210 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), | |
7211 | // .. TRI_ENABLE = 0 | |
7212 | // .. ==> 0XF8000780[0:0] = 0x00000000U | |
7213 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7214 | // .. L0_SEL = 0 | |
7215 | // .. ==> 0XF8000780[1:1] = 0x00000000U | |
7216 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7217 | // .. L1_SEL = 1 | |
7218 | // .. ==> 0XF8000780[2:2] = 0x00000001U | |
7219 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7220 | // .. L2_SEL = 0 | |
7221 | // .. ==> 0XF8000780[4:3] = 0x00000000U | |
7222 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7223 | // .. L3_SEL = 0 | |
7224 | // .. ==> 0XF8000780[7:5] = 0x00000000U | |
7225 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7226 | // .. Speed = 0 | |
7227 | // .. ==> 0XF8000780[8:8] = 0x00000000U | |
7228 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7229 | // .. IO_Type = 1 | |
7230 | // .. ==> 0XF8000780[11:9] = 0x00000001U | |
7231 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7232 | // .. PULLUP = 0 | |
7233 | // .. ==> 0XF8000780[12:12] = 0x00000000U | |
7234 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7235 | // .. DisableRcvr = 0 | |
7236 | // .. ==> 0XF8000780[13:13] = 0x00000000U | |
7237 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7238 | // .. | |
7239 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), | |
7240 | // .. TRI_ENABLE = 0 | |
7241 | // .. ==> 0XF8000784[0:0] = 0x00000000U | |
7242 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7243 | // .. L0_SEL = 0 | |
7244 | // .. ==> 0XF8000784[1:1] = 0x00000000U | |
7245 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7246 | // .. L1_SEL = 1 | |
7247 | // .. ==> 0XF8000784[2:2] = 0x00000001U | |
7248 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7249 | // .. L2_SEL = 0 | |
7250 | // .. ==> 0XF8000784[4:3] = 0x00000000U | |
7251 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7252 | // .. L3_SEL = 0 | |
7253 | // .. ==> 0XF8000784[7:5] = 0x00000000U | |
7254 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7255 | // .. Speed = 0 | |
7256 | // .. ==> 0XF8000784[8:8] = 0x00000000U | |
7257 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7258 | // .. IO_Type = 1 | |
7259 | // .. ==> 0XF8000784[11:9] = 0x00000001U | |
7260 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7261 | // .. PULLUP = 0 | |
7262 | // .. ==> 0XF8000784[12:12] = 0x00000000U | |
7263 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7264 | // .. DisableRcvr = 0 | |
7265 | // .. ==> 0XF8000784[13:13] = 0x00000000U | |
7266 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7267 | // .. | |
7268 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), | |
7269 | // .. TRI_ENABLE = 0 | |
7270 | // .. ==> 0XF8000788[0:0] = 0x00000000U | |
7271 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7272 | // .. L0_SEL = 0 | |
7273 | // .. ==> 0XF8000788[1:1] = 0x00000000U | |
7274 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7275 | // .. L1_SEL = 1 | |
7276 | // .. ==> 0XF8000788[2:2] = 0x00000001U | |
7277 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7278 | // .. L2_SEL = 0 | |
7279 | // .. ==> 0XF8000788[4:3] = 0x00000000U | |
7280 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7281 | // .. L3_SEL = 0 | |
7282 | // .. ==> 0XF8000788[7:5] = 0x00000000U | |
7283 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7284 | // .. Speed = 0 | |
7285 | // .. ==> 0XF8000788[8:8] = 0x00000000U | |
7286 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7287 | // .. IO_Type = 1 | |
7288 | // .. ==> 0XF8000788[11:9] = 0x00000001U | |
7289 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7290 | // .. PULLUP = 0 | |
7291 | // .. ==> 0XF8000788[12:12] = 0x00000000U | |
7292 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7293 | // .. DisableRcvr = 0 | |
7294 | // .. ==> 0XF8000788[13:13] = 0x00000000U | |
7295 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7296 | // .. | |
7297 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), | |
7298 | // .. TRI_ENABLE = 0 | |
7299 | // .. ==> 0XF800078C[0:0] = 0x00000000U | |
7300 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7301 | // .. L0_SEL = 0 | |
7302 | // .. ==> 0XF800078C[1:1] = 0x00000000U | |
7303 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7304 | // .. L1_SEL = 1 | |
7305 | // .. ==> 0XF800078C[2:2] = 0x00000001U | |
7306 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7307 | // .. L2_SEL = 0 | |
7308 | // .. ==> 0XF800078C[4:3] = 0x00000000U | |
7309 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7310 | // .. L3_SEL = 0 | |
7311 | // .. ==> 0XF800078C[7:5] = 0x00000000U | |
7312 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7313 | // .. Speed = 0 | |
7314 | // .. ==> 0XF800078C[8:8] = 0x00000000U | |
7315 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7316 | // .. IO_Type = 1 | |
7317 | // .. ==> 0XF800078C[11:9] = 0x00000001U | |
7318 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7319 | // .. PULLUP = 0 | |
7320 | // .. ==> 0XF800078C[12:12] = 0x00000000U | |
7321 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7322 | // .. DisableRcvr = 0 | |
7323 | // .. ==> 0XF800078C[13:13] = 0x00000000U | |
7324 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7325 | // .. | |
7326 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), | |
7327 | // .. TRI_ENABLE = 1 | |
7328 | // .. ==> 0XF8000790[0:0] = 0x00000001U | |
7329 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7330 | // .. L0_SEL = 0 | |
7331 | // .. ==> 0XF8000790[1:1] = 0x00000000U | |
7332 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7333 | // .. L1_SEL = 1 | |
7334 | // .. ==> 0XF8000790[2:2] = 0x00000001U | |
7335 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7336 | // .. L2_SEL = 0 | |
7337 | // .. ==> 0XF8000790[4:3] = 0x00000000U | |
7338 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7339 | // .. L3_SEL = 0 | |
7340 | // .. ==> 0XF8000790[7:5] = 0x00000000U | |
7341 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7342 | // .. Speed = 0 | |
7343 | // .. ==> 0XF8000790[8:8] = 0x00000000U | |
7344 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7345 | // .. IO_Type = 1 | |
7346 | // .. ==> 0XF8000790[11:9] = 0x00000001U | |
7347 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7348 | // .. PULLUP = 0 | |
7349 | // .. ==> 0XF8000790[12:12] = 0x00000000U | |
7350 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7351 | // .. DisableRcvr = 0 | |
7352 | // .. ==> 0XF8000790[13:13] = 0x00000000U | |
7353 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7354 | // .. | |
7355 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), | |
7356 | // .. TRI_ENABLE = 0 | |
7357 | // .. ==> 0XF8000794[0:0] = 0x00000000U | |
7358 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7359 | // .. L0_SEL = 0 | |
7360 | // .. ==> 0XF8000794[1:1] = 0x00000000U | |
7361 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7362 | // .. L1_SEL = 1 | |
7363 | // .. ==> 0XF8000794[2:2] = 0x00000001U | |
7364 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7365 | // .. L2_SEL = 0 | |
7366 | // .. ==> 0XF8000794[4:3] = 0x00000000U | |
7367 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7368 | // .. L3_SEL = 0 | |
7369 | // .. ==> 0XF8000794[7:5] = 0x00000000U | |
7370 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7371 | // .. Speed = 0 | |
7372 | // .. ==> 0XF8000794[8:8] = 0x00000000U | |
7373 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7374 | // .. IO_Type = 1 | |
7375 | // .. ==> 0XF8000794[11:9] = 0x00000001U | |
7376 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7377 | // .. PULLUP = 0 | |
7378 | // .. ==> 0XF8000794[12:12] = 0x00000000U | |
7379 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7380 | // .. DisableRcvr = 0 | |
7381 | // .. ==> 0XF8000794[13:13] = 0x00000000U | |
7382 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7383 | // .. | |
7384 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), | |
7385 | // .. TRI_ENABLE = 0 | |
7386 | // .. ==> 0XF8000798[0:0] = 0x00000000U | |
7387 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7388 | // .. L0_SEL = 0 | |
7389 | // .. ==> 0XF8000798[1:1] = 0x00000000U | |
7390 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7391 | // .. L1_SEL = 1 | |
7392 | // .. ==> 0XF8000798[2:2] = 0x00000001U | |
7393 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7394 | // .. L2_SEL = 0 | |
7395 | // .. ==> 0XF8000798[4:3] = 0x00000000U | |
7396 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7397 | // .. L3_SEL = 0 | |
7398 | // .. ==> 0XF8000798[7:5] = 0x00000000U | |
7399 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7400 | // .. Speed = 0 | |
7401 | // .. ==> 0XF8000798[8:8] = 0x00000000U | |
7402 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7403 | // .. IO_Type = 1 | |
7404 | // .. ==> 0XF8000798[11:9] = 0x00000001U | |
7405 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7406 | // .. PULLUP = 0 | |
7407 | // .. ==> 0XF8000798[12:12] = 0x00000000U | |
7408 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7409 | // .. DisableRcvr = 0 | |
7410 | // .. ==> 0XF8000798[13:13] = 0x00000000U | |
7411 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7412 | // .. | |
7413 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), | |
7414 | // .. TRI_ENABLE = 0 | |
7415 | // .. ==> 0XF800079C[0:0] = 0x00000000U | |
7416 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7417 | // .. L0_SEL = 0 | |
7418 | // .. ==> 0XF800079C[1:1] = 0x00000000U | |
7419 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7420 | // .. L1_SEL = 1 | |
7421 | // .. ==> 0XF800079C[2:2] = 0x00000001U | |
7422 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7423 | // .. L2_SEL = 0 | |
7424 | // .. ==> 0XF800079C[4:3] = 0x00000000U | |
7425 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7426 | // .. L3_SEL = 0 | |
7427 | // .. ==> 0XF800079C[7:5] = 0x00000000U | |
7428 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7429 | // .. Speed = 0 | |
7430 | // .. ==> 0XF800079C[8:8] = 0x00000000U | |
7431 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7432 | // .. IO_Type = 1 | |
7433 | // .. ==> 0XF800079C[11:9] = 0x00000001U | |
7434 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7435 | // .. PULLUP = 0 | |
7436 | // .. ==> 0XF800079C[12:12] = 0x00000000U | |
7437 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7438 | // .. DisableRcvr = 0 | |
7439 | // .. ==> 0XF800079C[13:13] = 0x00000000U | |
7440 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7441 | // .. | |
7442 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), | |
7443 | // .. TRI_ENABLE = 0 | |
7444 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | |
7445 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7446 | // .. L0_SEL = 0 | |
7447 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | |
7448 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7449 | // .. L1_SEL = 0 | |
7450 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | |
7451 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7452 | // .. L2_SEL = 0 | |
7453 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | |
7454 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7455 | // .. L3_SEL = 4 | |
7456 | // .. ==> 0XF80007A0[7:5] = 0x00000004U | |
7457 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7458 | // .. Speed = 0 | |
7459 | // .. ==> 0XF80007A0[8:8] = 0x00000000U | |
7460 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7461 | // .. IO_Type = 1 | |
7462 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | |
7463 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7464 | // .. PULLUP = 0 | |
7465 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | |
7466 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7467 | // .. DisableRcvr = 0 | |
7468 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | |
7469 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7470 | // .. | |
7471 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), | |
7472 | // .. TRI_ENABLE = 0 | |
7473 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | |
7474 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7475 | // .. L0_SEL = 0 | |
7476 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | |
7477 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7478 | // .. L1_SEL = 0 | |
7479 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | |
7480 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7481 | // .. L2_SEL = 0 | |
7482 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | |
7483 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7484 | // .. L3_SEL = 4 | |
7485 | // .. ==> 0XF80007A4[7:5] = 0x00000004U | |
7486 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7487 | // .. Speed = 0 | |
7488 | // .. ==> 0XF80007A4[8:8] = 0x00000000U | |
7489 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7490 | // .. IO_Type = 1 | |
7491 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | |
7492 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7493 | // .. PULLUP = 0 | |
7494 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | |
7495 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7496 | // .. DisableRcvr = 0 | |
7497 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | |
7498 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7499 | // .. | |
7500 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), | |
7501 | // .. TRI_ENABLE = 0 | |
7502 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | |
7503 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7504 | // .. L0_SEL = 0 | |
7505 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | |
7506 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7507 | // .. L1_SEL = 0 | |
7508 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | |
7509 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7510 | // .. L2_SEL = 0 | |
7511 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | |
7512 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7513 | // .. L3_SEL = 4 | |
7514 | // .. ==> 0XF80007A8[7:5] = 0x00000004U | |
7515 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7516 | // .. Speed = 0 | |
7517 | // .. ==> 0XF80007A8[8:8] = 0x00000000U | |
7518 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7519 | // .. IO_Type = 1 | |
7520 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | |
7521 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7522 | // .. PULLUP = 0 | |
7523 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | |
7524 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7525 | // .. DisableRcvr = 0 | |
7526 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | |
7527 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7528 | // .. | |
7529 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), | |
7530 | // .. TRI_ENABLE = 0 | |
7531 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | |
7532 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7533 | // .. L0_SEL = 0 | |
7534 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | |
7535 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7536 | // .. L1_SEL = 0 | |
7537 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | |
7538 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7539 | // .. L2_SEL = 0 | |
7540 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | |
7541 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7542 | // .. L3_SEL = 4 | |
7543 | // .. ==> 0XF80007AC[7:5] = 0x00000004U | |
7544 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7545 | // .. Speed = 0 | |
7546 | // .. ==> 0XF80007AC[8:8] = 0x00000000U | |
7547 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7548 | // .. IO_Type = 1 | |
7549 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | |
7550 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7551 | // .. PULLUP = 0 | |
7552 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | |
7553 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7554 | // .. DisableRcvr = 0 | |
7555 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | |
7556 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7557 | // .. | |
7558 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), | |
7559 | // .. TRI_ENABLE = 0 | |
7560 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | |
7561 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7562 | // .. L0_SEL = 0 | |
7563 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | |
7564 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7565 | // .. L1_SEL = 0 | |
7566 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | |
7567 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7568 | // .. L2_SEL = 0 | |
7569 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | |
7570 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7571 | // .. L3_SEL = 4 | |
7572 | // .. ==> 0XF80007B0[7:5] = 0x00000004U | |
7573 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7574 | // .. Speed = 0 | |
7575 | // .. ==> 0XF80007B0[8:8] = 0x00000000U | |
7576 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7577 | // .. IO_Type = 1 | |
7578 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | |
7579 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7580 | // .. PULLUP = 0 | |
7581 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | |
7582 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7583 | // .. DisableRcvr = 0 | |
7584 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | |
7585 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7586 | // .. | |
7587 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), | |
7588 | // .. TRI_ENABLE = 0 | |
7589 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | |
7590 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7591 | // .. L0_SEL = 0 | |
7592 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | |
7593 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7594 | // .. L1_SEL = 0 | |
7595 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | |
7596 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7597 | // .. L2_SEL = 0 | |
7598 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | |
7599 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7600 | // .. L3_SEL = 4 | |
7601 | // .. ==> 0XF80007B4[7:5] = 0x00000004U | |
7602 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7603 | // .. Speed = 0 | |
7604 | // .. ==> 0XF80007B4[8:8] = 0x00000000U | |
7605 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7606 | // .. IO_Type = 1 | |
7607 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | |
7608 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7609 | // .. PULLUP = 0 | |
7610 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | |
7611 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7612 | // .. DisableRcvr = 0 | |
7613 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | |
7614 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7615 | // .. | |
7616 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), | |
7617 | // .. TRI_ENABLE = 1 | |
7618 | // .. ==> 0XF80007B8[0:0] = 0x00000001U | |
7619 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7620 | // .. Speed = 0 | |
7621 | // .. ==> 0XF80007B8[8:8] = 0x00000000U | |
7622 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7623 | // .. IO_Type = 1 | |
7624 | // .. ==> 0XF80007B8[11:9] = 0x00000001U | |
7625 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7626 | // .. PULLUP = 0 | |
7627 | // .. ==> 0XF80007B8[12:12] = 0x00000000U | |
7628 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7629 | // .. DisableRcvr = 0 | |
7630 | // .. ==> 0XF80007B8[13:13] = 0x00000000U | |
7631 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7632 | // .. | |
7633 | EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), | |
7634 | // .. TRI_ENABLE = 0 | |
7635 | // .. ==> 0XF80007BC[0:0] = 0x00000000U | |
7636 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7637 | // .. L0_SEL = 0 | |
7638 | // .. ==> 0XF80007BC[1:1] = 0x00000000U | |
7639 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7640 | // .. L1_SEL = 0 | |
7641 | // .. ==> 0XF80007BC[2:2] = 0x00000000U | |
7642 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7643 | // .. L2_SEL = 0 | |
7644 | // .. ==> 0XF80007BC[4:3] = 0x00000000U | |
7645 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7646 | // .. L3_SEL = 0 | |
7647 | // .. ==> 0XF80007BC[7:5] = 0x00000000U | |
7648 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7649 | // .. Speed = 0 | |
7650 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | |
7651 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7652 | // .. IO_Type = 1 | |
7653 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | |
7654 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7655 | // .. PULLUP = 0 | |
7656 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | |
7657 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7658 | // .. DisableRcvr = 0 | |
7659 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | |
7660 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7661 | // .. | |
7662 | EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), | |
7663 | // .. TRI_ENABLE = 0 | |
7664 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | |
7665 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7666 | // .. L0_SEL = 0 | |
7667 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | |
7668 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7669 | // .. L1_SEL = 0 | |
7670 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | |
7671 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7672 | // .. L2_SEL = 0 | |
7673 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | |
7674 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7675 | // .. L3_SEL = 7 | |
7676 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | |
7677 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | |
7678 | // .. Speed = 0 | |
7679 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | |
7680 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7681 | // .. IO_Type = 1 | |
7682 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | |
7683 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7684 | // .. PULLUP = 0 | |
7685 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | |
7686 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7687 | // .. DisableRcvr = 0 | |
7688 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | |
7689 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7690 | // .. | |
7691 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | |
7692 | // .. TRI_ENABLE = 1 | |
7693 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | |
7694 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7695 | // .. L0_SEL = 0 | |
7696 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | |
7697 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7698 | // .. L1_SEL = 0 | |
7699 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | |
7700 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7701 | // .. L2_SEL = 0 | |
7702 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | |
7703 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7704 | // .. L3_SEL = 7 | |
7705 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | |
7706 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | |
7707 | // .. Speed = 0 | |
7708 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | |
7709 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7710 | // .. IO_Type = 1 | |
7711 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | |
7712 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7713 | // .. PULLUP = 0 | |
7714 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | |
7715 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7716 | // .. DisableRcvr = 0 | |
7717 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | |
7718 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7719 | // .. | |
7720 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | |
7721 | // .. TRI_ENABLE = 1 | |
7722 | // .. ==> 0XF80007C8[0:0] = 0x00000001U | |
7723 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7724 | // .. Speed = 0 | |
7725 | // .. ==> 0XF80007C8[8:8] = 0x00000000U | |
7726 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7727 | // .. IO_Type = 1 | |
7728 | // .. ==> 0XF80007C8[11:9] = 0x00000001U | |
7729 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7730 | // .. PULLUP = 0 | |
7731 | // .. ==> 0XF80007C8[12:12] = 0x00000000U | |
7732 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7733 | // .. DisableRcvr = 0 | |
7734 | // .. ==> 0XF80007C8[13:13] = 0x00000000U | |
7735 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7736 | // .. | |
7737 | EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), | |
7738 | // .. TRI_ENABLE = 0 | |
7739 | // .. ==> 0XF80007CC[0:0] = 0x00000000U | |
7740 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7741 | // .. L0_SEL = 0 | |
7742 | // .. ==> 0XF80007CC[1:1] = 0x00000000U | |
7743 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7744 | // .. L1_SEL = 0 | |
7745 | // .. ==> 0XF80007CC[2:2] = 0x00000000U | |
7746 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7747 | // .. L2_SEL = 0 | |
7748 | // .. ==> 0XF80007CC[4:3] = 0x00000000U | |
7749 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7750 | // .. L3_SEL = 0 | |
7751 | // .. ==> 0XF80007CC[7:5] = 0x00000000U | |
7752 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
7753 | // .. Speed = 0 | |
7754 | // .. ==> 0XF80007CC[8:8] = 0x00000000U | |
7755 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7756 | // .. IO_Type = 1 | |
7757 | // .. ==> 0XF80007CC[11:9] = 0x00000001U | |
7758 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7759 | // .. PULLUP = 0 | |
7760 | // .. ==> 0XF80007CC[12:12] = 0x00000000U | |
7761 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7762 | // .. DisableRcvr = 0 | |
7763 | // .. ==> 0XF80007CC[13:13] = 0x00000000U | |
7764 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7765 | // .. | |
7766 | EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), | |
7767 | // .. TRI_ENABLE = 0 | |
7768 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | |
7769 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7770 | // .. L0_SEL = 0 | |
7771 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | |
7772 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7773 | // .. L1_SEL = 0 | |
7774 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | |
7775 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7776 | // .. L2_SEL = 0 | |
7777 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | |
7778 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7779 | // .. L3_SEL = 4 | |
7780 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | |
7781 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7782 | // .. Speed = 0 | |
7783 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | |
7784 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7785 | // .. IO_Type = 1 | |
7786 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | |
7787 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7788 | // .. PULLUP = 0 | |
7789 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | |
7790 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7791 | // .. DisableRcvr = 0 | |
7792 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | |
7793 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7794 | // .. | |
7795 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | |
7796 | // .. TRI_ENABLE = 0 | |
7797 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | |
7798 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7799 | // .. L0_SEL = 0 | |
7800 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | |
7801 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
7802 | // .. L1_SEL = 0 | |
7803 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | |
7804 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
7805 | // .. L2_SEL = 0 | |
7806 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | |
7807 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
7808 | // .. L3_SEL = 4 | |
7809 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | |
7810 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
7811 | // .. Speed = 0 | |
7812 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | |
7813 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7814 | // .. IO_Type = 1 | |
7815 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | |
7816 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
7817 | // .. PULLUP = 0 | |
7818 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | |
7819 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
7820 | // .. DisableRcvr = 0 | |
7821 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | |
7822 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
7823 | // .. | |
7824 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | |
7825 | // .. SDIO0_WP_SEL = 50 | |
7826 | // .. ==> 0XF8000830[5:0] = 0x00000032U | |
7827 | // .. ==> MASK : 0x0000003FU VAL : 0x00000032U | |
7828 | // .. SDIO0_CD_SEL = 46 | |
7829 | // .. ==> 0XF8000830[21:16] = 0x0000002EU | |
7830 | // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U | |
7831 | // .. | |
7832 | EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), | |
7833 | // .. FINISH: MIO PROGRAMMING | |
7834 | // .. START: LOCK IT BACK | |
7835 | // .. LOCK_KEY = 0X767B | |
7836 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
7837 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
7838 | // .. | |
7839 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
7840 | // .. FINISH: LOCK IT BACK | |
7841 | // FINISH: top | |
7842 | // | |
7843 | EMIT_EXIT(), | |
7844 | ||
7845 | // | |
7846 | }; | |
7847 | ||
7848 | unsigned long ps7_peripherals_init_data_2_0[] = { | |
7849 | // START: top | |
7850 | // .. START: SLCR SETTINGS | |
7851 | // .. UNLOCK_KEY = 0XDF0D | |
7852 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
7853 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
7854 | // .. | |
7855 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
7856 | // .. FINISH: SLCR SETTINGS | |
7857 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | |
7858 | // .. IBUF_DISABLE_MODE = 0x1 | |
7859 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | |
7860 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
7861 | // .. TERM_DISABLE_MODE = 0x1 | |
7862 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | |
7863 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
7864 | // .. | |
7865 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | |
7866 | // .. IBUF_DISABLE_MODE = 0x1 | |
7867 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | |
7868 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
7869 | // .. TERM_DISABLE_MODE = 0x1 | |
7870 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | |
7871 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
7872 | // .. | |
7873 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | |
7874 | // .. IBUF_DISABLE_MODE = 0x1 | |
7875 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | |
7876 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
7877 | // .. TERM_DISABLE_MODE = 0x1 | |
7878 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | |
7879 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
7880 | // .. | |
7881 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | |
7882 | // .. IBUF_DISABLE_MODE = 0x1 | |
7883 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | |
7884 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
7885 | // .. TERM_DISABLE_MODE = 0x1 | |
7886 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | |
7887 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
7888 | // .. | |
7889 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | |
7890 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | |
7891 | // .. START: LOCK IT BACK | |
7892 | // .. LOCK_KEY = 0X767B | |
7893 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
7894 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
7895 | // .. | |
7896 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
7897 | // .. FINISH: LOCK IT BACK | |
7898 | // .. START: SRAM/NOR SET OPMODE | |
7899 | // .. FINISH: SRAM/NOR SET OPMODE | |
7900 | // .. START: UART REGISTERS | |
7901 | // .. BDIV = 0x6 | |
7902 | // .. ==> 0XE0001034[7:0] = 0x00000006U | |
7903 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | |
7904 | // .. | |
7905 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | |
7906 | // .. CD = 0x3e | |
7907 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | |
7908 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | |
7909 | // .. | |
7910 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | |
7911 | // .. STPBRK = 0x0 | |
7912 | // .. ==> 0XE0001000[8:8] = 0x00000000U | |
7913 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
7914 | // .. STTBRK = 0x0 | |
7915 | // .. ==> 0XE0001000[7:7] = 0x00000000U | |
7916 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
7917 | // .. RSTTO = 0x0 | |
7918 | // .. ==> 0XE0001000[6:6] = 0x00000000U | |
7919 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
7920 | // .. TXDIS = 0x0 | |
7921 | // .. ==> 0XE0001000[5:5] = 0x00000000U | |
7922 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
7923 | // .. TXEN = 0x1 | |
7924 | // .. ==> 0XE0001000[4:4] = 0x00000001U | |
7925 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
7926 | // .. RXDIS = 0x0 | |
7927 | // .. ==> 0XE0001000[3:3] = 0x00000000U | |
7928 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
7929 | // .. RXEN = 0x1 | |
7930 | // .. ==> 0XE0001000[2:2] = 0x00000001U | |
7931 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
7932 | // .. TXRES = 0x1 | |
7933 | // .. ==> 0XE0001000[1:1] = 0x00000001U | |
7934 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
7935 | // .. RXRES = 0x1 | |
7936 | // .. ==> 0XE0001000[0:0] = 0x00000001U | |
7937 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
7938 | // .. | |
7939 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | |
7940 | // .. IRMODE = 0x0 | |
7941 | // .. ==> 0XE0001004[11:11] = 0x00000000U | |
7942 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
7943 | // .. UCLKEN = 0x0 | |
7944 | // .. ==> 0XE0001004[10:10] = 0x00000000U | |
7945 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
7946 | // .. CHMODE = 0x0 | |
7947 | // .. ==> 0XE0001004[9:8] = 0x00000000U | |
7948 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | |
7949 | // .. NBSTOP = 0x0 | |
7950 | // .. ==> 0XE0001004[7:6] = 0x00000000U | |
7951 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | |
7952 | // .. PAR = 0x4 | |
7953 | // .. ==> 0XE0001004[5:3] = 0x00000004U | |
7954 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | |
7955 | // .. CHRL = 0x0 | |
7956 | // .. ==> 0XE0001004[2:1] = 0x00000000U | |
7957 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
7958 | // .. CLKS = 0x0 | |
7959 | // .. ==> 0XE0001004[0:0] = 0x00000000U | |
7960 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
7961 | // .. | |
7962 | EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), | |
7963 | // .. FINISH: UART REGISTERS | |
7964 | // .. START: QSPI REGISTERS | |
7965 | // .. Holdb_dr = 1 | |
7966 | // .. ==> 0XE000D000[19:19] = 0x00000001U | |
7967 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
7968 | // .. | |
7969 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | |
7970 | // .. FINISH: QSPI REGISTERS | |
7971 | // .. START: PL POWER ON RESET REGISTERS | |
7972 | // .. PCFG_POR_CNT_4K = 0 | |
7973 | // .. ==> 0XF8007000[29:29] = 0x00000000U | |
7974 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | |
7975 | // .. | |
7976 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | |
7977 | // .. FINISH: PL POWER ON RESET REGISTERS | |
7978 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | |
7979 | // .. .. START: NAND SET CYCLE | |
7980 | // .. .. FINISH: NAND SET CYCLE | |
7981 | // .. .. START: OPMODE | |
7982 | // .. .. FINISH: OPMODE | |
7983 | // .. .. START: DIRECT COMMAND | |
7984 | // .. .. FINISH: DIRECT COMMAND | |
7985 | // .. .. START: SRAM/NOR CS0 SET CYCLE | |
7986 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | |
7987 | // .. .. START: DIRECT COMMAND | |
7988 | // .. .. FINISH: DIRECT COMMAND | |
7989 | // .. .. START: NOR CS0 BASE ADDRESS | |
7990 | // .. .. FINISH: NOR CS0 BASE ADDRESS | |
7991 | // .. .. START: SRAM/NOR CS1 SET CYCLE | |
7992 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | |
7993 | // .. .. START: DIRECT COMMAND | |
7994 | // .. .. FINISH: DIRECT COMMAND | |
7995 | // .. .. START: NOR CS1 BASE ADDRESS | |
7996 | // .. .. FINISH: NOR CS1 BASE ADDRESS | |
7997 | // .. .. START: USB RESET | |
7998 | // .. .. .. START: USB0 RESET | |
7999 | // .. .. .. .. START: DIR MODE BANK 0 | |
8000 | // .. .. .. .. DIRECTION_0 = 0x80 | |
8001 | // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U | |
8002 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | |
8003 | // .. .. .. .. | |
8004 | EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), | |
8005 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
8006 | // .. .. .. .. START: DIR MODE BANK 1 | |
8007 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
8008 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8009 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
8010 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
8011 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
8012 | // .. .. .. .. DATA_0_LSW = 0x80 | |
8013 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | |
8014 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | |
8015 | // .. .. .. .. | |
8016 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | |
8017 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8018 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8019 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8020 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8021 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8022 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8023 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8024 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
8025 | // .. .. .. .. OP_ENABLE_0 = 0x80 | |
8026 | // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U | |
8027 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | |
8028 | // .. .. .. .. | |
8029 | EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), | |
8030 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
8031 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
8032 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
8033 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
8034 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
8035 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
8036 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
8037 | // .. .. .. .. DATA_0_LSW = 0x0 | |
8038 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U | |
8039 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U | |
8040 | // .. .. .. .. | |
8041 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), | |
8042 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
8043 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
8044 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
8045 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
8046 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
8047 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
8048 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
8049 | // .. .. .. .. START: ADD 1 MS DELAY | |
8050 | // .. .. .. .. | |
8051 | EMIT_MASKDELAY(0XF8F00200, 1), | |
8052 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
8053 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8054 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
8055 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
8056 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
8057 | // .. .. .. .. DATA_0_LSW = 0x80 | |
8058 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | |
8059 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | |
8060 | // .. .. .. .. | |
8061 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | |
8062 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8063 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8064 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8065 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8066 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8067 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8068 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8069 | // .. .. .. FINISH: USB0 RESET | |
8070 | // .. .. .. START: USB1 RESET | |
8071 | // .. .. .. .. START: DIR MODE BANK 0 | |
8072 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
8073 | // .. .. .. .. START: DIR MODE BANK 1 | |
8074 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
8075 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8076 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8077 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8078 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8079 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8080 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8081 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8082 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8083 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
8084 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
8085 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
8086 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
8087 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
8088 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
8089 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
8090 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
8091 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
8092 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
8093 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
8094 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
8095 | // .. .. .. .. START: ADD 1 MS DELAY | |
8096 | // .. .. .. .. | |
8097 | EMIT_MASKDELAY(0XF8F00200, 1), | |
8098 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
8099 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8100 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8101 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8102 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8103 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8104 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8105 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8106 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8107 | // .. .. .. FINISH: USB1 RESET | |
8108 | // .. .. FINISH: USB RESET | |
8109 | // .. .. START: ENET RESET | |
8110 | // .. .. .. START: ENET0 RESET | |
8111 | // .. .. .. .. START: DIR MODE BANK 0 | |
8112 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
8113 | // .. .. .. .. START: DIR MODE BANK 1 | |
8114 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
8115 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8116 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8117 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8118 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8119 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8120 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8121 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8122 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8123 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
8124 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
8125 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
8126 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
8127 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
8128 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
8129 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
8130 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
8131 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
8132 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
8133 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
8134 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
8135 | // .. .. .. .. START: ADD 1 MS DELAY | |
8136 | // .. .. .. .. | |
8137 | EMIT_MASKDELAY(0XF8F00200, 1), | |
8138 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
8139 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8140 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8141 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8142 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8143 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8144 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8145 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8146 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8147 | // .. .. .. FINISH: ENET0 RESET | |
8148 | // .. .. .. START: ENET1 RESET | |
8149 | // .. .. .. .. START: DIR MODE BANK 0 | |
8150 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
8151 | // .. .. .. .. START: DIR MODE BANK 1 | |
8152 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
8153 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8154 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8155 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8156 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8157 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8158 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8159 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8160 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8161 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
8162 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
8163 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
8164 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
8165 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
8166 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
8167 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
8168 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
8169 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
8170 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
8171 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
8172 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
8173 | // .. .. .. .. START: ADD 1 MS DELAY | |
8174 | // .. .. .. .. | |
8175 | EMIT_MASKDELAY(0XF8F00200, 1), | |
8176 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
8177 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8178 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8179 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8180 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8181 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8182 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8183 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8184 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8185 | // .. .. .. FINISH: ENET1 RESET | |
8186 | // .. .. FINISH: ENET RESET | |
8187 | // .. .. START: I2C RESET | |
8188 | // .. .. .. START: I2C0 RESET | |
8189 | // .. .. .. .. START: DIR MODE GPIO BANK0 | |
8190 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | |
8191 | // .. .. .. .. START: DIR MODE GPIO BANK1 | |
8192 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | |
8193 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8194 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8195 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8196 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8197 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8198 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8199 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8200 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8201 | // .. .. .. .. START: OUTPUT ENABLE | |
8202 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
8203 | // .. .. .. .. START: OUTPUT ENABLE | |
8204 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
8205 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
8206 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
8207 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
8208 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
8209 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
8210 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
8211 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
8212 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
8213 | // .. .. .. .. START: ADD 1 MS DELAY | |
8214 | // .. .. .. .. | |
8215 | EMIT_MASKDELAY(0XF8F00200, 1), | |
8216 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
8217 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8218 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8219 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8220 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8221 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8222 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8223 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8224 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8225 | // .. .. .. FINISH: I2C0 RESET | |
8226 | // .. .. .. START: I2C1 RESET | |
8227 | // .. .. .. .. START: DIR MODE GPIO BANK0 | |
8228 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | |
8229 | // .. .. .. .. START: DIR MODE GPIO BANK1 | |
8230 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | |
8231 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8232 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8233 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8234 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8235 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8236 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8237 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8238 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8239 | // .. .. .. .. START: OUTPUT ENABLE | |
8240 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
8241 | // .. .. .. .. START: OUTPUT ENABLE | |
8242 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
8243 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
8244 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
8245 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
8246 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
8247 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
8248 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
8249 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
8250 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
8251 | // .. .. .. .. START: ADD 1 MS DELAY | |
8252 | // .. .. .. .. | |
8253 | EMIT_MASKDELAY(0XF8F00200, 1), | |
8254 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
8255 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8256 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8257 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8258 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
8259 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8260 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
8261 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8262 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
8263 | // .. .. .. FINISH: I2C1 RESET | |
8264 | // .. .. FINISH: I2C RESET | |
8265 | // .. .. START: NOR CHIP SELECT | |
8266 | // .. .. .. START: DIR MODE BANK 0 | |
8267 | // .. .. .. FINISH: DIR MODE BANK 0 | |
8268 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8269 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
8270 | // .. .. .. START: OUTPUT ENABLE BANK 0 | |
8271 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
8272 | // .. .. FINISH: NOR CHIP SELECT | |
8273 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | |
8274 | // FINISH: top | |
8275 | // | |
8276 | EMIT_EXIT(), | |
8277 | ||
8278 | // | |
8279 | }; | |
8280 | ||
8281 | unsigned long ps7_post_config_2_0[] = { | |
8282 | // START: top | |
8283 | // .. START: SLCR SETTINGS | |
8284 | // .. UNLOCK_KEY = 0XDF0D | |
8285 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
8286 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
8287 | // .. | |
8288 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
8289 | // .. FINISH: SLCR SETTINGS | |
8290 | // .. START: ENABLING LEVEL SHIFTER | |
8291 | // .. USER_INP_ICT_EN_0 = 3 | |
8292 | // .. ==> 0XF8000900[1:0] = 0x00000003U | |
8293 | // .. ==> MASK : 0x00000003U VAL : 0x00000003U | |
8294 | // .. USER_INP_ICT_EN_1 = 3 | |
8295 | // .. ==> 0XF8000900[3:2] = 0x00000003U | |
8296 | // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU | |
8297 | // .. | |
8298 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | |
8299 | // .. FINISH: ENABLING LEVEL SHIFTER | |
8300 | // .. START: FPGA RESETS TO 0 | |
8301 | // .. reserved_3 = 0 | |
8302 | // .. ==> 0XF8000240[31:25] = 0x00000000U | |
8303 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | |
8304 | // .. FPGA_ACP_RST = 0 | |
8305 | // .. ==> 0XF8000240[24:24] = 0x00000000U | |
8306 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
8307 | // .. FPGA_AXDS3_RST = 0 | |
8308 | // .. ==> 0XF8000240[23:23] = 0x00000000U | |
8309 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
8310 | // .. FPGA_AXDS2_RST = 0 | |
8311 | // .. ==> 0XF8000240[22:22] = 0x00000000U | |
8312 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
8313 | // .. FPGA_AXDS1_RST = 0 | |
8314 | // .. ==> 0XF8000240[21:21] = 0x00000000U | |
8315 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
8316 | // .. FPGA_AXDS0_RST = 0 | |
8317 | // .. ==> 0XF8000240[20:20] = 0x00000000U | |
8318 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
8319 | // .. reserved_2 = 0 | |
8320 | // .. ==> 0XF8000240[19:18] = 0x00000000U | |
8321 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | |
8322 | // .. FSSW1_FPGA_RST = 0 | |
8323 | // .. ==> 0XF8000240[17:17] = 0x00000000U | |
8324 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
8325 | // .. FSSW0_FPGA_RST = 0 | |
8326 | // .. ==> 0XF8000240[16:16] = 0x00000000U | |
8327 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
8328 | // .. reserved_1 = 0 | |
8329 | // .. ==> 0XF8000240[15:14] = 0x00000000U | |
8330 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | |
8331 | // .. FPGA_FMSW1_RST = 0 | |
8332 | // .. ==> 0XF8000240[13:13] = 0x00000000U | |
8333 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
8334 | // .. FPGA_FMSW0_RST = 0 | |
8335 | // .. ==> 0XF8000240[12:12] = 0x00000000U | |
8336 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
8337 | // .. FPGA_DMA3_RST = 0 | |
8338 | // .. ==> 0XF8000240[11:11] = 0x00000000U | |
8339 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
8340 | // .. FPGA_DMA2_RST = 0 | |
8341 | // .. ==> 0XF8000240[10:10] = 0x00000000U | |
8342 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
8343 | // .. FPGA_DMA1_RST = 0 | |
8344 | // .. ==> 0XF8000240[9:9] = 0x00000000U | |
8345 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
8346 | // .. FPGA_DMA0_RST = 0 | |
8347 | // .. ==> 0XF8000240[8:8] = 0x00000000U | |
8348 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
8349 | // .. reserved = 0 | |
8350 | // .. ==> 0XF8000240[7:4] = 0x00000000U | |
8351 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
8352 | // .. FPGA3_OUT_RST = 0 | |
8353 | // .. ==> 0XF8000240[3:3] = 0x00000000U | |
8354 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
8355 | // .. FPGA2_OUT_RST = 0 | |
8356 | // .. ==> 0XF8000240[2:2] = 0x00000000U | |
8357 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
8358 | // .. FPGA1_OUT_RST = 0 | |
8359 | // .. ==> 0XF8000240[1:1] = 0x00000000U | |
8360 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
8361 | // .. FPGA0_OUT_RST = 0 | |
8362 | // .. ==> 0XF8000240[0:0] = 0x00000000U | |
8363 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
8364 | // .. | |
8365 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | |
8366 | // .. FINISH: FPGA RESETS TO 0 | |
8367 | // .. START: AFI REGISTERS | |
8368 | // .. .. START: AFI0 REGISTERS | |
8369 | // .. .. FINISH: AFI0 REGISTERS | |
8370 | // .. .. START: AFI1 REGISTERS | |
8371 | // .. .. FINISH: AFI1 REGISTERS | |
8372 | // .. .. START: AFI2 REGISTERS | |
8373 | // .. .. FINISH: AFI2 REGISTERS | |
8374 | // .. .. START: AFI3 REGISTERS | |
8375 | // .. .. FINISH: AFI3 REGISTERS | |
8376 | // .. FINISH: AFI REGISTERS | |
8377 | // .. START: LOCK IT BACK | |
8378 | // .. LOCK_KEY = 0X767B | |
8379 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
8380 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
8381 | // .. | |
8382 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
8383 | // .. FINISH: LOCK IT BACK | |
8384 | // FINISH: top | |
8385 | // | |
8386 | EMIT_EXIT(), | |
8387 | ||
8388 | // | |
8389 | }; | |
8390 | ||
95b237ec MY |
8391 | |
8392 | unsigned long ps7_pll_init_data_1_0[] = { | |
8393 | // START: top | |
8394 | // .. START: SLCR SETTINGS | |
8395 | // .. UNLOCK_KEY = 0XDF0D | |
8396 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
8397 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
8398 | // .. | |
8399 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
8400 | // .. FINISH: SLCR SETTINGS | |
8401 | // .. START: PLL SLCR REGISTERS | |
8402 | // .. .. START: ARM PLL INIT | |
8403 | // .. .. PLL_RES = 0x2 | |
8404 | // .. .. ==> 0XF8000110[7:4] = 0x00000002U | |
8405 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
8406 | // .. .. PLL_CP = 0x2 | |
8407 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | |
8408 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
8409 | // .. .. LOCK_CNT = 0xfa | |
8410 | // .. .. ==> 0XF8000110[21:12] = 0x000000FAU | |
8411 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | |
8412 | // .. .. | |
8413 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), | |
8414 | // .. .. .. START: UPDATE FB_DIV | |
8415 | // .. .. .. PLL_FDIV = 0x28 | |
8416 | // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U | |
8417 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U | |
8418 | // .. .. .. | |
8419 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), | |
8420 | // .. .. .. FINISH: UPDATE FB_DIV | |
8421 | // .. .. .. START: BY PASS PLL | |
8422 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
8423 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | |
8424 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
8425 | // .. .. .. | |
8426 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | |
8427 | // .. .. .. FINISH: BY PASS PLL | |
8428 | // .. .. .. START: ASSERT RESET | |
8429 | // .. .. .. PLL_RESET = 1 | |
8430 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | |
8431 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8432 | // .. .. .. | |
8433 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | |
8434 | // .. .. .. FINISH: ASSERT RESET | |
8435 | // .. .. .. START: DEASSERT RESET | |
8436 | // .. .. .. PLL_RESET = 0 | |
8437 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | |
8438 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
8439 | // .. .. .. | |
8440 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | |
8441 | // .. .. .. FINISH: DEASSERT RESET | |
8442 | // .. .. .. START: CHECK PLL STATUS | |
8443 | // .. .. .. ARM_PLL_LOCK = 1 | |
8444 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | |
8445 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8446 | // .. .. .. | |
8447 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | |
8448 | // .. .. .. FINISH: CHECK PLL STATUS | |
8449 | // .. .. .. START: REMOVE PLL BY PASS | |
8450 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
8451 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | |
8452 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
8453 | // .. .. .. | |
8454 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | |
8455 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
8456 | // .. .. .. SRCSEL = 0x0 | |
8457 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | |
8458 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8459 | // .. .. .. DIVISOR = 0x2 | |
8460 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U | |
8461 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U | |
8462 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | |
8463 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | |
8464 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | |
8465 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | |
8466 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | |
8467 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | |
8468 | // .. .. .. CPU_2XCLKACT = 0x1 | |
8469 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | |
8470 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | |
8471 | // .. .. .. CPU_1XCLKACT = 0x1 | |
8472 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | |
8473 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | |
8474 | // .. .. .. CPU_PERI_CLKACT = 0x1 | |
8475 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | |
8476 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
8477 | // .. .. .. | |
8478 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), | |
8479 | // .. .. FINISH: ARM PLL INIT | |
8480 | // .. .. START: DDR PLL INIT | |
8481 | // .. .. PLL_RES = 0x2 | |
8482 | // .. .. ==> 0XF8000114[7:4] = 0x00000002U | |
8483 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | |
8484 | // .. .. PLL_CP = 0x2 | |
8485 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | |
8486 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
8487 | // .. .. LOCK_CNT = 0x12c | |
8488 | // .. .. ==> 0XF8000114[21:12] = 0x0000012CU | |
8489 | // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U | |
8490 | // .. .. | |
8491 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), | |
8492 | // .. .. .. START: UPDATE FB_DIV | |
8493 | // .. .. .. PLL_FDIV = 0x20 | |
8494 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U | |
8495 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U | |
8496 | // .. .. .. | |
8497 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), | |
8498 | // .. .. .. FINISH: UPDATE FB_DIV | |
8499 | // .. .. .. START: BY PASS PLL | |
8500 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
8501 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | |
8502 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
8503 | // .. .. .. | |
8504 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | |
8505 | // .. .. .. FINISH: BY PASS PLL | |
8506 | // .. .. .. START: ASSERT RESET | |
8507 | // .. .. .. PLL_RESET = 1 | |
8508 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | |
8509 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8510 | // .. .. .. | |
8511 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | |
8512 | // .. .. .. FINISH: ASSERT RESET | |
8513 | // .. .. .. START: DEASSERT RESET | |
8514 | // .. .. .. PLL_RESET = 0 | |
8515 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | |
8516 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
8517 | // .. .. .. | |
8518 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | |
8519 | // .. .. .. FINISH: DEASSERT RESET | |
8520 | // .. .. .. START: CHECK PLL STATUS | |
8521 | // .. .. .. DDR_PLL_LOCK = 1 | |
8522 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | |
8523 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
8524 | // .. .. .. | |
8525 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | |
8526 | // .. .. .. FINISH: CHECK PLL STATUS | |
8527 | // .. .. .. START: REMOVE PLL BY PASS | |
8528 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
8529 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | |
8530 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
8531 | // .. .. .. | |
8532 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | |
8533 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
8534 | // .. .. .. DDR_3XCLKACT = 0x1 | |
8535 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | |
8536 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8537 | // .. .. .. DDR_2XCLKACT = 0x1 | |
8538 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | |
8539 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
8540 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | |
8541 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | |
8542 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | |
8543 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | |
8544 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | |
8545 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | |
8546 | // .. .. .. | |
8547 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | |
8548 | // .. .. FINISH: DDR PLL INIT | |
8549 | // .. .. START: IO PLL INIT | |
8550 | // .. .. PLL_RES = 0xc | |
8551 | // .. .. ==> 0XF8000118[7:4] = 0x0000000CU | |
8552 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | |
8553 | // .. .. PLL_CP = 0x2 | |
8554 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | |
8555 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
8556 | // .. .. LOCK_CNT = 0x145 | |
8557 | // .. .. ==> 0XF8000118[21:12] = 0x00000145U | |
8558 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U | |
8559 | // .. .. | |
8560 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), | |
8561 | // .. .. .. START: UPDATE FB_DIV | |
8562 | // .. .. .. PLL_FDIV = 0x1e | |
8563 | // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU | |
8564 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U | |
8565 | // .. .. .. | |
8566 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), | |
8567 | // .. .. .. FINISH: UPDATE FB_DIV | |
8568 | // .. .. .. START: BY PASS PLL | |
8569 | // .. .. .. PLL_BYPASS_FORCE = 1 | |
8570 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | |
8571 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
8572 | // .. .. .. | |
8573 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | |
8574 | // .. .. .. FINISH: BY PASS PLL | |
8575 | // .. .. .. START: ASSERT RESET | |
8576 | // .. .. .. PLL_RESET = 1 | |
8577 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | |
8578 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8579 | // .. .. .. | |
8580 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | |
8581 | // .. .. .. FINISH: ASSERT RESET | |
8582 | // .. .. .. START: DEASSERT RESET | |
8583 | // .. .. .. PLL_RESET = 0 | |
8584 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | |
8585 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
8586 | // .. .. .. | |
8587 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | |
8588 | // .. .. .. FINISH: DEASSERT RESET | |
8589 | // .. .. .. START: CHECK PLL STATUS | |
8590 | // .. .. .. IO_PLL_LOCK = 1 | |
8591 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | |
8592 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
8593 | // .. .. .. | |
8594 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | |
8595 | // .. .. .. FINISH: CHECK PLL STATUS | |
8596 | // .. .. .. START: REMOVE PLL BY PASS | |
8597 | // .. .. .. PLL_BYPASS_FORCE = 0 | |
8598 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | |
8599 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
8600 | // .. .. .. | |
8601 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | |
8602 | // .. .. .. FINISH: REMOVE PLL BY PASS | |
8603 | // .. .. FINISH: IO PLL INIT | |
8604 | // .. FINISH: PLL SLCR REGISTERS | |
8605 | // .. START: LOCK IT BACK | |
8606 | // .. LOCK_KEY = 0X767B | |
8607 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
8608 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
8609 | // .. | |
8610 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
8611 | // .. FINISH: LOCK IT BACK | |
8612 | // FINISH: top | |
8613 | // | |
8614 | EMIT_EXIT(), | |
8615 | ||
8616 | // | |
8617 | }; | |
8618 | ||
8619 | unsigned long ps7_clock_init_data_1_0[] = { | |
8620 | // START: top | |
8621 | // .. START: SLCR SETTINGS | |
8622 | // .. UNLOCK_KEY = 0XDF0D | |
8623 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
8624 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
8625 | // .. | |
8626 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
8627 | // .. FINISH: SLCR SETTINGS | |
8628 | // .. START: CLOCK CONTROL SLCR REGISTERS | |
8629 | // .. CLKACT = 0x1 | |
8630 | // .. ==> 0XF8000128[0:0] = 0x00000001U | |
8631 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8632 | // .. DIVISOR0 = 0x23 | |
8633 | // .. ==> 0XF8000128[13:8] = 0x00000023U | |
8634 | // .. ==> MASK : 0x00003F00U VAL : 0x00002300U | |
8635 | // .. DIVISOR1 = 0x3 | |
8636 | // .. ==> 0XF8000128[25:20] = 0x00000003U | |
8637 | // .. ==> MASK : 0x03F00000U VAL : 0x00300000U | |
8638 | // .. | |
8639 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), | |
8640 | // .. CLKACT = 0x1 | |
8641 | // .. ==> 0XF8000138[0:0] = 0x00000001U | |
8642 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8643 | // .. SRCSEL = 0x0 | |
8644 | // .. ==> 0XF8000138[4:4] = 0x00000000U | |
8645 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
8646 | // .. | |
8647 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | |
8648 | // .. CLKACT = 0x1 | |
8649 | // .. ==> 0XF8000140[0:0] = 0x00000001U | |
8650 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8651 | // .. SRCSEL = 0x0 | |
8652 | // .. ==> 0XF8000140[6:4] = 0x00000000U | |
8653 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
8654 | // .. DIVISOR = 0x8 | |
8655 | // .. ==> 0XF8000140[13:8] = 0x00000008U | |
8656 | // .. ==> MASK : 0x00003F00U VAL : 0x00000800U | |
8657 | // .. DIVISOR1 = 0x1 | |
8658 | // .. ==> 0XF8000140[25:20] = 0x00000001U | |
8659 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
8660 | // .. | |
8661 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), | |
8662 | // .. CLKACT = 0x1 | |
8663 | // .. ==> 0XF800014C[0:0] = 0x00000001U | |
8664 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8665 | // .. SRCSEL = 0x0 | |
8666 | // .. ==> 0XF800014C[5:4] = 0x00000000U | |
8667 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8668 | // .. DIVISOR = 0x5 | |
8669 | // .. ==> 0XF800014C[13:8] = 0x00000005U | |
8670 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | |
8671 | // .. | |
8672 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), | |
8673 | // .. CLKACT0 = 0x1 | |
8674 | // .. ==> 0XF8000150[0:0] = 0x00000001U | |
8675 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8676 | // .. CLKACT1 = 0x0 | |
8677 | // .. ==> 0XF8000150[1:1] = 0x00000000U | |
8678 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
8679 | // .. SRCSEL = 0x0 | |
8680 | // .. ==> 0XF8000150[5:4] = 0x00000000U | |
8681 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8682 | // .. DIVISOR = 0x14 | |
8683 | // .. ==> 0XF8000150[13:8] = 0x00000014U | |
8684 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
8685 | // .. | |
8686 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), | |
8687 | // .. CLKACT0 = 0x0 | |
8688 | // .. ==> 0XF8000154[0:0] = 0x00000000U | |
8689 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
8690 | // .. CLKACT1 = 0x1 | |
8691 | // .. ==> 0XF8000154[1:1] = 0x00000001U | |
8692 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
8693 | // .. SRCSEL = 0x0 | |
8694 | // .. ==> 0XF8000154[5:4] = 0x00000000U | |
8695 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8696 | // .. DIVISOR = 0x14 | |
8697 | // .. ==> 0XF8000154[13:8] = 0x00000014U | |
8698 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
8699 | // .. | |
8700 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), | |
8701 | // .. CLKACT = 0x1 | |
8702 | // .. ==> 0XF8000168[0:0] = 0x00000001U | |
8703 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8704 | // .. SRCSEL = 0x0 | |
8705 | // .. ==> 0XF8000168[5:4] = 0x00000000U | |
8706 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8707 | // .. DIVISOR = 0x5 | |
8708 | // .. ==> 0XF8000168[13:8] = 0x00000005U | |
8709 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | |
8710 | // .. | |
8711 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), | |
8712 | // .. SRCSEL = 0x0 | |
8713 | // .. ==> 0XF8000170[5:4] = 0x00000000U | |
8714 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8715 | // .. DIVISOR0 = 0xa | |
8716 | // .. ==> 0XF8000170[13:8] = 0x0000000AU | |
8717 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | |
8718 | // .. DIVISOR1 = 0x1 | |
8719 | // .. ==> 0XF8000170[25:20] = 0x00000001U | |
8720 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
8721 | // .. | |
8722 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), | |
8723 | // .. SRCSEL = 0x0 | |
8724 | // .. ==> 0XF8000180[5:4] = 0x00000000U | |
8725 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8726 | // .. DIVISOR0 = 0xa | |
8727 | // .. ==> 0XF8000180[13:8] = 0x0000000AU | |
8728 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | |
8729 | // .. DIVISOR1 = 0x1 | |
8730 | // .. ==> 0XF8000180[25:20] = 0x00000001U | |
8731 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
8732 | // .. | |
8733 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), | |
8734 | // .. SRCSEL = 0x0 | |
8735 | // .. ==> 0XF8000190[5:4] = 0x00000000U | |
8736 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8737 | // .. DIVISOR0 = 0x1e | |
8738 | // .. ==> 0XF8000190[13:8] = 0x0000001EU | |
8739 | // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U | |
8740 | // .. DIVISOR1 = 0x1 | |
8741 | // .. ==> 0XF8000190[25:20] = 0x00000001U | |
8742 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
8743 | // .. | |
8744 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), | |
8745 | // .. SRCSEL = 0x0 | |
8746 | // .. ==> 0XF80001A0[5:4] = 0x00000000U | |
8747 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | |
8748 | // .. DIVISOR0 = 0x14 | |
8749 | // .. ==> 0XF80001A0[13:8] = 0x00000014U | |
8750 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | |
8751 | // .. DIVISOR1 = 0x1 | |
8752 | // .. ==> 0XF80001A0[25:20] = 0x00000001U | |
8753 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | |
8754 | // .. | |
8755 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), | |
8756 | // .. CLK_621_TRUE = 0x1 | |
8757 | // .. ==> 0XF80001C4[0:0] = 0x00000001U | |
8758 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8759 | // .. | |
8760 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | |
8761 | // .. DMA_CPU_2XCLKACT = 0x1 | |
8762 | // .. ==> 0XF800012C[0:0] = 0x00000001U | |
8763 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
8764 | // .. USB0_CPU_1XCLKACT = 0x1 | |
8765 | // .. ==> 0XF800012C[2:2] = 0x00000001U | |
8766 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
8767 | // .. USB1_CPU_1XCLKACT = 0x1 | |
8768 | // .. ==> 0XF800012C[3:3] = 0x00000001U | |
8769 | // .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
8770 | // .. GEM0_CPU_1XCLKACT = 0x1 | |
8771 | // .. ==> 0XF800012C[6:6] = 0x00000001U | |
8772 | // .. ==> MASK : 0x00000040U VAL : 0x00000040U | |
8773 | // .. GEM1_CPU_1XCLKACT = 0x0 | |
8774 | // .. ==> 0XF800012C[7:7] = 0x00000000U | |
8775 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
8776 | // .. SDI0_CPU_1XCLKACT = 0x1 | |
8777 | // .. ==> 0XF800012C[10:10] = 0x00000001U | |
8778 | // .. ==> MASK : 0x00000400U VAL : 0x00000400U | |
8779 | // .. SDI1_CPU_1XCLKACT = 0x0 | |
8780 | // .. ==> 0XF800012C[11:11] = 0x00000000U | |
8781 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
8782 | // .. SPI0_CPU_1XCLKACT = 0x0 | |
8783 | // .. ==> 0XF800012C[14:14] = 0x00000000U | |
8784 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
8785 | // .. SPI1_CPU_1XCLKACT = 0x0 | |
8786 | // .. ==> 0XF800012C[15:15] = 0x00000000U | |
8787 | // .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
8788 | // .. CAN0_CPU_1XCLKACT = 0x0 | |
8789 | // .. ==> 0XF800012C[16:16] = 0x00000000U | |
8790 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
8791 | // .. CAN1_CPU_1XCLKACT = 0x0 | |
8792 | // .. ==> 0XF800012C[17:17] = 0x00000000U | |
8793 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
8794 | // .. I2C0_CPU_1XCLKACT = 0x1 | |
8795 | // .. ==> 0XF800012C[18:18] = 0x00000001U | |
8796 | // .. ==> MASK : 0x00040000U VAL : 0x00040000U | |
8797 | // .. I2C1_CPU_1XCLKACT = 0x1 | |
8798 | // .. ==> 0XF800012C[19:19] = 0x00000001U | |
8799 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
8800 | // .. UART0_CPU_1XCLKACT = 0x0 | |
8801 | // .. ==> 0XF800012C[20:20] = 0x00000000U | |
8802 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
8803 | // .. UART1_CPU_1XCLKACT = 0x1 | |
8804 | // .. ==> 0XF800012C[21:21] = 0x00000001U | |
8805 | // .. ==> MASK : 0x00200000U VAL : 0x00200000U | |
8806 | // .. GPIO_CPU_1XCLKACT = 0x1 | |
8807 | // .. ==> 0XF800012C[22:22] = 0x00000001U | |
8808 | // .. ==> MASK : 0x00400000U VAL : 0x00400000U | |
8809 | // .. LQSPI_CPU_1XCLKACT = 0x1 | |
8810 | // .. ==> 0XF800012C[23:23] = 0x00000001U | |
8811 | // .. ==> MASK : 0x00800000U VAL : 0x00800000U | |
8812 | // .. SMC_CPU_1XCLKACT = 0x1 | |
8813 | // .. ==> 0XF800012C[24:24] = 0x00000001U | |
8814 | // .. ==> MASK : 0x01000000U VAL : 0x01000000U | |
8815 | // .. | |
8816 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), | |
8817 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | |
8818 | // .. START: THIS SHOULD BE BLANK | |
8819 | // .. FINISH: THIS SHOULD BE BLANK | |
8820 | // .. START: LOCK IT BACK | |
8821 | // .. LOCK_KEY = 0X767B | |
8822 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
8823 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
8824 | // .. | |
8825 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
8826 | // .. FINISH: LOCK IT BACK | |
8827 | // FINISH: top | |
8828 | // | |
8829 | EMIT_EXIT(), | |
8830 | ||
8831 | // | |
8832 | }; | |
8833 | ||
8834 | unsigned long ps7_ddr_init_data_1_0[] = { | |
8835 | // START: top | |
8836 | // .. START: DDR INITIALIZATION | |
8837 | // .. .. START: LOCK DDR | |
8838 | // .. .. reg_ddrc_soft_rstb = 0 | |
8839 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | |
8840 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
8841 | // .. .. reg_ddrc_powerdown_en = 0x0 | |
8842 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | |
8843 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
8844 | // .. .. reg_ddrc_data_bus_width = 0x0 | |
8845 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | |
8846 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | |
8847 | // .. .. reg_ddrc_burst8_refresh = 0x0 | |
8848 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | |
8849 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
8850 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | |
8851 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | |
8852 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | |
8853 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | |
8854 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | |
8855 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
8856 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | |
8857 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | |
8858 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
8859 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | |
8860 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | |
8861 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
8862 | // .. .. | |
8863 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | |
8864 | // .. .. FINISH: LOCK DDR | |
8865 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 | |
8866 | // .. .. ==> 0XF8006004[11:0] = 0x00000081U | |
8867 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U | |
8868 | // .. .. reg_ddrc_active_ranks = 0x1 | |
8869 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | |
8870 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | |
8871 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | |
8872 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | |
8873 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | |
8874 | // .. .. reg_ddrc_wr_odt_block = 0x1 | |
8875 | // .. .. ==> 0XF8006004[20:19] = 0x00000001U | |
8876 | // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U | |
8877 | // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 | |
8878 | // .. .. ==> 0XF8006004[21:21] = 0x00000000U | |
8879 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
8880 | // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 | |
8881 | // .. .. ==> 0XF8006004[26:22] = 0x00000000U | |
8882 | // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U | |
8883 | // .. .. reg_ddrc_addrmap_open_bank = 0x0 | |
8884 | // .. .. ==> 0XF8006004[27:27] = 0x00000000U | |
8885 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | |
8886 | // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 | |
8887 | // .. .. ==> 0XF8006004[28:28] = 0x00000000U | |
8888 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | |
8889 | // .. .. | |
8890 | EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), | |
8891 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | |
8892 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | |
8893 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | |
8894 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | |
8895 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | |
8896 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | |
8897 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | |
8898 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | |
8899 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | |
8900 | // .. .. | |
8901 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | |
8902 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | |
8903 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | |
8904 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | |
8905 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | |
8906 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | |
8907 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | |
8908 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | |
8909 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | |
8910 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | |
8911 | // .. .. | |
8912 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | |
8913 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | |
8914 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | |
8915 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | |
8916 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | |
8917 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | |
8918 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | |
8919 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | |
8920 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | |
8921 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | |
8922 | // .. .. | |
8923 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | |
8924 | // .. .. reg_ddrc_t_rc = 0x1a | |
8925 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | |
8926 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | |
8927 | // .. .. reg_ddrc_t_rfc_min = 0xa0 | |
8928 | // .. .. ==> 0XF8006014[13:6] = 0x000000A0U | |
8929 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U | |
8930 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | |
8931 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | |
8932 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | |
8933 | // .. .. | |
8934 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), | |
8935 | // .. .. reg_ddrc_wr2pre = 0x12 | |
8936 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | |
8937 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | |
8938 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | |
8939 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | |
8940 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | |
8941 | // .. .. reg_ddrc_t_faw = 0x16 | |
8942 | // .. .. ==> 0XF8006018[15:10] = 0x00000016U | |
8943 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U | |
8944 | // .. .. reg_ddrc_t_ras_max = 0x24 | |
8945 | // .. .. ==> 0XF8006018[21:16] = 0x00000024U | |
8946 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U | |
8947 | // .. .. reg_ddrc_t_ras_min = 0x13 | |
8948 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | |
8949 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | |
8950 | // .. .. reg_ddrc_t_cke = 0x4 | |
8951 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | |
8952 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | |
8953 | // .. .. | |
8954 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), | |
8955 | // .. .. reg_ddrc_write_latency = 0x5 | |
8956 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | |
8957 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | |
8958 | // .. .. reg_ddrc_rd2wr = 0x7 | |
8959 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | |
8960 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | |
8961 | // .. .. reg_ddrc_wr2rd = 0xe | |
8962 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | |
8963 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | |
8964 | // .. .. reg_ddrc_t_xp = 0x4 | |
8965 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | |
8966 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | |
8967 | // .. .. reg_ddrc_pad_pd = 0x0 | |
8968 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | |
8969 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | |
8970 | // .. .. reg_ddrc_rd2pre = 0x4 | |
8971 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | |
8972 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | |
8973 | // .. .. reg_ddrc_t_rcd = 0x7 | |
8974 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | |
8975 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | |
8976 | // .. .. | |
8977 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | |
8978 | // .. .. reg_ddrc_t_ccd = 0x4 | |
8979 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | |
8980 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | |
8981 | // .. .. reg_ddrc_t_rrd = 0x6 | |
8982 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | |
8983 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | |
8984 | // .. .. reg_ddrc_refresh_margin = 0x2 | |
8985 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | |
8986 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | |
8987 | // .. .. reg_ddrc_t_rp = 0x7 | |
8988 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | |
8989 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | |
8990 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | |
8991 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | |
8992 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | |
8993 | // .. .. reg_ddrc_sdram = 0x1 | |
8994 | // .. .. ==> 0XF8006020[21:21] = 0x00000001U | |
8995 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | |
8996 | // .. .. reg_ddrc_mobile = 0x0 | |
8997 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | |
8998 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
8999 | // .. .. reg_ddrc_clock_stop_en = 0x0 | |
9000 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | |
9001 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
9002 | // .. .. reg_ddrc_read_latency = 0x7 | |
9003 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | |
9004 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | |
9005 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | |
9006 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | |
9007 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | |
9008 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | |
9009 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | |
9010 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | |
9011 | // .. .. reg_ddrc_loopback = 0x0 | |
9012 | // .. .. ==> 0XF8006020[31:31] = 0x00000000U | |
9013 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | |
9014 | // .. .. | |
9015 | EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), | |
9016 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | |
9017 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | |
9018 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9019 | // .. .. reg_ddrc_prefer_write = 0x0 | |
9020 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | |
9021 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9022 | // .. .. reg_ddrc_max_rank_rd = 0xf | |
9023 | // .. .. ==> 0XF8006024[5:2] = 0x0000000FU | |
9024 | // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU | |
9025 | // .. .. reg_ddrc_mr_wr = 0x0 | |
9026 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | |
9027 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
9028 | // .. .. reg_ddrc_mr_addr = 0x0 | |
9029 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | |
9030 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | |
9031 | // .. .. reg_ddrc_mr_data = 0x0 | |
9032 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | |
9033 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | |
9034 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | |
9035 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | |
9036 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
9037 | // .. .. reg_ddrc_mr_type = 0x0 | |
9038 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | |
9039 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | |
9040 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | |
9041 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | |
9042 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | |
9043 | // .. .. | |
9044 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), | |
9045 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | |
9046 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | |
9047 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | |
9048 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | |
9049 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | |
9050 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | |
9051 | // .. .. reg_ddrc_t_mrd = 0x4 | |
9052 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | |
9053 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | |
9054 | // .. .. | |
9055 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | |
9056 | // .. .. reg_ddrc_emr2 = 0x8 | |
9057 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | |
9058 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | |
9059 | // .. .. reg_ddrc_emr3 = 0x0 | |
9060 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | |
9061 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | |
9062 | // .. .. | |
9063 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | |
9064 | // .. .. reg_ddrc_mr = 0x930 | |
9065 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | |
9066 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | |
9067 | // .. .. reg_ddrc_emr = 0x4 | |
9068 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | |
9069 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | |
9070 | // .. .. | |
9071 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | |
9072 | // .. .. reg_ddrc_burst_rdwr = 0x4 | |
9073 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | |
9074 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | |
9075 | // .. .. reg_ddrc_pre_cke_x1024 = 0x105 | |
9076 | // .. .. ==> 0XF8006034[13:4] = 0x00000105U | |
9077 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U | |
9078 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | |
9079 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | |
9080 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | |
9081 | // .. .. reg_ddrc_burstchop = 0x0 | |
9082 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | |
9083 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | |
9084 | // .. .. | |
9085 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), | |
9086 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | |
9087 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | |
9088 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9089 | // .. .. reg_ddrc_dis_dq = 0x0 | |
9090 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | |
9091 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9092 | // .. .. reg_phy_debug_mode = 0x0 | |
9093 | // .. .. ==> 0XF8006038[6:6] = 0x00000000U | |
9094 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
9095 | // .. .. reg_phy_wr_level_start = 0x0 | |
9096 | // .. .. ==> 0XF8006038[7:7] = 0x00000000U | |
9097 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
9098 | // .. .. reg_phy_rd_level_start = 0x0 | |
9099 | // .. .. ==> 0XF8006038[8:8] = 0x00000000U | |
9100 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
9101 | // .. .. reg_phy_dq0_wait_t = 0x0 | |
9102 | // .. .. ==> 0XF8006038[12:9] = 0x00000000U | |
9103 | // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U | |
9104 | // .. .. | |
9105 | EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), | |
9106 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | |
9107 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | |
9108 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | |
9109 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | |
9110 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | |
9111 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | |
9112 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | |
9113 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | |
9114 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | |
9115 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | |
9116 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | |
9117 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | |
9118 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | |
9119 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | |
9120 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | |
9121 | // .. .. | |
9122 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | |
9123 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | |
9124 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | |
9125 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
9126 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | |
9127 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | |
9128 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
9129 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | |
9130 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | |
9131 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | |
9132 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | |
9133 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | |
9134 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | |
9135 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | |
9136 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | |
9137 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | |
9138 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | |
9139 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | |
9140 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | |
9141 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | |
9142 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | |
9143 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | |
9144 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | |
9145 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | |
9146 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | |
9147 | // .. .. | |
9148 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | |
9149 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | |
9150 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | |
9151 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | |
9152 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | |
9153 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | |
9154 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | |
9155 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | |
9156 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | |
9157 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | |
9158 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | |
9159 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | |
9160 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | |
9161 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | |
9162 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | |
9163 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | |
9164 | // .. .. reg_ddrc_addrmap_row_b14 = 0x6 | |
9165 | // .. .. ==> 0XF8006044[23:20] = 0x00000006U | |
9166 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U | |
9167 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | |
9168 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | |
9169 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | |
9170 | // .. .. | |
9171 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), | |
9172 | // .. .. reg_ddrc_rank0_rd_odt = 0x0 | |
9173 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | |
9174 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | |
9175 | // .. .. reg_ddrc_rank0_wr_odt = 0x1 | |
9176 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | |
9177 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | |
9178 | // .. .. reg_ddrc_rank1_rd_odt = 0x1 | |
9179 | // .. .. ==> 0XF8006048[8:6] = 0x00000001U | |
9180 | // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U | |
9181 | // .. .. reg_ddrc_rank1_wr_odt = 0x1 | |
9182 | // .. .. ==> 0XF8006048[11:9] = 0x00000001U | |
9183 | // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
9184 | // .. .. reg_phy_rd_local_odt = 0x0 | |
9185 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | |
9186 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | |
9187 | // .. .. reg_phy_wr_local_odt = 0x3 | |
9188 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | |
9189 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | |
9190 | // .. .. reg_phy_idle_local_odt = 0x3 | |
9191 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | |
9192 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | |
9193 | // .. .. reg_ddrc_rank2_rd_odt = 0x0 | |
9194 | // .. .. ==> 0XF8006048[20:18] = 0x00000000U | |
9195 | // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U | |
9196 | // .. .. reg_ddrc_rank2_wr_odt = 0x0 | |
9197 | // .. .. ==> 0XF8006048[23:21] = 0x00000000U | |
9198 | // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U | |
9199 | // .. .. reg_ddrc_rank3_rd_odt = 0x0 | |
9200 | // .. .. ==> 0XF8006048[26:24] = 0x00000000U | |
9201 | // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
9202 | // .. .. reg_ddrc_rank3_wr_odt = 0x0 | |
9203 | // .. .. ==> 0XF8006048[29:27] = 0x00000000U | |
9204 | // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U | |
9205 | // .. .. | |
9206 | EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), | |
9207 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | |
9208 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | |
9209 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
9210 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | |
9211 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | |
9212 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
9213 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | |
9214 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | |
9215 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | |
9216 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | |
9217 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | |
9218 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
9219 | // .. .. reg_phy_use_fixed_re = 0x1 | |
9220 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | |
9221 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | |
9222 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | |
9223 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | |
9224 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9225 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | |
9226 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | |
9227 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9228 | // .. .. reg_phy_clk_stall_level = 0x0 | |
9229 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | |
9230 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
9231 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | |
9232 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | |
9233 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | |
9234 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | |
9235 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | |
9236 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | |
9237 | // .. .. | |
9238 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | |
9239 | // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 | |
9240 | // .. .. ==> 0XF8006058[7:0] = 0x00000001U | |
9241 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U | |
9242 | // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 | |
9243 | // .. .. ==> 0XF8006058[15:8] = 0x00000001U | |
9244 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U | |
9245 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | |
9246 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | |
9247 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9248 | // .. .. | |
9249 | EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), | |
9250 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | |
9251 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | |
9252 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | |
9253 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | |
9254 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | |
9255 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
9256 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | |
9257 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | |
9258 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | |
9259 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | |
9260 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | |
9261 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | |
9262 | // .. .. | |
9263 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | |
9264 | // .. .. reg_ddrc_pageclose = 0x0 | |
9265 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | |
9266 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9267 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | |
9268 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | |
9269 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | |
9270 | // .. .. reg_ddrc_auto_pre_en = 0x0 | |
9271 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | |
9272 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
9273 | // .. .. reg_ddrc_refresh_update_level = 0x0 | |
9274 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | |
9275 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
9276 | // .. .. reg_ddrc_dis_wc = 0x0 | |
9277 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | |
9278 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
9279 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | |
9280 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | |
9281 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9282 | // .. .. reg_ddrc_selfref_en = 0x0 | |
9283 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | |
9284 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
9285 | // .. .. | |
9286 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | |
9287 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | |
9288 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | |
9289 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | |
9290 | // .. .. reg_arb_go2critical_en = 0x1 | |
9291 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | |
9292 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | |
9293 | // .. .. | |
9294 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | |
9295 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | |
9296 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | |
9297 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | |
9298 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | |
9299 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | |
9300 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | |
9301 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | |
9302 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | |
9303 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | |
9304 | // .. .. | |
9305 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | |
9306 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | |
9307 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | |
9308 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | |
9309 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | |
9310 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | |
9311 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | |
9312 | // .. .. | |
9313 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | |
9314 | // .. .. refresh_timer0_start_value_x32 = 0x0 | |
9315 | // .. .. ==> 0XF80060A0[11:0] = 0x00000000U | |
9316 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U | |
9317 | // .. .. refresh_timer1_start_value_x32 = 0x8 | |
9318 | // .. .. ==> 0XF80060A0[23:12] = 0x00000008U | |
9319 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U | |
9320 | // .. .. | |
9321 | EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), | |
9322 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | |
9323 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | |
9324 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9325 | // .. .. reg_ddrc_ddr3 = 0x1 | |
9326 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | |
9327 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
9328 | // .. .. reg_ddrc_t_mod = 0x200 | |
9329 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | |
9330 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | |
9331 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | |
9332 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | |
9333 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | |
9334 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | |
9335 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | |
9336 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | |
9337 | // .. .. | |
9338 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | |
9339 | // .. .. t_zq_short_interval_x1024 = 0xcb73 | |
9340 | // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U | |
9341 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U | |
9342 | // .. .. dram_rstn_x1024 = 0x69 | |
9343 | // .. .. ==> 0XF80060A8[27:20] = 0x00000069U | |
9344 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U | |
9345 | // .. .. | |
9346 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), | |
9347 | // .. .. deeppowerdown_en = 0x0 | |
9348 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | |
9349 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9350 | // .. .. deeppowerdown_to_x1024 = 0xff | |
9351 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | |
9352 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | |
9353 | // .. .. | |
9354 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | |
9355 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | |
9356 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | |
9357 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | |
9358 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | |
9359 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | |
9360 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | |
9361 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | |
9362 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | |
9363 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
9364 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | |
9365 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | |
9366 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
9367 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | |
9368 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | |
9369 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | |
9370 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | |
9371 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | |
9372 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | |
9373 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | |
9374 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | |
9375 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
9376 | // .. .. | |
9377 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | |
9378 | // .. .. reg_ddrc_2t_delay = 0x0 | |
9379 | // .. .. ==> 0XF80060B4[8:0] = 0x00000000U | |
9380 | // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U | |
9381 | // .. .. reg_ddrc_skip_ocd = 0x1 | |
9382 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | |
9383 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | |
9384 | // .. .. reg_ddrc_dis_pre_bypass = 0x0 | |
9385 | // .. .. ==> 0XF80060B4[10:10] = 0x00000000U | |
9386 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9387 | // .. .. | |
9388 | EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), | |
9389 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | |
9390 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | |
9391 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | |
9392 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | |
9393 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | |
9394 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | |
9395 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | |
9396 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | |
9397 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | |
9398 | // .. .. | |
9399 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | |
9400 | // .. .. START: RESET ECC ERROR | |
9401 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | |
9402 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | |
9403 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
9404 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | |
9405 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | |
9406 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
9407 | // .. .. | |
9408 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | |
9409 | // .. .. FINISH: RESET ECC ERROR | |
9410 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | |
9411 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | |
9412 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9413 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | |
9414 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | |
9415 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9416 | // .. .. | |
9417 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | |
9418 | // .. .. CORR_ECC_LOG_VALID = 0x0 | |
9419 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | |
9420 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9421 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | |
9422 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | |
9423 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | |
9424 | // .. .. | |
9425 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | |
9426 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | |
9427 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | |
9428 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9429 | // .. .. | |
9430 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | |
9431 | // .. .. STAT_NUM_CORR_ERR = 0x0 | |
9432 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | |
9433 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | |
9434 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | |
9435 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | |
9436 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | |
9437 | // .. .. | |
9438 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | |
9439 | // .. .. reg_ddrc_ecc_mode = 0x0 | |
9440 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | |
9441 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | |
9442 | // .. .. reg_ddrc_dis_scrub = 0x1 | |
9443 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | |
9444 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | |
9445 | // .. .. | |
9446 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | |
9447 | // .. .. reg_phy_dif_on = 0x0 | |
9448 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | |
9449 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | |
9450 | // .. .. reg_phy_dif_off = 0x0 | |
9451 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | |
9452 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
9453 | // .. .. | |
9454 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | |
9455 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
9456 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | |
9457 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
9458 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
9459 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | |
9460 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9461 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
9462 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | |
9463 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
9464 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
9465 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | |
9466 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
9467 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
9468 | // .. .. ==> 0XF8006118[4:4] = 0x00000000U | |
9469 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
9470 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
9471 | // .. .. ==> 0XF8006118[5:5] = 0x00000000U | |
9472 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
9473 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
9474 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | |
9475 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
9476 | // .. .. reg_phy_bist_err_clr = 0x0 | |
9477 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | |
9478 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
9479 | // .. .. reg_phy_dq_offset = 0x40 | |
9480 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | |
9481 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
9482 | // .. .. | |
9483 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), | |
9484 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
9485 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | |
9486 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
9487 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
9488 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | |
9489 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9490 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
9491 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | |
9492 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
9493 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
9494 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | |
9495 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
9496 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
9497 | // .. .. ==> 0XF800611C[4:4] = 0x00000000U | |
9498 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
9499 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
9500 | // .. .. ==> 0XF800611C[5:5] = 0x00000000U | |
9501 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
9502 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
9503 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | |
9504 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
9505 | // .. .. reg_phy_bist_err_clr = 0x0 | |
9506 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | |
9507 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
9508 | // .. .. reg_phy_dq_offset = 0x40 | |
9509 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | |
9510 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
9511 | // .. .. | |
9512 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), | |
9513 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
9514 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | |
9515 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
9516 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
9517 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | |
9518 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9519 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
9520 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | |
9521 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
9522 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
9523 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | |
9524 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
9525 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
9526 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | |
9527 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
9528 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
9529 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | |
9530 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
9531 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
9532 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | |
9533 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
9534 | // .. .. reg_phy_bist_err_clr = 0x0 | |
9535 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | |
9536 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
9537 | // .. .. reg_phy_dq_offset = 0x40 | |
9538 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | |
9539 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
9540 | // .. .. | |
9541 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), | |
9542 | // .. .. reg_phy_data_slice_in_use = 0x1 | |
9543 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | |
9544 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
9545 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | |
9546 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | |
9547 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9548 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | |
9549 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | |
9550 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
9551 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | |
9552 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | |
9553 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
9554 | // .. .. reg_phy_board_lpbk_tx = 0x0 | |
9555 | // .. .. ==> 0XF8006124[4:4] = 0x00000000U | |
9556 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
9557 | // .. .. reg_phy_board_lpbk_rx = 0x0 | |
9558 | // .. .. ==> 0XF8006124[5:5] = 0x00000000U | |
9559 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
9560 | // .. .. reg_phy_bist_shift_dq = 0x0 | |
9561 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | |
9562 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | |
9563 | // .. .. reg_phy_bist_err_clr = 0x0 | |
9564 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | |
9565 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | |
9566 | // .. .. reg_phy_dq_offset = 0x40 | |
9567 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | |
9568 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | |
9569 | // .. .. | |
9570 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), | |
9571 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | |
9572 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | |
9573 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | |
9574 | // .. .. reg_phy_gatelvl_init_ratio = 0xb0 | |
9575 | // .. .. ==> 0XF800612C[19:10] = 0x000000B0U | |
9576 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U | |
9577 | // .. .. | |
9578 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), | |
9579 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | |
9580 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | |
9581 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | |
9582 | // .. .. reg_phy_gatelvl_init_ratio = 0xb1 | |
9583 | // .. .. ==> 0XF8006130[19:10] = 0x000000B1U | |
9584 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U | |
9585 | // .. .. | |
9586 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), | |
9587 | // .. .. reg_phy_wrlvl_init_ratio = 0x3 | |
9588 | // .. .. ==> 0XF8006134[9:0] = 0x00000003U | |
9589 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U | |
9590 | // .. .. reg_phy_gatelvl_init_ratio = 0xbc | |
9591 | // .. .. ==> 0XF8006134[19:10] = 0x000000BCU | |
9592 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U | |
9593 | // .. .. | |
9594 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), | |
9595 | // .. .. reg_phy_wrlvl_init_ratio = 0x3 | |
9596 | // .. .. ==> 0XF8006138[9:0] = 0x00000003U | |
9597 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U | |
9598 | // .. .. reg_phy_gatelvl_init_ratio = 0xbb | |
9599 | // .. .. ==> 0XF8006138[19:10] = 0x000000BBU | |
9600 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U | |
9601 | // .. .. | |
9602 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), | |
9603 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
9604 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | |
9605 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
9606 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
9607 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | |
9608 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9609 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
9610 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | |
9611 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9612 | // .. .. | |
9613 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | |
9614 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
9615 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | |
9616 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
9617 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
9618 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | |
9619 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9620 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
9621 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | |
9622 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9623 | // .. .. | |
9624 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | |
9625 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
9626 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | |
9627 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
9628 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
9629 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | |
9630 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9631 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
9632 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | |
9633 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9634 | // .. .. | |
9635 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | |
9636 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | |
9637 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | |
9638 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | |
9639 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | |
9640 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | |
9641 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9642 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | |
9643 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | |
9644 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9645 | // .. .. | |
9646 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | |
9647 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | |
9648 | // .. .. ==> 0XF8006154[9:0] = 0x00000077U | |
9649 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | |
9650 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
9651 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | |
9652 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9653 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
9654 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | |
9655 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9656 | // .. .. | |
9657 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), | |
9658 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | |
9659 | // .. .. ==> 0XF8006158[9:0] = 0x00000077U | |
9660 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | |
9661 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
9662 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | |
9663 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9664 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
9665 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | |
9666 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9667 | // .. .. | |
9668 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), | |
9669 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 | |
9670 | // .. .. ==> 0XF800615C[9:0] = 0x00000083U | |
9671 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U | |
9672 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
9673 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | |
9674 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9675 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
9676 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | |
9677 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9678 | // .. .. | |
9679 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), | |
9680 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 | |
9681 | // .. .. ==> 0XF8006160[9:0] = 0x00000083U | |
9682 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U | |
9683 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | |
9684 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | |
9685 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9686 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | |
9687 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | |
9688 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9689 | // .. .. | |
9690 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), | |
9691 | // .. .. reg_phy_fifo_we_slave_ratio = 0x105 | |
9692 | // .. .. ==> 0XF8006168[10:0] = 0x00000105U | |
9693 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U | |
9694 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
9695 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | |
9696 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
9697 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
9698 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | |
9699 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
9700 | // .. .. | |
9701 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), | |
9702 | // .. .. reg_phy_fifo_we_slave_ratio = 0x106 | |
9703 | // .. .. ==> 0XF800616C[10:0] = 0x00000106U | |
9704 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U | |
9705 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
9706 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | |
9707 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
9708 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
9709 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | |
9710 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
9711 | // .. .. | |
9712 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), | |
9713 | // .. .. reg_phy_fifo_we_slave_ratio = 0x111 | |
9714 | // .. .. ==> 0XF8006170[10:0] = 0x00000111U | |
9715 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U | |
9716 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
9717 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | |
9718 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
9719 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
9720 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | |
9721 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
9722 | // .. .. | |
9723 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), | |
9724 | // .. .. reg_phy_fifo_we_slave_ratio = 0x110 | |
9725 | // .. .. ==> 0XF8006174[10:0] = 0x00000110U | |
9726 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U | |
9727 | // .. .. reg_phy_fifo_we_in_force = 0x0 | |
9728 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | |
9729 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
9730 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | |
9731 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | |
9732 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | |
9733 | // .. .. | |
9734 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), | |
9735 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | |
9736 | // .. .. ==> 0XF800617C[9:0] = 0x000000B7U | |
9737 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | |
9738 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
9739 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | |
9740 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9741 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
9742 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | |
9743 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9744 | // .. .. | |
9745 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), | |
9746 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | |
9747 | // .. .. ==> 0XF8006180[9:0] = 0x000000B7U | |
9748 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | |
9749 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
9750 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | |
9751 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9752 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
9753 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | |
9754 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9755 | // .. .. | |
9756 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), | |
9757 | // .. .. reg_phy_wr_data_slave_ratio = 0xc3 | |
9758 | // .. .. ==> 0XF8006184[9:0] = 0x000000C3U | |
9759 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U | |
9760 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
9761 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | |
9762 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9763 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
9764 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | |
9765 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9766 | // .. .. | |
9767 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), | |
9768 | // .. .. reg_phy_wr_data_slave_ratio = 0xc3 | |
9769 | // .. .. ==> 0XF8006188[9:0] = 0x000000C3U | |
9770 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U | |
9771 | // .. .. reg_phy_wr_data_slave_force = 0x0 | |
9772 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | |
9773 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
9774 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | |
9775 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | |
9776 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | |
9777 | // .. .. | |
9778 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), | |
9779 | // .. .. reg_phy_loopback = 0x0 | |
9780 | // .. .. ==> 0XF8006190[0:0] = 0x00000000U | |
9781 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9782 | // .. .. reg_phy_bl2 = 0x0 | |
9783 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | |
9784 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
9785 | // .. .. reg_phy_at_spd_atpg = 0x0 | |
9786 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | |
9787 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
9788 | // .. .. reg_phy_bist_enable = 0x0 | |
9789 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | |
9790 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
9791 | // .. .. reg_phy_bist_force_err = 0x0 | |
9792 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | |
9793 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
9794 | // .. .. reg_phy_bist_mode = 0x0 | |
9795 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | |
9796 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
9797 | // .. .. reg_phy_invert_clkout = 0x1 | |
9798 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | |
9799 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
9800 | // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 | |
9801 | // .. .. ==> 0XF8006190[8:8] = 0x00000000U | |
9802 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
9803 | // .. .. reg_phy_sel_logic = 0x0 | |
9804 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | |
9805 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
9806 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | |
9807 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | |
9808 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | |
9809 | // .. .. reg_phy_ctrl_slave_force = 0x0 | |
9810 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | |
9811 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
9812 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | |
9813 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | |
9814 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | |
9815 | // .. .. reg_phy_use_rank0_delays = 0x1 | |
9816 | // .. .. ==> 0XF8006190[28:28] = 0x00000001U | |
9817 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | |
9818 | // .. .. reg_phy_lpddr = 0x0 | |
9819 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | |
9820 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | |
9821 | // .. .. reg_phy_cmd_latency = 0x0 | |
9822 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | |
9823 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | |
9824 | // .. .. reg_phy_int_lpbk = 0x0 | |
9825 | // .. .. ==> 0XF8006190[31:31] = 0x00000000U | |
9826 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | |
9827 | // .. .. | |
9828 | EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), | |
9829 | // .. .. reg_phy_wr_rl_delay = 0x2 | |
9830 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | |
9831 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | |
9832 | // .. .. reg_phy_rd_rl_delay = 0x4 | |
9833 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | |
9834 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | |
9835 | // .. .. reg_phy_dll_lock_diff = 0xf | |
9836 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | |
9837 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | |
9838 | // .. .. reg_phy_use_wr_level = 0x1 | |
9839 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | |
9840 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | |
9841 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | |
9842 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | |
9843 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | |
9844 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | |
9845 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | |
9846 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | |
9847 | // .. .. reg_phy_dis_calib_rst = 0x0 | |
9848 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | |
9849 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9850 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | |
9851 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | |
9852 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | |
9853 | // .. .. | |
9854 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | |
9855 | // .. .. reg_arb_page_addr_mask = 0x0 | |
9856 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | |
9857 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | |
9858 | // .. .. | |
9859 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | |
9860 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
9861 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | |
9862 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9863 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
9864 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | |
9865 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9866 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
9867 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | |
9868 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9869 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
9870 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | |
9871 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9872 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
9873 | // .. .. ==> 0XF8006208[19:19] = 0x00000001U | |
9874 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
9875 | // .. .. | |
9876 | EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), | |
9877 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
9878 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | |
9879 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9880 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
9881 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | |
9882 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9883 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
9884 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | |
9885 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9886 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
9887 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | |
9888 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9889 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
9890 | // .. .. ==> 0XF800620C[19:19] = 0x00000001U | |
9891 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
9892 | // .. .. | |
9893 | EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), | |
9894 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
9895 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | |
9896 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9897 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
9898 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | |
9899 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9900 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
9901 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | |
9902 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9903 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
9904 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | |
9905 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9906 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
9907 | // .. .. ==> 0XF8006210[19:19] = 0x00000001U | |
9908 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
9909 | // .. .. | |
9910 | EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), | |
9911 | // .. .. reg_arb_pri_wr_portn = 0x3ff | |
9912 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | |
9913 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9914 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | |
9915 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | |
9916 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9917 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | |
9918 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | |
9919 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9920 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | |
9921 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | |
9922 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9923 | // .. .. reg_arb_dis_rmw_portn = 0x1 | |
9924 | // .. .. ==> 0XF8006214[19:19] = 0x00000001U | |
9925 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
9926 | // .. .. | |
9927 | EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), | |
9928 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
9929 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | |
9930 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9931 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
9932 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | |
9933 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9934 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
9935 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | |
9936 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9937 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
9938 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | |
9939 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9940 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
9941 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | |
9942 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
9943 | // .. .. | |
9944 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | |
9945 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
9946 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | |
9947 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9948 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
9949 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | |
9950 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9951 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
9952 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | |
9953 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9954 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
9955 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | |
9956 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9957 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
9958 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | |
9959 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
9960 | // .. .. | |
9961 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | |
9962 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
9963 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | |
9964 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9965 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
9966 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | |
9967 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9968 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
9969 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | |
9970 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9971 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
9972 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | |
9973 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9974 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
9975 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | |
9976 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
9977 | // .. .. | |
9978 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | |
9979 | // .. .. reg_arb_pri_rd_portn = 0x3ff | |
9980 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | |
9981 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | |
9982 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | |
9983 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | |
9984 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
9985 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | |
9986 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | |
9987 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
9988 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | |
9989 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | |
9990 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | |
9991 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | |
9992 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | |
9993 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | |
9994 | // .. .. | |
9995 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | |
9996 | // .. .. reg_ddrc_lpddr2 = 0x0 | |
9997 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | |
9998 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
9999 | // .. .. reg_ddrc_per_bank_refresh = 0x0 | |
10000 | // .. .. ==> 0XF80062A8[1:1] = 0x00000000U | |
10001 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10002 | // .. .. reg_ddrc_derate_enable = 0x0 | |
10003 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | |
10004 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10005 | // .. .. reg_ddrc_mr4_margin = 0x0 | |
10006 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | |
10007 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | |
10008 | // .. .. | |
10009 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), | |
10010 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | |
10011 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | |
10012 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | |
10013 | // .. .. | |
10014 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | |
10015 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | |
10016 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | |
10017 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | |
10018 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | |
10019 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | |
10020 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | |
10021 | // .. .. reg_ddrc_t_mrw = 0x5 | |
10022 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | |
10023 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | |
10024 | // .. .. | |
10025 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | |
10026 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 | |
10027 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U | |
10028 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U | |
10029 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | |
10030 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | |
10031 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | |
10032 | // .. .. | |
10033 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), | |
10034 | // .. .. START: POLL ON DCI STATUS | |
10035 | // .. .. DONE = 1 | |
10036 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | |
10037 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | |
10038 | // .. .. | |
10039 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | |
10040 | // .. .. FINISH: POLL ON DCI STATUS | |
10041 | // .. .. START: UNLOCK DDR | |
10042 | // .. .. reg_ddrc_soft_rstb = 0x1 | |
10043 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | |
10044 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
10045 | // .. .. reg_ddrc_powerdown_en = 0x0 | |
10046 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | |
10047 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10048 | // .. .. reg_ddrc_data_bus_width = 0x0 | |
10049 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | |
10050 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | |
10051 | // .. .. reg_ddrc_burst8_refresh = 0x0 | |
10052 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | |
10053 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | |
10054 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | |
10055 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | |
10056 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | |
10057 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | |
10058 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | |
10059 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
10060 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | |
10061 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | |
10062 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | |
10063 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | |
10064 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | |
10065 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
10066 | // .. .. | |
10067 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | |
10068 | // .. .. FINISH: UNLOCK DDR | |
10069 | // .. .. START: CHECK DDR STATUS | |
10070 | // .. .. ddrc_reg_operating_mode = 1 | |
10071 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | |
10072 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | |
10073 | // .. .. | |
10074 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | |
10075 | // .. .. FINISH: CHECK DDR STATUS | |
10076 | // .. FINISH: DDR INITIALIZATION | |
10077 | // FINISH: top | |
10078 | // | |
10079 | EMIT_EXIT(), | |
10080 | ||
10081 | // | |
10082 | }; | |
10083 | ||
10084 | unsigned long ps7_mio_init_data_1_0[] = { | |
10085 | // START: top | |
10086 | // .. START: SLCR SETTINGS | |
10087 | // .. UNLOCK_KEY = 0XDF0D | |
10088 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
10089 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
10090 | // .. | |
10091 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
10092 | // .. FINISH: SLCR SETTINGS | |
10093 | // .. START: OCM REMAPPING | |
10094 | // .. FINISH: OCM REMAPPING | |
10095 | // .. START: DDRIOB SETTINGS | |
10096 | // .. INP_POWER = 0x0 | |
10097 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | |
10098 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10099 | // .. INP_TYPE = 0x0 | |
10100 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | |
10101 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
10102 | // .. DCI_UPDATE = 0x0 | |
10103 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | |
10104 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10105 | // .. TERM_EN = 0x0 | |
10106 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | |
10107 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
10108 | // .. DCR_TYPE = 0x0 | |
10109 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | |
10110 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
10111 | // .. IBUF_DISABLE_MODE = 0x0 | |
10112 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | |
10113 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10114 | // .. TERM_DISABLE_MODE = 0x0 | |
10115 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | |
10116 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10117 | // .. OUTPUT_EN = 0x3 | |
10118 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | |
10119 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10120 | // .. PULLUP_EN = 0x0 | |
10121 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | |
10122 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10123 | // .. | |
10124 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | |
10125 | // .. INP_POWER = 0x0 | |
10126 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | |
10127 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10128 | // .. INP_TYPE = 0x0 | |
10129 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | |
10130 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
10131 | // .. DCI_UPDATE = 0x0 | |
10132 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | |
10133 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10134 | // .. TERM_EN = 0x0 | |
10135 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | |
10136 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
10137 | // .. DCR_TYPE = 0x0 | |
10138 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | |
10139 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
10140 | // .. IBUF_DISABLE_MODE = 0x0 | |
10141 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | |
10142 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10143 | // .. TERM_DISABLE_MODE = 0x0 | |
10144 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | |
10145 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10146 | // .. OUTPUT_EN = 0x3 | |
10147 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | |
10148 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10149 | // .. PULLUP_EN = 0x0 | |
10150 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | |
10151 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10152 | // .. | |
10153 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | |
10154 | // .. INP_POWER = 0x0 | |
10155 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | |
10156 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10157 | // .. INP_TYPE = 0x1 | |
10158 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | |
10159 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | |
10160 | // .. DCI_UPDATE = 0x0 | |
10161 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | |
10162 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10163 | // .. TERM_EN = 0x1 | |
10164 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | |
10165 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
10166 | // .. DCR_TYPE = 0x3 | |
10167 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | |
10168 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
10169 | // .. IBUF_DISABLE_MODE = 0 | |
10170 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | |
10171 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10172 | // .. TERM_DISABLE_MODE = 0 | |
10173 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | |
10174 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10175 | // .. OUTPUT_EN = 0x3 | |
10176 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | |
10177 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10178 | // .. PULLUP_EN = 0x0 | |
10179 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | |
10180 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10181 | // .. | |
10182 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | |
10183 | // .. INP_POWER = 0x0 | |
10184 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | |
10185 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10186 | // .. INP_TYPE = 0x1 | |
10187 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | |
10188 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | |
10189 | // .. DCI_UPDATE = 0x0 | |
10190 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | |
10191 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10192 | // .. TERM_EN = 0x1 | |
10193 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | |
10194 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
10195 | // .. DCR_TYPE = 0x3 | |
10196 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | |
10197 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
10198 | // .. IBUF_DISABLE_MODE = 0 | |
10199 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | |
10200 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10201 | // .. TERM_DISABLE_MODE = 0 | |
10202 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | |
10203 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10204 | // .. OUTPUT_EN = 0x3 | |
10205 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | |
10206 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10207 | // .. PULLUP_EN = 0x0 | |
10208 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | |
10209 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10210 | // .. | |
10211 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | |
10212 | // .. INP_POWER = 0x0 | |
10213 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | |
10214 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10215 | // .. INP_TYPE = 0x2 | |
10216 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | |
10217 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | |
10218 | // .. DCI_UPDATE = 0x0 | |
10219 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | |
10220 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10221 | // .. TERM_EN = 0x1 | |
10222 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | |
10223 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
10224 | // .. DCR_TYPE = 0x3 | |
10225 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | |
10226 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
10227 | // .. IBUF_DISABLE_MODE = 0 | |
10228 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | |
10229 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10230 | // .. TERM_DISABLE_MODE = 0 | |
10231 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | |
10232 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10233 | // .. OUTPUT_EN = 0x3 | |
10234 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | |
10235 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10236 | // .. PULLUP_EN = 0x0 | |
10237 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | |
10238 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10239 | // .. | |
10240 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | |
10241 | // .. INP_POWER = 0x0 | |
10242 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | |
10243 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10244 | // .. INP_TYPE = 0x2 | |
10245 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | |
10246 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | |
10247 | // .. DCI_UPDATE = 0x0 | |
10248 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | |
10249 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10250 | // .. TERM_EN = 0x1 | |
10251 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | |
10252 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
10253 | // .. DCR_TYPE = 0x3 | |
10254 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | |
10255 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | |
10256 | // .. IBUF_DISABLE_MODE = 0 | |
10257 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | |
10258 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10259 | // .. TERM_DISABLE_MODE = 0 | |
10260 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | |
10261 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10262 | // .. OUTPUT_EN = 0x3 | |
10263 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | |
10264 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10265 | // .. PULLUP_EN = 0x0 | |
10266 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | |
10267 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10268 | // .. | |
10269 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | |
10270 | // .. INP_POWER = 0x0 | |
10271 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | |
10272 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10273 | // .. INP_TYPE = 0x0 | |
10274 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | |
10275 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
10276 | // .. DCI_UPDATE = 0x0 | |
10277 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | |
10278 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10279 | // .. TERM_EN = 0x0 | |
10280 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | |
10281 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
10282 | // .. DCR_TYPE = 0x0 | |
10283 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | |
10284 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
10285 | // .. IBUF_DISABLE_MODE = 0x0 | |
10286 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | |
10287 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
10288 | // .. TERM_DISABLE_MODE = 0x0 | |
10289 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | |
10290 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10291 | // .. OUTPUT_EN = 0x3 | |
10292 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | |
10293 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | |
10294 | // .. PULLUP_EN = 0x0 | |
10295 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | |
10296 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
10297 | // .. | |
10298 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | |
10299 | // .. DRIVE_P = 0x1c | |
10300 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | |
10301 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
10302 | // .. DRIVE_N = 0xc | |
10303 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | |
10304 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
10305 | // .. SLEW_P = 0x3 | |
10306 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | |
10307 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | |
10308 | // .. SLEW_N = 0x3 | |
10309 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | |
10310 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | |
10311 | // .. GTL = 0x0 | |
10312 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | |
10313 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
10314 | // .. RTERM = 0x0 | |
10315 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | |
10316 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
10317 | // .. | |
10318 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | |
10319 | // .. DRIVE_P = 0x1c | |
10320 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | |
10321 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
10322 | // .. DRIVE_N = 0xc | |
10323 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | |
10324 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
10325 | // .. SLEW_P = 0x6 | |
10326 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | |
10327 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
10328 | // .. SLEW_N = 0x1f | |
10329 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | |
10330 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
10331 | // .. GTL = 0x0 | |
10332 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | |
10333 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
10334 | // .. RTERM = 0x0 | |
10335 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | |
10336 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
10337 | // .. | |
10338 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | |
10339 | // .. DRIVE_P = 0x1c | |
10340 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | |
10341 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
10342 | // .. DRIVE_N = 0xc | |
10343 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | |
10344 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
10345 | // .. SLEW_P = 0x6 | |
10346 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | |
10347 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
10348 | // .. SLEW_N = 0x1f | |
10349 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | |
10350 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
10351 | // .. GTL = 0x0 | |
10352 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | |
10353 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
10354 | // .. RTERM = 0x0 | |
10355 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | |
10356 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
10357 | // .. | |
10358 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | |
10359 | // .. DRIVE_P = 0x1c | |
10360 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | |
10361 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | |
10362 | // .. DRIVE_N = 0xc | |
10363 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | |
10364 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | |
10365 | // .. SLEW_P = 0x6 | |
10366 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | |
10367 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | |
10368 | // .. SLEW_N = 0x1f | |
10369 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | |
10370 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | |
10371 | // .. GTL = 0x0 | |
10372 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | |
10373 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | |
10374 | // .. RTERM = 0x0 | |
10375 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | |
10376 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | |
10377 | // .. | |
10378 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | |
10379 | // .. VREF_INT_EN = 0x1 | |
10380 | // .. ==> 0XF8000B6C[0:0] = 0x00000001U | |
10381 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
10382 | // .. VREF_SEL = 0x4 | |
10383 | // .. ==> 0XF8000B6C[4:1] = 0x00000004U | |
10384 | // .. ==> MASK : 0x0000001EU VAL : 0x00000008U | |
10385 | // .. VREF_EXT_EN = 0x0 | |
10386 | // .. ==> 0XF8000B6C[6:5] = 0x00000000U | |
10387 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | |
10388 | // .. VREF_PULLUP_EN = 0x0 | |
10389 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | |
10390 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | |
10391 | // .. REFIO_EN = 0x1 | |
10392 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | |
10393 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | |
10394 | // .. REFIO_PULLUP_EN = 0x0 | |
10395 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | |
10396 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10397 | // .. DRST_B_PULLUP_EN = 0x0 | |
10398 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | |
10399 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10400 | // .. CKE_PULLUP_EN = 0x0 | |
10401 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | |
10402 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | |
10403 | // .. | |
10404 | EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), | |
10405 | // .. .. START: ASSERT RESET | |
10406 | // .. .. RESET = 1 | |
10407 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | |
10408 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
10409 | // .. .. VRN_OUT = 0x1 | |
10410 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
10411 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
10412 | // .. .. | |
10413 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), | |
10414 | // .. .. FINISH: ASSERT RESET | |
10415 | // .. .. START: DEASSERT RESET | |
10416 | // .. .. RESET = 0 | |
10417 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | |
10418 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10419 | // .. .. VRN_OUT = 0x1 | |
10420 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
10421 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
10422 | // .. .. | |
10423 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | |
10424 | // .. .. FINISH: DEASSERT RESET | |
10425 | // .. .. RESET = 0x1 | |
10426 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | |
10427 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
10428 | // .. .. ENABLE = 0x1 | |
10429 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | |
10430 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10431 | // .. .. VRP_TRI = 0x0 | |
10432 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | |
10433 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10434 | // .. .. VRN_TRI = 0x0 | |
10435 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | |
10436 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
10437 | // .. .. VRP_OUT = 0x0 | |
10438 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | |
10439 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | |
10440 | // .. .. VRN_OUT = 0x1 | |
10441 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | |
10442 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | |
10443 | // .. .. NREF_OPT1 = 0x0 | |
10444 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | |
10445 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | |
10446 | // .. .. NREF_OPT2 = 0x0 | |
10447 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | |
10448 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | |
10449 | // .. .. NREF_OPT4 = 0x1 | |
10450 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | |
10451 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | |
10452 | // .. .. PREF_OPT1 = 0x0 | |
10453 | // .. .. ==> 0XF8000B70[16:14] = 0x00000000U | |
10454 | // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U | |
10455 | // .. .. PREF_OPT2 = 0x0 | |
10456 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | |
10457 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | |
10458 | // .. .. UPDATE_CONTROL = 0x0 | |
10459 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | |
10460 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
10461 | // .. .. INIT_COMPLETE = 0x0 | |
10462 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | |
10463 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
10464 | // .. .. TST_CLK = 0x0 | |
10465 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | |
10466 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
10467 | // .. .. TST_HLN = 0x0 | |
10468 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | |
10469 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
10470 | // .. .. TST_HLP = 0x0 | |
10471 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | |
10472 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
10473 | // .. .. TST_RST = 0x0 | |
10474 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | |
10475 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | |
10476 | // .. .. INT_DCI_EN = 0x0 | |
10477 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | |
10478 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | |
10479 | // .. .. | |
10480 | EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), | |
10481 | // .. FINISH: DDRIOB SETTINGS | |
10482 | // .. START: MIO PROGRAMMING | |
10483 | // .. TRI_ENABLE = 0 | |
10484 | // .. ==> 0XF8000700[0:0] = 0x00000000U | |
10485 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10486 | // .. L0_SEL = 0 | |
10487 | // .. ==> 0XF8000700[1:1] = 0x00000000U | |
10488 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10489 | // .. L1_SEL = 0 | |
10490 | // .. ==> 0XF8000700[2:2] = 0x00000000U | |
10491 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10492 | // .. L2_SEL = 0 | |
10493 | // .. ==> 0XF8000700[4:3] = 0x00000000U | |
10494 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10495 | // .. L3_SEL = 0 | |
10496 | // .. ==> 0XF8000700[7:5] = 0x00000000U | |
10497 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10498 | // .. Speed = 0 | |
10499 | // .. ==> 0XF8000700[8:8] = 0x00000000U | |
10500 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10501 | // .. IO_Type = 3 | |
10502 | // .. ==> 0XF8000700[11:9] = 0x00000003U | |
10503 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10504 | // .. PULLUP = 0 | |
10505 | // .. ==> 0XF8000700[12:12] = 0x00000000U | |
10506 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10507 | // .. DisableRcvr = 0 | |
10508 | // .. ==> 0XF8000700[13:13] = 0x00000000U | |
10509 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10510 | // .. | |
10511 | EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), | |
10512 | // .. TRI_ENABLE = 0 | |
10513 | // .. ==> 0XF8000704[0:0] = 0x00000000U | |
10514 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10515 | // .. L0_SEL = 1 | |
10516 | // .. ==> 0XF8000704[1:1] = 0x00000001U | |
10517 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10518 | // .. L1_SEL = 0 | |
10519 | // .. ==> 0XF8000704[2:2] = 0x00000000U | |
10520 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10521 | // .. L2_SEL = 0 | |
10522 | // .. ==> 0XF8000704[4:3] = 0x00000000U | |
10523 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10524 | // .. L3_SEL = 0 | |
10525 | // .. ==> 0XF8000704[7:5] = 0x00000000U | |
10526 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10527 | // .. Speed = 0 | |
10528 | // .. ==> 0XF8000704[8:8] = 0x00000000U | |
10529 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10530 | // .. IO_Type = 3 | |
10531 | // .. ==> 0XF8000704[11:9] = 0x00000003U | |
10532 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10533 | // .. PULLUP = 0 | |
10534 | // .. ==> 0XF8000704[12:12] = 0x00000000U | |
10535 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10536 | // .. DisableRcvr = 0 | |
10537 | // .. ==> 0XF8000704[13:13] = 0x00000000U | |
10538 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10539 | // .. | |
10540 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), | |
10541 | // .. TRI_ENABLE = 0 | |
10542 | // .. ==> 0XF8000708[0:0] = 0x00000000U | |
10543 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10544 | // .. L0_SEL = 1 | |
10545 | // .. ==> 0XF8000708[1:1] = 0x00000001U | |
10546 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10547 | // .. L1_SEL = 0 | |
10548 | // .. ==> 0XF8000708[2:2] = 0x00000000U | |
10549 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10550 | // .. L2_SEL = 0 | |
10551 | // .. ==> 0XF8000708[4:3] = 0x00000000U | |
10552 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10553 | // .. L3_SEL = 0 | |
10554 | // .. ==> 0XF8000708[7:5] = 0x00000000U | |
10555 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10556 | // .. Speed = 0 | |
10557 | // .. ==> 0XF8000708[8:8] = 0x00000000U | |
10558 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10559 | // .. IO_Type = 3 | |
10560 | // .. ==> 0XF8000708[11:9] = 0x00000003U | |
10561 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10562 | // .. PULLUP = 0 | |
10563 | // .. ==> 0XF8000708[12:12] = 0x00000000U | |
10564 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10565 | // .. DisableRcvr = 0 | |
10566 | // .. ==> 0XF8000708[13:13] = 0x00000000U | |
10567 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10568 | // .. | |
10569 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), | |
10570 | // .. TRI_ENABLE = 0 | |
10571 | // .. ==> 0XF800070C[0:0] = 0x00000000U | |
10572 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10573 | // .. L0_SEL = 1 | |
10574 | // .. ==> 0XF800070C[1:1] = 0x00000001U | |
10575 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10576 | // .. L1_SEL = 0 | |
10577 | // .. ==> 0XF800070C[2:2] = 0x00000000U | |
10578 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10579 | // .. L2_SEL = 0 | |
10580 | // .. ==> 0XF800070C[4:3] = 0x00000000U | |
10581 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10582 | // .. L3_SEL = 0 | |
10583 | // .. ==> 0XF800070C[7:5] = 0x00000000U | |
10584 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10585 | // .. Speed = 0 | |
10586 | // .. ==> 0XF800070C[8:8] = 0x00000000U | |
10587 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10588 | // .. IO_Type = 3 | |
10589 | // .. ==> 0XF800070C[11:9] = 0x00000003U | |
10590 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10591 | // .. PULLUP = 0 | |
10592 | // .. ==> 0XF800070C[12:12] = 0x00000000U | |
10593 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10594 | // .. DisableRcvr = 0 | |
10595 | // .. ==> 0XF800070C[13:13] = 0x00000000U | |
10596 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10597 | // .. | |
10598 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), | |
10599 | // .. TRI_ENABLE = 0 | |
10600 | // .. ==> 0XF8000710[0:0] = 0x00000000U | |
10601 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10602 | // .. L0_SEL = 1 | |
10603 | // .. ==> 0XF8000710[1:1] = 0x00000001U | |
10604 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10605 | // .. L1_SEL = 0 | |
10606 | // .. ==> 0XF8000710[2:2] = 0x00000000U | |
10607 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10608 | // .. L2_SEL = 0 | |
10609 | // .. ==> 0XF8000710[4:3] = 0x00000000U | |
10610 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10611 | // .. L3_SEL = 0 | |
10612 | // .. ==> 0XF8000710[7:5] = 0x00000000U | |
10613 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10614 | // .. Speed = 0 | |
10615 | // .. ==> 0XF8000710[8:8] = 0x00000000U | |
10616 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10617 | // .. IO_Type = 3 | |
10618 | // .. ==> 0XF8000710[11:9] = 0x00000003U | |
10619 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10620 | // .. PULLUP = 0 | |
10621 | // .. ==> 0XF8000710[12:12] = 0x00000000U | |
10622 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10623 | // .. DisableRcvr = 0 | |
10624 | // .. ==> 0XF8000710[13:13] = 0x00000000U | |
10625 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10626 | // .. | |
10627 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), | |
10628 | // .. TRI_ENABLE = 0 | |
10629 | // .. ==> 0XF8000714[0:0] = 0x00000000U | |
10630 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10631 | // .. L0_SEL = 1 | |
10632 | // .. ==> 0XF8000714[1:1] = 0x00000001U | |
10633 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10634 | // .. L1_SEL = 0 | |
10635 | // .. ==> 0XF8000714[2:2] = 0x00000000U | |
10636 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10637 | // .. L2_SEL = 0 | |
10638 | // .. ==> 0XF8000714[4:3] = 0x00000000U | |
10639 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10640 | // .. L3_SEL = 0 | |
10641 | // .. ==> 0XF8000714[7:5] = 0x00000000U | |
10642 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10643 | // .. Speed = 0 | |
10644 | // .. ==> 0XF8000714[8:8] = 0x00000000U | |
10645 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10646 | // .. IO_Type = 3 | |
10647 | // .. ==> 0XF8000714[11:9] = 0x00000003U | |
10648 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10649 | // .. PULLUP = 0 | |
10650 | // .. ==> 0XF8000714[12:12] = 0x00000000U | |
10651 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10652 | // .. DisableRcvr = 0 | |
10653 | // .. ==> 0XF8000714[13:13] = 0x00000000U | |
10654 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10655 | // .. | |
10656 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), | |
10657 | // .. TRI_ENABLE = 0 | |
10658 | // .. ==> 0XF8000718[0:0] = 0x00000000U | |
10659 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10660 | // .. L0_SEL = 1 | |
10661 | // .. ==> 0XF8000718[1:1] = 0x00000001U | |
10662 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10663 | // .. L1_SEL = 0 | |
10664 | // .. ==> 0XF8000718[2:2] = 0x00000000U | |
10665 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10666 | // .. L2_SEL = 0 | |
10667 | // .. ==> 0XF8000718[4:3] = 0x00000000U | |
10668 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10669 | // .. L3_SEL = 0 | |
10670 | // .. ==> 0XF8000718[7:5] = 0x00000000U | |
10671 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10672 | // .. Speed = 0 | |
10673 | // .. ==> 0XF8000718[8:8] = 0x00000000U | |
10674 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10675 | // .. IO_Type = 3 | |
10676 | // .. ==> 0XF8000718[11:9] = 0x00000003U | |
10677 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10678 | // .. PULLUP = 0 | |
10679 | // .. ==> 0XF8000718[12:12] = 0x00000000U | |
10680 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10681 | // .. DisableRcvr = 0 | |
10682 | // .. ==> 0XF8000718[13:13] = 0x00000000U | |
10683 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10684 | // .. | |
10685 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), | |
10686 | // .. TRI_ENABLE = 0 | |
10687 | // .. ==> 0XF800071C[0:0] = 0x00000000U | |
10688 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10689 | // .. L0_SEL = 0 | |
10690 | // .. ==> 0XF800071C[1:1] = 0x00000000U | |
10691 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10692 | // .. L1_SEL = 0 | |
10693 | // .. ==> 0XF800071C[2:2] = 0x00000000U | |
10694 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10695 | // .. L2_SEL = 0 | |
10696 | // .. ==> 0XF800071C[4:3] = 0x00000000U | |
10697 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10698 | // .. L3_SEL = 0 | |
10699 | // .. ==> 0XF800071C[7:5] = 0x00000000U | |
10700 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10701 | // .. Speed = 0 | |
10702 | // .. ==> 0XF800071C[8:8] = 0x00000000U | |
10703 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10704 | // .. IO_Type = 3 | |
10705 | // .. ==> 0XF800071C[11:9] = 0x00000003U | |
10706 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10707 | // .. PULLUP = 0 | |
10708 | // .. ==> 0XF800071C[12:12] = 0x00000000U | |
10709 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10710 | // .. DisableRcvr = 0 | |
10711 | // .. ==> 0XF800071C[13:13] = 0x00000000U | |
10712 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10713 | // .. | |
10714 | EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), | |
10715 | // .. TRI_ENABLE = 0 | |
10716 | // .. ==> 0XF8000720[0:0] = 0x00000000U | |
10717 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10718 | // .. L0_SEL = 1 | |
10719 | // .. ==> 0XF8000720[1:1] = 0x00000001U | |
10720 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10721 | // .. L1_SEL = 0 | |
10722 | // .. ==> 0XF8000720[2:2] = 0x00000000U | |
10723 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10724 | // .. L2_SEL = 0 | |
10725 | // .. ==> 0XF8000720[4:3] = 0x00000000U | |
10726 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10727 | // .. L3_SEL = 0 | |
10728 | // .. ==> 0XF8000720[7:5] = 0x00000000U | |
10729 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10730 | // .. Speed = 0 | |
10731 | // .. ==> 0XF8000720[8:8] = 0x00000000U | |
10732 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10733 | // .. IO_Type = 3 | |
10734 | // .. ==> 0XF8000720[11:9] = 0x00000003U | |
10735 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10736 | // .. PULLUP = 0 | |
10737 | // .. ==> 0XF8000720[12:12] = 0x00000000U | |
10738 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10739 | // .. DisableRcvr = 0 | |
10740 | // .. ==> 0XF8000720[13:13] = 0x00000000U | |
10741 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10742 | // .. | |
10743 | EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), | |
10744 | // .. TRI_ENABLE = 0 | |
10745 | // .. ==> 0XF8000724[0:0] = 0x00000000U | |
10746 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10747 | // .. L0_SEL = 0 | |
10748 | // .. ==> 0XF8000724[1:1] = 0x00000000U | |
10749 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10750 | // .. L1_SEL = 0 | |
10751 | // .. ==> 0XF8000724[2:2] = 0x00000000U | |
10752 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10753 | // .. L2_SEL = 0 | |
10754 | // .. ==> 0XF8000724[4:3] = 0x00000000U | |
10755 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10756 | // .. L3_SEL = 0 | |
10757 | // .. ==> 0XF8000724[7:5] = 0x00000000U | |
10758 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10759 | // .. Speed = 0 | |
10760 | // .. ==> 0XF8000724[8:8] = 0x00000000U | |
10761 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10762 | // .. IO_Type = 3 | |
10763 | // .. ==> 0XF8000724[11:9] = 0x00000003U | |
10764 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10765 | // .. PULLUP = 0 | |
10766 | // .. ==> 0XF8000724[12:12] = 0x00000000U | |
10767 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10768 | // .. DisableRcvr = 0 | |
10769 | // .. ==> 0XF8000724[13:13] = 0x00000000U | |
10770 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10771 | // .. | |
10772 | EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), | |
10773 | // .. TRI_ENABLE = 0 | |
10774 | // .. ==> 0XF8000728[0:0] = 0x00000000U | |
10775 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10776 | // .. L0_SEL = 0 | |
10777 | // .. ==> 0XF8000728[1:1] = 0x00000000U | |
10778 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10779 | // .. L1_SEL = 0 | |
10780 | // .. ==> 0XF8000728[2:2] = 0x00000000U | |
10781 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10782 | // .. L2_SEL = 0 | |
10783 | // .. ==> 0XF8000728[4:3] = 0x00000000U | |
10784 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10785 | // .. L3_SEL = 0 | |
10786 | // .. ==> 0XF8000728[7:5] = 0x00000000U | |
10787 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10788 | // .. Speed = 0 | |
10789 | // .. ==> 0XF8000728[8:8] = 0x00000000U | |
10790 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10791 | // .. IO_Type = 3 | |
10792 | // .. ==> 0XF8000728[11:9] = 0x00000003U | |
10793 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10794 | // .. PULLUP = 0 | |
10795 | // .. ==> 0XF8000728[12:12] = 0x00000000U | |
10796 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10797 | // .. DisableRcvr = 0 | |
10798 | // .. ==> 0XF8000728[13:13] = 0x00000000U | |
10799 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10800 | // .. | |
10801 | EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), | |
10802 | // .. TRI_ENABLE = 0 | |
10803 | // .. ==> 0XF800072C[0:0] = 0x00000000U | |
10804 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10805 | // .. L0_SEL = 0 | |
10806 | // .. ==> 0XF800072C[1:1] = 0x00000000U | |
10807 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10808 | // .. L1_SEL = 0 | |
10809 | // .. ==> 0XF800072C[2:2] = 0x00000000U | |
10810 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10811 | // .. L2_SEL = 0 | |
10812 | // .. ==> 0XF800072C[4:3] = 0x00000000U | |
10813 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10814 | // .. L3_SEL = 0 | |
10815 | // .. ==> 0XF800072C[7:5] = 0x00000000U | |
10816 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10817 | // .. Speed = 0 | |
10818 | // .. ==> 0XF800072C[8:8] = 0x00000000U | |
10819 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10820 | // .. IO_Type = 3 | |
10821 | // .. ==> 0XF800072C[11:9] = 0x00000003U | |
10822 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10823 | // .. PULLUP = 0 | |
10824 | // .. ==> 0XF800072C[12:12] = 0x00000000U | |
10825 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10826 | // .. DisableRcvr = 0 | |
10827 | // .. ==> 0XF800072C[13:13] = 0x00000000U | |
10828 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10829 | // .. | |
10830 | EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), | |
10831 | // .. TRI_ENABLE = 0 | |
10832 | // .. ==> 0XF8000730[0:0] = 0x00000000U | |
10833 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10834 | // .. L0_SEL = 0 | |
10835 | // .. ==> 0XF8000730[1:1] = 0x00000000U | |
10836 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10837 | // .. L1_SEL = 0 | |
10838 | // .. ==> 0XF8000730[2:2] = 0x00000000U | |
10839 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10840 | // .. L2_SEL = 0 | |
10841 | // .. ==> 0XF8000730[4:3] = 0x00000000U | |
10842 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10843 | // .. L3_SEL = 0 | |
10844 | // .. ==> 0XF8000730[7:5] = 0x00000000U | |
10845 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10846 | // .. Speed = 0 | |
10847 | // .. ==> 0XF8000730[8:8] = 0x00000000U | |
10848 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10849 | // .. IO_Type = 3 | |
10850 | // .. ==> 0XF8000730[11:9] = 0x00000003U | |
10851 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10852 | // .. PULLUP = 0 | |
10853 | // .. ==> 0XF8000730[12:12] = 0x00000000U | |
10854 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10855 | // .. DisableRcvr = 0 | |
10856 | // .. ==> 0XF8000730[13:13] = 0x00000000U | |
10857 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10858 | // .. | |
10859 | EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), | |
10860 | // .. TRI_ENABLE = 0 | |
10861 | // .. ==> 0XF8000734[0:0] = 0x00000000U | |
10862 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10863 | // .. L0_SEL = 0 | |
10864 | // .. ==> 0XF8000734[1:1] = 0x00000000U | |
10865 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10866 | // .. L1_SEL = 0 | |
10867 | // .. ==> 0XF8000734[2:2] = 0x00000000U | |
10868 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10869 | // .. L2_SEL = 0 | |
10870 | // .. ==> 0XF8000734[4:3] = 0x00000000U | |
10871 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10872 | // .. L3_SEL = 0 | |
10873 | // .. ==> 0XF8000734[7:5] = 0x00000000U | |
10874 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10875 | // .. Speed = 0 | |
10876 | // .. ==> 0XF8000734[8:8] = 0x00000000U | |
10877 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10878 | // .. IO_Type = 3 | |
10879 | // .. ==> 0XF8000734[11:9] = 0x00000003U | |
10880 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10881 | // .. PULLUP = 0 | |
10882 | // .. ==> 0XF8000734[12:12] = 0x00000000U | |
10883 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10884 | // .. DisableRcvr = 0 | |
10885 | // .. ==> 0XF8000734[13:13] = 0x00000000U | |
10886 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10887 | // .. | |
10888 | EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), | |
10889 | // .. TRI_ENABLE = 0 | |
10890 | // .. ==> 0XF8000738[0:0] = 0x00000000U | |
10891 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10892 | // .. L0_SEL = 0 | |
10893 | // .. ==> 0XF8000738[1:1] = 0x00000000U | |
10894 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10895 | // .. L1_SEL = 0 | |
10896 | // .. ==> 0XF8000738[2:2] = 0x00000000U | |
10897 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10898 | // .. L2_SEL = 0 | |
10899 | // .. ==> 0XF8000738[4:3] = 0x00000000U | |
10900 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10901 | // .. L3_SEL = 0 | |
10902 | // .. ==> 0XF8000738[7:5] = 0x00000000U | |
10903 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10904 | // .. Speed = 0 | |
10905 | // .. ==> 0XF8000738[8:8] = 0x00000000U | |
10906 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10907 | // .. IO_Type = 3 | |
10908 | // .. ==> 0XF8000738[11:9] = 0x00000003U | |
10909 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10910 | // .. PULLUP = 0 | |
10911 | // .. ==> 0XF8000738[12:12] = 0x00000000U | |
10912 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10913 | // .. DisableRcvr = 0 | |
10914 | // .. ==> 0XF8000738[13:13] = 0x00000000U | |
10915 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10916 | // .. | |
10917 | EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), | |
10918 | // .. TRI_ENABLE = 0 | |
10919 | // .. ==> 0XF800073C[0:0] = 0x00000000U | |
10920 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10921 | // .. L0_SEL = 0 | |
10922 | // .. ==> 0XF800073C[1:1] = 0x00000000U | |
10923 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
10924 | // .. L1_SEL = 0 | |
10925 | // .. ==> 0XF800073C[2:2] = 0x00000000U | |
10926 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10927 | // .. L2_SEL = 0 | |
10928 | // .. ==> 0XF800073C[4:3] = 0x00000000U | |
10929 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10930 | // .. L3_SEL = 0 | |
10931 | // .. ==> 0XF800073C[7:5] = 0x00000000U | |
10932 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10933 | // .. Speed = 0 | |
10934 | // .. ==> 0XF800073C[8:8] = 0x00000000U | |
10935 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10936 | // .. IO_Type = 3 | |
10937 | // .. ==> 0XF800073C[11:9] = 0x00000003U | |
10938 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | |
10939 | // .. PULLUP = 0 | |
10940 | // .. ==> 0XF800073C[12:12] = 0x00000000U | |
10941 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10942 | // .. DisableRcvr = 0 | |
10943 | // .. ==> 0XF800073C[13:13] = 0x00000000U | |
10944 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10945 | // .. | |
10946 | EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), | |
10947 | // .. TRI_ENABLE = 0 | |
10948 | // .. ==> 0XF8000740[0:0] = 0x00000000U | |
10949 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10950 | // .. L0_SEL = 1 | |
10951 | // .. ==> 0XF8000740[1:1] = 0x00000001U | |
10952 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10953 | // .. L1_SEL = 0 | |
10954 | // .. ==> 0XF8000740[2:2] = 0x00000000U | |
10955 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10956 | // .. L2_SEL = 0 | |
10957 | // .. ==> 0XF8000740[4:3] = 0x00000000U | |
10958 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10959 | // .. L3_SEL = 0 | |
10960 | // .. ==> 0XF8000740[7:5] = 0x00000000U | |
10961 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10962 | // .. Speed = 0 | |
10963 | // .. ==> 0XF8000740[8:8] = 0x00000000U | |
10964 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10965 | // .. IO_Type = 1 | |
10966 | // .. ==> 0XF8000740[11:9] = 0x00000001U | |
10967 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
10968 | // .. PULLUP = 0 | |
10969 | // .. ==> 0XF8000740[12:12] = 0x00000000U | |
10970 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
10971 | // .. DisableRcvr = 0 | |
10972 | // .. ==> 0XF8000740[13:13] = 0x00000000U | |
10973 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
10974 | // .. | |
10975 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), | |
10976 | // .. TRI_ENABLE = 0 | |
10977 | // .. ==> 0XF8000744[0:0] = 0x00000000U | |
10978 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
10979 | // .. L0_SEL = 1 | |
10980 | // .. ==> 0XF8000744[1:1] = 0x00000001U | |
10981 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
10982 | // .. L1_SEL = 0 | |
10983 | // .. ==> 0XF8000744[2:2] = 0x00000000U | |
10984 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
10985 | // .. L2_SEL = 0 | |
10986 | // .. ==> 0XF8000744[4:3] = 0x00000000U | |
10987 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
10988 | // .. L3_SEL = 0 | |
10989 | // .. ==> 0XF8000744[7:5] = 0x00000000U | |
10990 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
10991 | // .. Speed = 0 | |
10992 | // .. ==> 0XF8000744[8:8] = 0x00000000U | |
10993 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
10994 | // .. IO_Type = 1 | |
10995 | // .. ==> 0XF8000744[11:9] = 0x00000001U | |
10996 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
10997 | // .. PULLUP = 0 | |
10998 | // .. ==> 0XF8000744[12:12] = 0x00000000U | |
10999 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11000 | // .. DisableRcvr = 0 | |
11001 | // .. ==> 0XF8000744[13:13] = 0x00000000U | |
11002 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11003 | // .. | |
11004 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), | |
11005 | // .. TRI_ENABLE = 0 | |
11006 | // .. ==> 0XF8000748[0:0] = 0x00000000U | |
11007 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11008 | // .. L0_SEL = 1 | |
11009 | // .. ==> 0XF8000748[1:1] = 0x00000001U | |
11010 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11011 | // .. L1_SEL = 0 | |
11012 | // .. ==> 0XF8000748[2:2] = 0x00000000U | |
11013 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11014 | // .. L2_SEL = 0 | |
11015 | // .. ==> 0XF8000748[4:3] = 0x00000000U | |
11016 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11017 | // .. L3_SEL = 0 | |
11018 | // .. ==> 0XF8000748[7:5] = 0x00000000U | |
11019 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11020 | // .. Speed = 0 | |
11021 | // .. ==> 0XF8000748[8:8] = 0x00000000U | |
11022 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11023 | // .. IO_Type = 1 | |
11024 | // .. ==> 0XF8000748[11:9] = 0x00000001U | |
11025 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11026 | // .. PULLUP = 0 | |
11027 | // .. ==> 0XF8000748[12:12] = 0x00000000U | |
11028 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11029 | // .. DisableRcvr = 0 | |
11030 | // .. ==> 0XF8000748[13:13] = 0x00000000U | |
11031 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11032 | // .. | |
11033 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), | |
11034 | // .. TRI_ENABLE = 0 | |
11035 | // .. ==> 0XF800074C[0:0] = 0x00000000U | |
11036 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11037 | // .. L0_SEL = 1 | |
11038 | // .. ==> 0XF800074C[1:1] = 0x00000001U | |
11039 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11040 | // .. L1_SEL = 0 | |
11041 | // .. ==> 0XF800074C[2:2] = 0x00000000U | |
11042 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11043 | // .. L2_SEL = 0 | |
11044 | // .. ==> 0XF800074C[4:3] = 0x00000000U | |
11045 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11046 | // .. L3_SEL = 0 | |
11047 | // .. ==> 0XF800074C[7:5] = 0x00000000U | |
11048 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11049 | // .. Speed = 0 | |
11050 | // .. ==> 0XF800074C[8:8] = 0x00000000U | |
11051 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11052 | // .. IO_Type = 1 | |
11053 | // .. ==> 0XF800074C[11:9] = 0x00000001U | |
11054 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11055 | // .. PULLUP = 0 | |
11056 | // .. ==> 0XF800074C[12:12] = 0x00000000U | |
11057 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11058 | // .. DisableRcvr = 0 | |
11059 | // .. ==> 0XF800074C[13:13] = 0x00000000U | |
11060 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11061 | // .. | |
11062 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), | |
11063 | // .. TRI_ENABLE = 0 | |
11064 | // .. ==> 0XF8000750[0:0] = 0x00000000U | |
11065 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11066 | // .. L0_SEL = 1 | |
11067 | // .. ==> 0XF8000750[1:1] = 0x00000001U | |
11068 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11069 | // .. L1_SEL = 0 | |
11070 | // .. ==> 0XF8000750[2:2] = 0x00000000U | |
11071 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11072 | // .. L2_SEL = 0 | |
11073 | // .. ==> 0XF8000750[4:3] = 0x00000000U | |
11074 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11075 | // .. L3_SEL = 0 | |
11076 | // .. ==> 0XF8000750[7:5] = 0x00000000U | |
11077 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11078 | // .. Speed = 0 | |
11079 | // .. ==> 0XF8000750[8:8] = 0x00000000U | |
11080 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11081 | // .. IO_Type = 1 | |
11082 | // .. ==> 0XF8000750[11:9] = 0x00000001U | |
11083 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11084 | // .. PULLUP = 0 | |
11085 | // .. ==> 0XF8000750[12:12] = 0x00000000U | |
11086 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11087 | // .. DisableRcvr = 0 | |
11088 | // .. ==> 0XF8000750[13:13] = 0x00000000U | |
11089 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11090 | // .. | |
11091 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), | |
11092 | // .. TRI_ENABLE = 0 | |
11093 | // .. ==> 0XF8000754[0:0] = 0x00000000U | |
11094 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11095 | // .. L0_SEL = 1 | |
11096 | // .. ==> 0XF8000754[1:1] = 0x00000001U | |
11097 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11098 | // .. L1_SEL = 0 | |
11099 | // .. ==> 0XF8000754[2:2] = 0x00000000U | |
11100 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11101 | // .. L2_SEL = 0 | |
11102 | // .. ==> 0XF8000754[4:3] = 0x00000000U | |
11103 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11104 | // .. L3_SEL = 0 | |
11105 | // .. ==> 0XF8000754[7:5] = 0x00000000U | |
11106 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11107 | // .. Speed = 0 | |
11108 | // .. ==> 0XF8000754[8:8] = 0x00000000U | |
11109 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11110 | // .. IO_Type = 1 | |
11111 | // .. ==> 0XF8000754[11:9] = 0x00000001U | |
11112 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11113 | // .. PULLUP = 0 | |
11114 | // .. ==> 0XF8000754[12:12] = 0x00000000U | |
11115 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11116 | // .. DisableRcvr = 0 | |
11117 | // .. ==> 0XF8000754[13:13] = 0x00000000U | |
11118 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11119 | // .. | |
11120 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), | |
11121 | // .. TRI_ENABLE = 1 | |
11122 | // .. ==> 0XF8000758[0:0] = 0x00000001U | |
11123 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11124 | // .. L0_SEL = 1 | |
11125 | // .. ==> 0XF8000758[1:1] = 0x00000001U | |
11126 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11127 | // .. L1_SEL = 0 | |
11128 | // .. ==> 0XF8000758[2:2] = 0x00000000U | |
11129 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11130 | // .. L2_SEL = 0 | |
11131 | // .. ==> 0XF8000758[4:3] = 0x00000000U | |
11132 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11133 | // .. L3_SEL = 0 | |
11134 | // .. ==> 0XF8000758[7:5] = 0x00000000U | |
11135 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11136 | // .. Speed = 0 | |
11137 | // .. ==> 0XF8000758[8:8] = 0x00000000U | |
11138 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11139 | // .. IO_Type = 1 | |
11140 | // .. ==> 0XF8000758[11:9] = 0x00000001U | |
11141 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11142 | // .. PULLUP = 0 | |
11143 | // .. ==> 0XF8000758[12:12] = 0x00000000U | |
11144 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11145 | // .. DisableRcvr = 0 | |
11146 | // .. ==> 0XF8000758[13:13] = 0x00000000U | |
11147 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11148 | // .. | |
11149 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), | |
11150 | // .. TRI_ENABLE = 1 | |
11151 | // .. ==> 0XF800075C[0:0] = 0x00000001U | |
11152 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11153 | // .. L0_SEL = 1 | |
11154 | // .. ==> 0XF800075C[1:1] = 0x00000001U | |
11155 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11156 | // .. L1_SEL = 0 | |
11157 | // .. ==> 0XF800075C[2:2] = 0x00000000U | |
11158 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11159 | // .. L2_SEL = 0 | |
11160 | // .. ==> 0XF800075C[4:3] = 0x00000000U | |
11161 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11162 | // .. L3_SEL = 0 | |
11163 | // .. ==> 0XF800075C[7:5] = 0x00000000U | |
11164 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11165 | // .. Speed = 0 | |
11166 | // .. ==> 0XF800075C[8:8] = 0x00000000U | |
11167 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11168 | // .. IO_Type = 1 | |
11169 | // .. ==> 0XF800075C[11:9] = 0x00000001U | |
11170 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11171 | // .. PULLUP = 0 | |
11172 | // .. ==> 0XF800075C[12:12] = 0x00000000U | |
11173 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11174 | // .. DisableRcvr = 0 | |
11175 | // .. ==> 0XF800075C[13:13] = 0x00000000U | |
11176 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11177 | // .. | |
11178 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), | |
11179 | // .. TRI_ENABLE = 1 | |
11180 | // .. ==> 0XF8000760[0:0] = 0x00000001U | |
11181 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11182 | // .. L0_SEL = 1 | |
11183 | // .. ==> 0XF8000760[1:1] = 0x00000001U | |
11184 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11185 | // .. L1_SEL = 0 | |
11186 | // .. ==> 0XF8000760[2:2] = 0x00000000U | |
11187 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11188 | // .. L2_SEL = 0 | |
11189 | // .. ==> 0XF8000760[4:3] = 0x00000000U | |
11190 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11191 | // .. L3_SEL = 0 | |
11192 | // .. ==> 0XF8000760[7:5] = 0x00000000U | |
11193 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11194 | // .. Speed = 0 | |
11195 | // .. ==> 0XF8000760[8:8] = 0x00000000U | |
11196 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11197 | // .. IO_Type = 1 | |
11198 | // .. ==> 0XF8000760[11:9] = 0x00000001U | |
11199 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11200 | // .. PULLUP = 0 | |
11201 | // .. ==> 0XF8000760[12:12] = 0x00000000U | |
11202 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11203 | // .. DisableRcvr = 0 | |
11204 | // .. ==> 0XF8000760[13:13] = 0x00000000U | |
11205 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11206 | // .. | |
11207 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), | |
11208 | // .. TRI_ENABLE = 1 | |
11209 | // .. ==> 0XF8000764[0:0] = 0x00000001U | |
11210 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11211 | // .. L0_SEL = 1 | |
11212 | // .. ==> 0XF8000764[1:1] = 0x00000001U | |
11213 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11214 | // .. L1_SEL = 0 | |
11215 | // .. ==> 0XF8000764[2:2] = 0x00000000U | |
11216 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11217 | // .. L2_SEL = 0 | |
11218 | // .. ==> 0XF8000764[4:3] = 0x00000000U | |
11219 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11220 | // .. L3_SEL = 0 | |
11221 | // .. ==> 0XF8000764[7:5] = 0x00000000U | |
11222 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11223 | // .. Speed = 0 | |
11224 | // .. ==> 0XF8000764[8:8] = 0x00000000U | |
11225 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11226 | // .. IO_Type = 1 | |
11227 | // .. ==> 0XF8000764[11:9] = 0x00000001U | |
11228 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11229 | // .. PULLUP = 0 | |
11230 | // .. ==> 0XF8000764[12:12] = 0x00000000U | |
11231 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11232 | // .. DisableRcvr = 0 | |
11233 | // .. ==> 0XF8000764[13:13] = 0x00000000U | |
11234 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11235 | // .. | |
11236 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), | |
11237 | // .. TRI_ENABLE = 1 | |
11238 | // .. ==> 0XF8000768[0:0] = 0x00000001U | |
11239 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11240 | // .. L0_SEL = 1 | |
11241 | // .. ==> 0XF8000768[1:1] = 0x00000001U | |
11242 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11243 | // .. L1_SEL = 0 | |
11244 | // .. ==> 0XF8000768[2:2] = 0x00000000U | |
11245 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11246 | // .. L2_SEL = 0 | |
11247 | // .. ==> 0XF8000768[4:3] = 0x00000000U | |
11248 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11249 | // .. L3_SEL = 0 | |
11250 | // .. ==> 0XF8000768[7:5] = 0x00000000U | |
11251 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11252 | // .. Speed = 0 | |
11253 | // .. ==> 0XF8000768[8:8] = 0x00000000U | |
11254 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11255 | // .. IO_Type = 1 | |
11256 | // .. ==> 0XF8000768[11:9] = 0x00000001U | |
11257 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11258 | // .. PULLUP = 0 | |
11259 | // .. ==> 0XF8000768[12:12] = 0x00000000U | |
11260 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11261 | // .. DisableRcvr = 0 | |
11262 | // .. ==> 0XF8000768[13:13] = 0x00000000U | |
11263 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11264 | // .. | |
11265 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), | |
11266 | // .. TRI_ENABLE = 1 | |
11267 | // .. ==> 0XF800076C[0:0] = 0x00000001U | |
11268 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11269 | // .. L0_SEL = 1 | |
11270 | // .. ==> 0XF800076C[1:1] = 0x00000001U | |
11271 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
11272 | // .. L1_SEL = 0 | |
11273 | // .. ==> 0XF800076C[2:2] = 0x00000000U | |
11274 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11275 | // .. L2_SEL = 0 | |
11276 | // .. ==> 0XF800076C[4:3] = 0x00000000U | |
11277 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11278 | // .. L3_SEL = 0 | |
11279 | // .. ==> 0XF800076C[7:5] = 0x00000000U | |
11280 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11281 | // .. Speed = 0 | |
11282 | // .. ==> 0XF800076C[8:8] = 0x00000000U | |
11283 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11284 | // .. IO_Type = 1 | |
11285 | // .. ==> 0XF800076C[11:9] = 0x00000001U | |
11286 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11287 | // .. PULLUP = 0 | |
11288 | // .. ==> 0XF800076C[12:12] = 0x00000000U | |
11289 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11290 | // .. DisableRcvr = 0 | |
11291 | // .. ==> 0XF800076C[13:13] = 0x00000000U | |
11292 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11293 | // .. | |
11294 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), | |
11295 | // .. TRI_ENABLE = 0 | |
11296 | // .. ==> 0XF8000770[0:0] = 0x00000000U | |
11297 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11298 | // .. L0_SEL = 0 | |
11299 | // .. ==> 0XF8000770[1:1] = 0x00000000U | |
11300 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11301 | // .. L1_SEL = 1 | |
11302 | // .. ==> 0XF8000770[2:2] = 0x00000001U | |
11303 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11304 | // .. L2_SEL = 0 | |
11305 | // .. ==> 0XF8000770[4:3] = 0x00000000U | |
11306 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11307 | // .. L3_SEL = 0 | |
11308 | // .. ==> 0XF8000770[7:5] = 0x00000000U | |
11309 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11310 | // .. Speed = 0 | |
11311 | // .. ==> 0XF8000770[8:8] = 0x00000000U | |
11312 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11313 | // .. IO_Type = 1 | |
11314 | // .. ==> 0XF8000770[11:9] = 0x00000001U | |
11315 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11316 | // .. PULLUP = 0 | |
11317 | // .. ==> 0XF8000770[12:12] = 0x00000000U | |
11318 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11319 | // .. DisableRcvr = 0 | |
11320 | // .. ==> 0XF8000770[13:13] = 0x00000000U | |
11321 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11322 | // .. | |
11323 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), | |
11324 | // .. TRI_ENABLE = 1 | |
11325 | // .. ==> 0XF8000774[0:0] = 0x00000001U | |
11326 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11327 | // .. L0_SEL = 0 | |
11328 | // .. ==> 0XF8000774[1:1] = 0x00000000U | |
11329 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11330 | // .. L1_SEL = 1 | |
11331 | // .. ==> 0XF8000774[2:2] = 0x00000001U | |
11332 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11333 | // .. L2_SEL = 0 | |
11334 | // .. ==> 0XF8000774[4:3] = 0x00000000U | |
11335 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11336 | // .. L3_SEL = 0 | |
11337 | // .. ==> 0XF8000774[7:5] = 0x00000000U | |
11338 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11339 | // .. Speed = 0 | |
11340 | // .. ==> 0XF8000774[8:8] = 0x00000000U | |
11341 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11342 | // .. IO_Type = 1 | |
11343 | // .. ==> 0XF8000774[11:9] = 0x00000001U | |
11344 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11345 | // .. PULLUP = 0 | |
11346 | // .. ==> 0XF8000774[12:12] = 0x00000000U | |
11347 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11348 | // .. DisableRcvr = 0 | |
11349 | // .. ==> 0XF8000774[13:13] = 0x00000000U | |
11350 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11351 | // .. | |
11352 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), | |
11353 | // .. TRI_ENABLE = 0 | |
11354 | // .. ==> 0XF8000778[0:0] = 0x00000000U | |
11355 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11356 | // .. L0_SEL = 0 | |
11357 | // .. ==> 0XF8000778[1:1] = 0x00000000U | |
11358 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11359 | // .. L1_SEL = 1 | |
11360 | // .. ==> 0XF8000778[2:2] = 0x00000001U | |
11361 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11362 | // .. L2_SEL = 0 | |
11363 | // .. ==> 0XF8000778[4:3] = 0x00000000U | |
11364 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11365 | // .. L3_SEL = 0 | |
11366 | // .. ==> 0XF8000778[7:5] = 0x00000000U | |
11367 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11368 | // .. Speed = 0 | |
11369 | // .. ==> 0XF8000778[8:8] = 0x00000000U | |
11370 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11371 | // .. IO_Type = 1 | |
11372 | // .. ==> 0XF8000778[11:9] = 0x00000001U | |
11373 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11374 | // .. PULLUP = 0 | |
11375 | // .. ==> 0XF8000778[12:12] = 0x00000000U | |
11376 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11377 | // .. DisableRcvr = 0 | |
11378 | // .. ==> 0XF8000778[13:13] = 0x00000000U | |
11379 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11380 | // .. | |
11381 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), | |
11382 | // .. TRI_ENABLE = 1 | |
11383 | // .. ==> 0XF800077C[0:0] = 0x00000001U | |
11384 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11385 | // .. L0_SEL = 0 | |
11386 | // .. ==> 0XF800077C[1:1] = 0x00000000U | |
11387 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11388 | // .. L1_SEL = 1 | |
11389 | // .. ==> 0XF800077C[2:2] = 0x00000001U | |
11390 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11391 | // .. L2_SEL = 0 | |
11392 | // .. ==> 0XF800077C[4:3] = 0x00000000U | |
11393 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11394 | // .. L3_SEL = 0 | |
11395 | // .. ==> 0XF800077C[7:5] = 0x00000000U | |
11396 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11397 | // .. Speed = 0 | |
11398 | // .. ==> 0XF800077C[8:8] = 0x00000000U | |
11399 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11400 | // .. IO_Type = 1 | |
11401 | // .. ==> 0XF800077C[11:9] = 0x00000001U | |
11402 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11403 | // .. PULLUP = 0 | |
11404 | // .. ==> 0XF800077C[12:12] = 0x00000000U | |
11405 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11406 | // .. DisableRcvr = 0 | |
11407 | // .. ==> 0XF800077C[13:13] = 0x00000000U | |
11408 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11409 | // .. | |
11410 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), | |
11411 | // .. TRI_ENABLE = 0 | |
11412 | // .. ==> 0XF8000780[0:0] = 0x00000000U | |
11413 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11414 | // .. L0_SEL = 0 | |
11415 | // .. ==> 0XF8000780[1:1] = 0x00000000U | |
11416 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11417 | // .. L1_SEL = 1 | |
11418 | // .. ==> 0XF8000780[2:2] = 0x00000001U | |
11419 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11420 | // .. L2_SEL = 0 | |
11421 | // .. ==> 0XF8000780[4:3] = 0x00000000U | |
11422 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11423 | // .. L3_SEL = 0 | |
11424 | // .. ==> 0XF8000780[7:5] = 0x00000000U | |
11425 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11426 | // .. Speed = 0 | |
11427 | // .. ==> 0XF8000780[8:8] = 0x00000000U | |
11428 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11429 | // .. IO_Type = 1 | |
11430 | // .. ==> 0XF8000780[11:9] = 0x00000001U | |
11431 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11432 | // .. PULLUP = 0 | |
11433 | // .. ==> 0XF8000780[12:12] = 0x00000000U | |
11434 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11435 | // .. DisableRcvr = 0 | |
11436 | // .. ==> 0XF8000780[13:13] = 0x00000000U | |
11437 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11438 | // .. | |
11439 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), | |
11440 | // .. TRI_ENABLE = 0 | |
11441 | // .. ==> 0XF8000784[0:0] = 0x00000000U | |
11442 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11443 | // .. L0_SEL = 0 | |
11444 | // .. ==> 0XF8000784[1:1] = 0x00000000U | |
11445 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11446 | // .. L1_SEL = 1 | |
11447 | // .. ==> 0XF8000784[2:2] = 0x00000001U | |
11448 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11449 | // .. L2_SEL = 0 | |
11450 | // .. ==> 0XF8000784[4:3] = 0x00000000U | |
11451 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11452 | // .. L3_SEL = 0 | |
11453 | // .. ==> 0XF8000784[7:5] = 0x00000000U | |
11454 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11455 | // .. Speed = 0 | |
11456 | // .. ==> 0XF8000784[8:8] = 0x00000000U | |
11457 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11458 | // .. IO_Type = 1 | |
11459 | // .. ==> 0XF8000784[11:9] = 0x00000001U | |
11460 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11461 | // .. PULLUP = 0 | |
11462 | // .. ==> 0XF8000784[12:12] = 0x00000000U | |
11463 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11464 | // .. DisableRcvr = 0 | |
11465 | // .. ==> 0XF8000784[13:13] = 0x00000000U | |
11466 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11467 | // .. | |
11468 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), | |
11469 | // .. TRI_ENABLE = 0 | |
11470 | // .. ==> 0XF8000788[0:0] = 0x00000000U | |
11471 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11472 | // .. L0_SEL = 0 | |
11473 | // .. ==> 0XF8000788[1:1] = 0x00000000U | |
11474 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11475 | // .. L1_SEL = 1 | |
11476 | // .. ==> 0XF8000788[2:2] = 0x00000001U | |
11477 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11478 | // .. L2_SEL = 0 | |
11479 | // .. ==> 0XF8000788[4:3] = 0x00000000U | |
11480 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11481 | // .. L3_SEL = 0 | |
11482 | // .. ==> 0XF8000788[7:5] = 0x00000000U | |
11483 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11484 | // .. Speed = 0 | |
11485 | // .. ==> 0XF8000788[8:8] = 0x00000000U | |
11486 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11487 | // .. IO_Type = 1 | |
11488 | // .. ==> 0XF8000788[11:9] = 0x00000001U | |
11489 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11490 | // .. PULLUP = 0 | |
11491 | // .. ==> 0XF8000788[12:12] = 0x00000000U | |
11492 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11493 | // .. DisableRcvr = 0 | |
11494 | // .. ==> 0XF8000788[13:13] = 0x00000000U | |
11495 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11496 | // .. | |
11497 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), | |
11498 | // .. TRI_ENABLE = 0 | |
11499 | // .. ==> 0XF800078C[0:0] = 0x00000000U | |
11500 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11501 | // .. L0_SEL = 0 | |
11502 | // .. ==> 0XF800078C[1:1] = 0x00000000U | |
11503 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11504 | // .. L1_SEL = 1 | |
11505 | // .. ==> 0XF800078C[2:2] = 0x00000001U | |
11506 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11507 | // .. L2_SEL = 0 | |
11508 | // .. ==> 0XF800078C[4:3] = 0x00000000U | |
11509 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11510 | // .. L3_SEL = 0 | |
11511 | // .. ==> 0XF800078C[7:5] = 0x00000000U | |
11512 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11513 | // .. Speed = 0 | |
11514 | // .. ==> 0XF800078C[8:8] = 0x00000000U | |
11515 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11516 | // .. IO_Type = 1 | |
11517 | // .. ==> 0XF800078C[11:9] = 0x00000001U | |
11518 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11519 | // .. PULLUP = 0 | |
11520 | // .. ==> 0XF800078C[12:12] = 0x00000000U | |
11521 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11522 | // .. DisableRcvr = 0 | |
11523 | // .. ==> 0XF800078C[13:13] = 0x00000000U | |
11524 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11525 | // .. | |
11526 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), | |
11527 | // .. TRI_ENABLE = 1 | |
11528 | // .. ==> 0XF8000790[0:0] = 0x00000001U | |
11529 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11530 | // .. L0_SEL = 0 | |
11531 | // .. ==> 0XF8000790[1:1] = 0x00000000U | |
11532 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11533 | // .. L1_SEL = 1 | |
11534 | // .. ==> 0XF8000790[2:2] = 0x00000001U | |
11535 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11536 | // .. L2_SEL = 0 | |
11537 | // .. ==> 0XF8000790[4:3] = 0x00000000U | |
11538 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11539 | // .. L3_SEL = 0 | |
11540 | // .. ==> 0XF8000790[7:5] = 0x00000000U | |
11541 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11542 | // .. Speed = 0 | |
11543 | // .. ==> 0XF8000790[8:8] = 0x00000000U | |
11544 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11545 | // .. IO_Type = 1 | |
11546 | // .. ==> 0XF8000790[11:9] = 0x00000001U | |
11547 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11548 | // .. PULLUP = 0 | |
11549 | // .. ==> 0XF8000790[12:12] = 0x00000000U | |
11550 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11551 | // .. DisableRcvr = 0 | |
11552 | // .. ==> 0XF8000790[13:13] = 0x00000000U | |
11553 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11554 | // .. | |
11555 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), | |
11556 | // .. TRI_ENABLE = 0 | |
11557 | // .. ==> 0XF8000794[0:0] = 0x00000000U | |
11558 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11559 | // .. L0_SEL = 0 | |
11560 | // .. ==> 0XF8000794[1:1] = 0x00000000U | |
11561 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11562 | // .. L1_SEL = 1 | |
11563 | // .. ==> 0XF8000794[2:2] = 0x00000001U | |
11564 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11565 | // .. L2_SEL = 0 | |
11566 | // .. ==> 0XF8000794[4:3] = 0x00000000U | |
11567 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11568 | // .. L3_SEL = 0 | |
11569 | // .. ==> 0XF8000794[7:5] = 0x00000000U | |
11570 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11571 | // .. Speed = 0 | |
11572 | // .. ==> 0XF8000794[8:8] = 0x00000000U | |
11573 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11574 | // .. IO_Type = 1 | |
11575 | // .. ==> 0XF8000794[11:9] = 0x00000001U | |
11576 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11577 | // .. PULLUP = 0 | |
11578 | // .. ==> 0XF8000794[12:12] = 0x00000000U | |
11579 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11580 | // .. DisableRcvr = 0 | |
11581 | // .. ==> 0XF8000794[13:13] = 0x00000000U | |
11582 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11583 | // .. | |
11584 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), | |
11585 | // .. TRI_ENABLE = 0 | |
11586 | // .. ==> 0XF8000798[0:0] = 0x00000000U | |
11587 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11588 | // .. L0_SEL = 0 | |
11589 | // .. ==> 0XF8000798[1:1] = 0x00000000U | |
11590 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11591 | // .. L1_SEL = 1 | |
11592 | // .. ==> 0XF8000798[2:2] = 0x00000001U | |
11593 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11594 | // .. L2_SEL = 0 | |
11595 | // .. ==> 0XF8000798[4:3] = 0x00000000U | |
11596 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11597 | // .. L3_SEL = 0 | |
11598 | // .. ==> 0XF8000798[7:5] = 0x00000000U | |
11599 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11600 | // .. Speed = 0 | |
11601 | // .. ==> 0XF8000798[8:8] = 0x00000000U | |
11602 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11603 | // .. IO_Type = 1 | |
11604 | // .. ==> 0XF8000798[11:9] = 0x00000001U | |
11605 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11606 | // .. PULLUP = 0 | |
11607 | // .. ==> 0XF8000798[12:12] = 0x00000000U | |
11608 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11609 | // .. DisableRcvr = 0 | |
11610 | // .. ==> 0XF8000798[13:13] = 0x00000000U | |
11611 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11612 | // .. | |
11613 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), | |
11614 | // .. TRI_ENABLE = 0 | |
11615 | // .. ==> 0XF800079C[0:0] = 0x00000000U | |
11616 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11617 | // .. L0_SEL = 0 | |
11618 | // .. ==> 0XF800079C[1:1] = 0x00000000U | |
11619 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11620 | // .. L1_SEL = 1 | |
11621 | // .. ==> 0XF800079C[2:2] = 0x00000001U | |
11622 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
11623 | // .. L2_SEL = 0 | |
11624 | // .. ==> 0XF800079C[4:3] = 0x00000000U | |
11625 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11626 | // .. L3_SEL = 0 | |
11627 | // .. ==> 0XF800079C[7:5] = 0x00000000U | |
11628 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11629 | // .. Speed = 0 | |
11630 | // .. ==> 0XF800079C[8:8] = 0x00000000U | |
11631 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11632 | // .. IO_Type = 1 | |
11633 | // .. ==> 0XF800079C[11:9] = 0x00000001U | |
11634 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11635 | // .. PULLUP = 0 | |
11636 | // .. ==> 0XF800079C[12:12] = 0x00000000U | |
11637 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11638 | // .. DisableRcvr = 0 | |
11639 | // .. ==> 0XF800079C[13:13] = 0x00000000U | |
11640 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11641 | // .. | |
11642 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), | |
11643 | // .. TRI_ENABLE = 0 | |
11644 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | |
11645 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11646 | // .. L0_SEL = 0 | |
11647 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | |
11648 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11649 | // .. L1_SEL = 0 | |
11650 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | |
11651 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11652 | // .. L2_SEL = 0 | |
11653 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | |
11654 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11655 | // .. L3_SEL = 4 | |
11656 | // .. ==> 0XF80007A0[7:5] = 0x00000004U | |
11657 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11658 | // .. Speed = 0 | |
11659 | // .. ==> 0XF80007A0[8:8] = 0x00000000U | |
11660 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11661 | // .. IO_Type = 1 | |
11662 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | |
11663 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11664 | // .. PULLUP = 0 | |
11665 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | |
11666 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11667 | // .. DisableRcvr = 0 | |
11668 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | |
11669 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11670 | // .. | |
11671 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), | |
11672 | // .. TRI_ENABLE = 0 | |
11673 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | |
11674 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11675 | // .. L0_SEL = 0 | |
11676 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | |
11677 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11678 | // .. L1_SEL = 0 | |
11679 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | |
11680 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11681 | // .. L2_SEL = 0 | |
11682 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | |
11683 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11684 | // .. L3_SEL = 4 | |
11685 | // .. ==> 0XF80007A4[7:5] = 0x00000004U | |
11686 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11687 | // .. Speed = 0 | |
11688 | // .. ==> 0XF80007A4[8:8] = 0x00000000U | |
11689 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11690 | // .. IO_Type = 1 | |
11691 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | |
11692 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11693 | // .. PULLUP = 0 | |
11694 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | |
11695 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11696 | // .. DisableRcvr = 0 | |
11697 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | |
11698 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11699 | // .. | |
11700 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), | |
11701 | // .. TRI_ENABLE = 0 | |
11702 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | |
11703 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11704 | // .. L0_SEL = 0 | |
11705 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | |
11706 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11707 | // .. L1_SEL = 0 | |
11708 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | |
11709 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11710 | // .. L2_SEL = 0 | |
11711 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | |
11712 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11713 | // .. L3_SEL = 4 | |
11714 | // .. ==> 0XF80007A8[7:5] = 0x00000004U | |
11715 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11716 | // .. Speed = 0 | |
11717 | // .. ==> 0XF80007A8[8:8] = 0x00000000U | |
11718 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11719 | // .. IO_Type = 1 | |
11720 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | |
11721 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11722 | // .. PULLUP = 0 | |
11723 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | |
11724 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11725 | // .. DisableRcvr = 0 | |
11726 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | |
11727 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11728 | // .. | |
11729 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), | |
11730 | // .. TRI_ENABLE = 0 | |
11731 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | |
11732 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11733 | // .. L0_SEL = 0 | |
11734 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | |
11735 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11736 | // .. L1_SEL = 0 | |
11737 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | |
11738 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11739 | // .. L2_SEL = 0 | |
11740 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | |
11741 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11742 | // .. L3_SEL = 4 | |
11743 | // .. ==> 0XF80007AC[7:5] = 0x00000004U | |
11744 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11745 | // .. Speed = 0 | |
11746 | // .. ==> 0XF80007AC[8:8] = 0x00000000U | |
11747 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11748 | // .. IO_Type = 1 | |
11749 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | |
11750 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11751 | // .. PULLUP = 0 | |
11752 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | |
11753 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11754 | // .. DisableRcvr = 0 | |
11755 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | |
11756 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11757 | // .. | |
11758 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), | |
11759 | // .. TRI_ENABLE = 0 | |
11760 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | |
11761 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11762 | // .. L0_SEL = 0 | |
11763 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | |
11764 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11765 | // .. L1_SEL = 0 | |
11766 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | |
11767 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11768 | // .. L2_SEL = 0 | |
11769 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | |
11770 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11771 | // .. L3_SEL = 4 | |
11772 | // .. ==> 0XF80007B0[7:5] = 0x00000004U | |
11773 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11774 | // .. Speed = 0 | |
11775 | // .. ==> 0XF80007B0[8:8] = 0x00000000U | |
11776 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11777 | // .. IO_Type = 1 | |
11778 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | |
11779 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11780 | // .. PULLUP = 0 | |
11781 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | |
11782 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11783 | // .. DisableRcvr = 0 | |
11784 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | |
11785 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11786 | // .. | |
11787 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), | |
11788 | // .. TRI_ENABLE = 0 | |
11789 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | |
11790 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11791 | // .. L0_SEL = 0 | |
11792 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | |
11793 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11794 | // .. L1_SEL = 0 | |
11795 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | |
11796 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11797 | // .. L2_SEL = 0 | |
11798 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | |
11799 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11800 | // .. L3_SEL = 4 | |
11801 | // .. ==> 0XF80007B4[7:5] = 0x00000004U | |
11802 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11803 | // .. Speed = 0 | |
11804 | // .. ==> 0XF80007B4[8:8] = 0x00000000U | |
11805 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11806 | // .. IO_Type = 1 | |
11807 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | |
11808 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11809 | // .. PULLUP = 0 | |
11810 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | |
11811 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11812 | // .. DisableRcvr = 0 | |
11813 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | |
11814 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11815 | // .. | |
11816 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), | |
11817 | // .. TRI_ENABLE = 1 | |
11818 | // .. ==> 0XF80007B8[0:0] = 0x00000001U | |
11819 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11820 | // .. Speed = 0 | |
11821 | // .. ==> 0XF80007B8[8:8] = 0x00000000U | |
11822 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11823 | // .. IO_Type = 1 | |
11824 | // .. ==> 0XF80007B8[11:9] = 0x00000001U | |
11825 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11826 | // .. PULLUP = 0 | |
11827 | // .. ==> 0XF80007B8[12:12] = 0x00000000U | |
11828 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11829 | // .. DisableRcvr = 0 | |
11830 | // .. ==> 0XF80007B8[13:13] = 0x00000000U | |
11831 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11832 | // .. | |
11833 | EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), | |
11834 | // .. TRI_ENABLE = 0 | |
11835 | // .. ==> 0XF80007BC[0:0] = 0x00000000U | |
11836 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11837 | // .. L0_SEL = 0 | |
11838 | // .. ==> 0XF80007BC[1:1] = 0x00000000U | |
11839 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11840 | // .. L1_SEL = 0 | |
11841 | // .. ==> 0XF80007BC[2:2] = 0x00000000U | |
11842 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11843 | // .. L2_SEL = 0 | |
11844 | // .. ==> 0XF80007BC[4:3] = 0x00000000U | |
11845 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11846 | // .. L3_SEL = 0 | |
11847 | // .. ==> 0XF80007BC[7:5] = 0x00000000U | |
11848 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11849 | // .. Speed = 0 | |
11850 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | |
11851 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11852 | // .. IO_Type = 1 | |
11853 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | |
11854 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11855 | // .. PULLUP = 0 | |
11856 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | |
11857 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11858 | // .. DisableRcvr = 0 | |
11859 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | |
11860 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11861 | // .. | |
11862 | EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), | |
11863 | // .. TRI_ENABLE = 0 | |
11864 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | |
11865 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11866 | // .. L0_SEL = 0 | |
11867 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | |
11868 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11869 | // .. L1_SEL = 0 | |
11870 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | |
11871 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11872 | // .. L2_SEL = 0 | |
11873 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | |
11874 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11875 | // .. L3_SEL = 7 | |
11876 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | |
11877 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | |
11878 | // .. Speed = 0 | |
11879 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | |
11880 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11881 | // .. IO_Type = 1 | |
11882 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | |
11883 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11884 | // .. PULLUP = 0 | |
11885 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | |
11886 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11887 | // .. DisableRcvr = 0 | |
11888 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | |
11889 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11890 | // .. | |
11891 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | |
11892 | // .. TRI_ENABLE = 1 | |
11893 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | |
11894 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11895 | // .. L0_SEL = 0 | |
11896 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | |
11897 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11898 | // .. L1_SEL = 0 | |
11899 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | |
11900 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11901 | // .. L2_SEL = 0 | |
11902 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | |
11903 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11904 | // .. L3_SEL = 7 | |
11905 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | |
11906 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | |
11907 | // .. Speed = 0 | |
11908 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | |
11909 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11910 | // .. IO_Type = 1 | |
11911 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | |
11912 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11913 | // .. PULLUP = 0 | |
11914 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | |
11915 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11916 | // .. DisableRcvr = 0 | |
11917 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | |
11918 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11919 | // .. | |
11920 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | |
11921 | // .. TRI_ENABLE = 1 | |
11922 | // .. ==> 0XF80007C8[0:0] = 0x00000001U | |
11923 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
11924 | // .. Speed = 0 | |
11925 | // .. ==> 0XF80007C8[8:8] = 0x00000000U | |
11926 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11927 | // .. IO_Type = 1 | |
11928 | // .. ==> 0XF80007C8[11:9] = 0x00000001U | |
11929 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11930 | // .. PULLUP = 0 | |
11931 | // .. ==> 0XF80007C8[12:12] = 0x00000000U | |
11932 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11933 | // .. DisableRcvr = 0 | |
11934 | // .. ==> 0XF80007C8[13:13] = 0x00000000U | |
11935 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11936 | // .. | |
11937 | EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), | |
11938 | // .. TRI_ENABLE = 0 | |
11939 | // .. ==> 0XF80007CC[0:0] = 0x00000000U | |
11940 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11941 | // .. L0_SEL = 0 | |
11942 | // .. ==> 0XF80007CC[1:1] = 0x00000000U | |
11943 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11944 | // .. L1_SEL = 0 | |
11945 | // .. ==> 0XF80007CC[2:2] = 0x00000000U | |
11946 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11947 | // .. L2_SEL = 0 | |
11948 | // .. ==> 0XF80007CC[4:3] = 0x00000000U | |
11949 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11950 | // .. L3_SEL = 0 | |
11951 | // .. ==> 0XF80007CC[7:5] = 0x00000000U | |
11952 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | |
11953 | // .. Speed = 0 | |
11954 | // .. ==> 0XF80007CC[8:8] = 0x00000000U | |
11955 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11956 | // .. IO_Type = 1 | |
11957 | // .. ==> 0XF80007CC[11:9] = 0x00000001U | |
11958 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11959 | // .. PULLUP = 0 | |
11960 | // .. ==> 0XF80007CC[12:12] = 0x00000000U | |
11961 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11962 | // .. DisableRcvr = 0 | |
11963 | // .. ==> 0XF80007CC[13:13] = 0x00000000U | |
11964 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11965 | // .. | |
11966 | EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), | |
11967 | // .. TRI_ENABLE = 0 | |
11968 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | |
11969 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11970 | // .. L0_SEL = 0 | |
11971 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | |
11972 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
11973 | // .. L1_SEL = 0 | |
11974 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | |
11975 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
11976 | // .. L2_SEL = 0 | |
11977 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | |
11978 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
11979 | // .. L3_SEL = 4 | |
11980 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | |
11981 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
11982 | // .. Speed = 0 | |
11983 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | |
11984 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
11985 | // .. IO_Type = 1 | |
11986 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | |
11987 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
11988 | // .. PULLUP = 0 | |
11989 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | |
11990 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
11991 | // .. DisableRcvr = 0 | |
11992 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | |
11993 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
11994 | // .. | |
11995 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | |
11996 | // .. TRI_ENABLE = 0 | |
11997 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | |
11998 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
11999 | // .. L0_SEL = 0 | |
12000 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | |
12001 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
12002 | // .. L1_SEL = 0 | |
12003 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | |
12004 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
12005 | // .. L2_SEL = 0 | |
12006 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | |
12007 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | |
12008 | // .. L3_SEL = 4 | |
12009 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | |
12010 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | |
12011 | // .. Speed = 0 | |
12012 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | |
12013 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
12014 | // .. IO_Type = 1 | |
12015 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | |
12016 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | |
12017 | // .. PULLUP = 0 | |
12018 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | |
12019 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
12020 | // .. DisableRcvr = 0 | |
12021 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | |
12022 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
12023 | // .. | |
12024 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | |
12025 | // .. SDIO0_WP_SEL = 50 | |
12026 | // .. ==> 0XF8000830[5:0] = 0x00000032U | |
12027 | // .. ==> MASK : 0x0000003FU VAL : 0x00000032U | |
12028 | // .. SDIO0_CD_SEL = 46 | |
12029 | // .. ==> 0XF8000830[21:16] = 0x0000002EU | |
12030 | // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U | |
12031 | // .. | |
12032 | EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), | |
12033 | // .. FINISH: MIO PROGRAMMING | |
12034 | // .. START: LOCK IT BACK | |
12035 | // .. LOCK_KEY = 0X767B | |
12036 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
12037 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
12038 | // .. | |
12039 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
12040 | // .. FINISH: LOCK IT BACK | |
12041 | // FINISH: top | |
12042 | // | |
12043 | EMIT_EXIT(), | |
12044 | ||
12045 | // | |
12046 | }; | |
12047 | ||
12048 | unsigned long ps7_peripherals_init_data_1_0[] = { | |
12049 | // START: top | |
12050 | // .. START: SLCR SETTINGS | |
12051 | // .. UNLOCK_KEY = 0XDF0D | |
12052 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
12053 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
12054 | // .. | |
12055 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
12056 | // .. FINISH: SLCR SETTINGS | |
12057 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | |
12058 | // .. IBUF_DISABLE_MODE = 0x1 | |
12059 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | |
12060 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
12061 | // .. TERM_DISABLE_MODE = 0x1 | |
12062 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | |
12063 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
12064 | // .. | |
12065 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | |
12066 | // .. IBUF_DISABLE_MODE = 0x1 | |
12067 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | |
12068 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
12069 | // .. TERM_DISABLE_MODE = 0x1 | |
12070 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | |
12071 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
12072 | // .. | |
12073 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | |
12074 | // .. IBUF_DISABLE_MODE = 0x1 | |
12075 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | |
12076 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
12077 | // .. TERM_DISABLE_MODE = 0x1 | |
12078 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | |
12079 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
12080 | // .. | |
12081 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | |
12082 | // .. IBUF_DISABLE_MODE = 0x1 | |
12083 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | |
12084 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | |
12085 | // .. TERM_DISABLE_MODE = 0x1 | |
12086 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | |
12087 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | |
12088 | // .. | |
12089 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | |
12090 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | |
12091 | // .. START: LOCK IT BACK | |
12092 | // .. LOCK_KEY = 0X767B | |
12093 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
12094 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
12095 | // .. | |
12096 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
12097 | // .. FINISH: LOCK IT BACK | |
12098 | // .. START: SRAM/NOR SET OPMODE | |
12099 | // .. FINISH: SRAM/NOR SET OPMODE | |
12100 | // .. START: UART REGISTERS | |
12101 | // .. BDIV = 0x6 | |
12102 | // .. ==> 0XE0001034[7:0] = 0x00000006U | |
12103 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | |
12104 | // .. | |
12105 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | |
12106 | // .. CD = 0x3e | |
12107 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | |
12108 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | |
12109 | // .. | |
12110 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | |
12111 | // .. STPBRK = 0x0 | |
12112 | // .. ==> 0XE0001000[8:8] = 0x00000000U | |
12113 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
12114 | // .. STTBRK = 0x0 | |
12115 | // .. ==> 0XE0001000[7:7] = 0x00000000U | |
12116 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | |
12117 | // .. RSTTO = 0x0 | |
12118 | // .. ==> 0XE0001000[6:6] = 0x00000000U | |
12119 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | |
12120 | // .. TXDIS = 0x0 | |
12121 | // .. ==> 0XE0001000[5:5] = 0x00000000U | |
12122 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | |
12123 | // .. TXEN = 0x1 | |
12124 | // .. ==> 0XE0001000[4:4] = 0x00000001U | |
12125 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | |
12126 | // .. RXDIS = 0x0 | |
12127 | // .. ==> 0XE0001000[3:3] = 0x00000000U | |
12128 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
12129 | // .. RXEN = 0x1 | |
12130 | // .. ==> 0XE0001000[2:2] = 0x00000001U | |
12131 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | |
12132 | // .. TXRES = 0x1 | |
12133 | // .. ==> 0XE0001000[1:1] = 0x00000001U | |
12134 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | |
12135 | // .. RXRES = 0x1 | |
12136 | // .. ==> 0XE0001000[0:0] = 0x00000001U | |
12137 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | |
12138 | // .. | |
12139 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | |
12140 | // .. IRMODE = 0x0 | |
12141 | // .. ==> 0XE0001004[11:11] = 0x00000000U | |
12142 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
12143 | // .. UCLKEN = 0x0 | |
12144 | // .. ==> 0XE0001004[10:10] = 0x00000000U | |
12145 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
12146 | // .. CHMODE = 0x0 | |
12147 | // .. ==> 0XE0001004[9:8] = 0x00000000U | |
12148 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | |
12149 | // .. NBSTOP = 0x0 | |
12150 | // .. ==> 0XE0001004[7:6] = 0x00000000U | |
12151 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | |
12152 | // .. PAR = 0x4 | |
12153 | // .. ==> 0XE0001004[5:3] = 0x00000004U | |
12154 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | |
12155 | // .. CHRL = 0x0 | |
12156 | // .. ==> 0XE0001004[2:1] = 0x00000000U | |
12157 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | |
12158 | // .. CLKS = 0x0 | |
12159 | // .. ==> 0XE0001004[0:0] = 0x00000000U | |
12160 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
12161 | // .. | |
12162 | EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), | |
12163 | // .. FINISH: UART REGISTERS | |
12164 | // .. START: QSPI REGISTERS | |
12165 | // .. Holdb_dr = 1 | |
12166 | // .. ==> 0XE000D000[19:19] = 0x00000001U | |
12167 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | |
12168 | // .. | |
12169 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | |
12170 | // .. FINISH: QSPI REGISTERS | |
12171 | // .. START: PL POWER ON RESET REGISTERS | |
12172 | // .. PCFG_POR_CNT_4K = 0 | |
12173 | // .. ==> 0XF8007000[29:29] = 0x00000000U | |
12174 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | |
12175 | // .. | |
12176 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | |
12177 | // .. FINISH: PL POWER ON RESET REGISTERS | |
12178 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | |
12179 | // .. .. START: NAND SET CYCLE | |
12180 | // .. .. FINISH: NAND SET CYCLE | |
12181 | // .. .. START: OPMODE | |
12182 | // .. .. FINISH: OPMODE | |
12183 | // .. .. START: DIRECT COMMAND | |
12184 | // .. .. FINISH: DIRECT COMMAND | |
12185 | // .. .. START: SRAM/NOR CS0 SET CYCLE | |
12186 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | |
12187 | // .. .. START: DIRECT COMMAND | |
12188 | // .. .. FINISH: DIRECT COMMAND | |
12189 | // .. .. START: NOR CS0 BASE ADDRESS | |
12190 | // .. .. FINISH: NOR CS0 BASE ADDRESS | |
12191 | // .. .. START: SRAM/NOR CS1 SET CYCLE | |
12192 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | |
12193 | // .. .. START: DIRECT COMMAND | |
12194 | // .. .. FINISH: DIRECT COMMAND | |
12195 | // .. .. START: NOR CS1 BASE ADDRESS | |
12196 | // .. .. FINISH: NOR CS1 BASE ADDRESS | |
12197 | // .. .. START: USB RESET | |
12198 | // .. .. .. START: USB0 RESET | |
12199 | // .. .. .. .. START: DIR MODE BANK 0 | |
12200 | // .. .. .. .. DIRECTION_0 = 0x80 | |
12201 | // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U | |
12202 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | |
12203 | // .. .. .. .. | |
12204 | EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), | |
12205 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
12206 | // .. .. .. .. START: DIR MODE BANK 1 | |
12207 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
12208 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12209 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
12210 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
12211 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
12212 | // .. .. .. .. DATA_0_LSW = 0x80 | |
12213 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | |
12214 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | |
12215 | // .. .. .. .. | |
12216 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | |
12217 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12218 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12219 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12220 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12221 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12222 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12223 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12224 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
12225 | // .. .. .. .. OP_ENABLE_0 = 0x80 | |
12226 | // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U | |
12227 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | |
12228 | // .. .. .. .. | |
12229 | EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), | |
12230 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
12231 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
12232 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
12233 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
12234 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
12235 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
12236 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
12237 | // .. .. .. .. DATA_0_LSW = 0x0 | |
12238 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U | |
12239 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U | |
12240 | // .. .. .. .. | |
12241 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), | |
12242 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
12243 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
12244 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
12245 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
12246 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
12247 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
12248 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
12249 | // .. .. .. .. START: ADD 1 MS DELAY | |
12250 | // .. .. .. .. | |
12251 | EMIT_MASKDELAY(0XF8F00200, 1), | |
12252 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
12253 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12254 | // .. .. .. .. MASK_0_LSW = 0xff7f | |
12255 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | |
12256 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | |
12257 | // .. .. .. .. DATA_0_LSW = 0x80 | |
12258 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | |
12259 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | |
12260 | // .. .. .. .. | |
12261 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | |
12262 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12263 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12264 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12265 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12266 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12267 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12268 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12269 | // .. .. .. FINISH: USB0 RESET | |
12270 | // .. .. .. START: USB1 RESET | |
12271 | // .. .. .. .. START: DIR MODE BANK 0 | |
12272 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
12273 | // .. .. .. .. START: DIR MODE BANK 1 | |
12274 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
12275 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12276 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12277 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12278 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12279 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12280 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12281 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12282 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12283 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
12284 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
12285 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
12286 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
12287 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
12288 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
12289 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
12290 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
12291 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
12292 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
12293 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
12294 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
12295 | // .. .. .. .. START: ADD 1 MS DELAY | |
12296 | // .. .. .. .. | |
12297 | EMIT_MASKDELAY(0XF8F00200, 1), | |
12298 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
12299 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12300 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12301 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12302 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12303 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12304 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12305 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12306 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12307 | // .. .. .. FINISH: USB1 RESET | |
12308 | // .. .. FINISH: USB RESET | |
12309 | // .. .. START: ENET RESET | |
12310 | // .. .. .. START: ENET0 RESET | |
12311 | // .. .. .. .. START: DIR MODE BANK 0 | |
12312 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
12313 | // .. .. .. .. START: DIR MODE BANK 1 | |
12314 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
12315 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12316 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12317 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12318 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12319 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12320 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12321 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12322 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12323 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
12324 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
12325 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
12326 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
12327 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
12328 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
12329 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
12330 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
12331 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
12332 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
12333 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
12334 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
12335 | // .. .. .. .. START: ADD 1 MS DELAY | |
12336 | // .. .. .. .. | |
12337 | EMIT_MASKDELAY(0XF8F00200, 1), | |
12338 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
12339 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12340 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12341 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12342 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12343 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12344 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12345 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12346 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12347 | // .. .. .. FINISH: ENET0 RESET | |
12348 | // .. .. .. START: ENET1 RESET | |
12349 | // .. .. .. .. START: DIR MODE BANK 0 | |
12350 | // .. .. .. .. FINISH: DIR MODE BANK 0 | |
12351 | // .. .. .. .. START: DIR MODE BANK 1 | |
12352 | // .. .. .. .. FINISH: DIR MODE BANK 1 | |
12353 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12354 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12355 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12356 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12357 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12358 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12359 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12360 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12361 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | |
12362 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
12363 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | |
12364 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | |
12365 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
12366 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
12367 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
12368 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
12369 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
12370 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
12371 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
12372 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
12373 | // .. .. .. .. START: ADD 1 MS DELAY | |
12374 | // .. .. .. .. | |
12375 | EMIT_MASKDELAY(0XF8F00200, 1), | |
12376 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
12377 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12378 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12379 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12380 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12381 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12382 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12383 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12384 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12385 | // .. .. .. FINISH: ENET1 RESET | |
12386 | // .. .. FINISH: ENET RESET | |
12387 | // .. .. START: I2C RESET | |
12388 | // .. .. .. START: I2C0 RESET | |
12389 | // .. .. .. .. START: DIR MODE GPIO BANK0 | |
12390 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | |
12391 | // .. .. .. .. START: DIR MODE GPIO BANK1 | |
12392 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | |
12393 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12394 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12395 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12396 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12397 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12398 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12399 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12400 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12401 | // .. .. .. .. START: OUTPUT ENABLE | |
12402 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
12403 | // .. .. .. .. START: OUTPUT ENABLE | |
12404 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
12405 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
12406 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
12407 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
12408 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
12409 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
12410 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
12411 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
12412 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
12413 | // .. .. .. .. START: ADD 1 MS DELAY | |
12414 | // .. .. .. .. | |
12415 | EMIT_MASKDELAY(0XF8F00200, 1), | |
12416 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
12417 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12418 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12419 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12420 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12421 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12422 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12423 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12424 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12425 | // .. .. .. FINISH: I2C0 RESET | |
12426 | // .. .. .. START: I2C1 RESET | |
12427 | // .. .. .. .. START: DIR MODE GPIO BANK0 | |
12428 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | |
12429 | // .. .. .. .. START: DIR MODE GPIO BANK1 | |
12430 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | |
12431 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12432 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12433 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12434 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12435 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12436 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12437 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12438 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12439 | // .. .. .. .. START: OUTPUT ENABLE | |
12440 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
12441 | // .. .. .. .. START: OUTPUT ENABLE | |
12442 | // .. .. .. .. FINISH: OUTPUT ENABLE | |
12443 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | |
12444 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | |
12445 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | |
12446 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | |
12447 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | |
12448 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | |
12449 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | |
12450 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | |
12451 | // .. .. .. .. START: ADD 1 MS DELAY | |
12452 | // .. .. .. .. | |
12453 | EMIT_MASKDELAY(0XF8F00200, 1), | |
12454 | // .. .. .. .. FINISH: ADD 1 MS DELAY | |
12455 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12456 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12457 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12458 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | |
12459 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12460 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | |
12461 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12462 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | |
12463 | // .. .. .. FINISH: I2C1 RESET | |
12464 | // .. .. FINISH: I2C RESET | |
12465 | // .. .. START: NOR CHIP SELECT | |
12466 | // .. .. .. START: DIR MODE BANK 0 | |
12467 | // .. .. .. FINISH: DIR MODE BANK 0 | |
12468 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12469 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | |
12470 | // .. .. .. START: OUTPUT ENABLE BANK 0 | |
12471 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | |
12472 | // .. .. FINISH: NOR CHIP SELECT | |
12473 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | |
12474 | // FINISH: top | |
12475 | // | |
12476 | EMIT_EXIT(), | |
12477 | ||
12478 | // | |
12479 | }; | |
12480 | ||
12481 | unsigned long ps7_post_config_1_0[] = { | |
12482 | // START: top | |
12483 | // .. START: SLCR SETTINGS | |
12484 | // .. UNLOCK_KEY = 0XDF0D | |
12485 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | |
12486 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | |
12487 | // .. | |
12488 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | |
12489 | // .. FINISH: SLCR SETTINGS | |
12490 | // .. START: ENABLING LEVEL SHIFTER | |
12491 | // .. USER_INP_ICT_EN_0 = 3 | |
12492 | // .. ==> 0XF8000900[1:0] = 0x00000003U | |
12493 | // .. ==> MASK : 0x00000003U VAL : 0x00000003U | |
12494 | // .. USER_INP_ICT_EN_1 = 3 | |
12495 | // .. ==> 0XF8000900[3:2] = 0x00000003U | |
12496 | // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU | |
12497 | // .. | |
12498 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | |
12499 | // .. FINISH: ENABLING LEVEL SHIFTER | |
12500 | // .. START: FPGA RESETS TO 0 | |
12501 | // .. reserved_3 = 0 | |
12502 | // .. ==> 0XF8000240[31:25] = 0x00000000U | |
12503 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | |
12504 | // .. FPGA_ACP_RST = 0 | |
12505 | // .. ==> 0XF8000240[24:24] = 0x00000000U | |
12506 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | |
12507 | // .. FPGA_AXDS3_RST = 0 | |
12508 | // .. ==> 0XF8000240[23:23] = 0x00000000U | |
12509 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | |
12510 | // .. FPGA_AXDS2_RST = 0 | |
12511 | // .. ==> 0XF8000240[22:22] = 0x00000000U | |
12512 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | |
12513 | // .. FPGA_AXDS1_RST = 0 | |
12514 | // .. ==> 0XF8000240[21:21] = 0x00000000U | |
12515 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | |
12516 | // .. FPGA_AXDS0_RST = 0 | |
12517 | // .. ==> 0XF8000240[20:20] = 0x00000000U | |
12518 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | |
12519 | // .. reserved_2 = 0 | |
12520 | // .. ==> 0XF8000240[19:18] = 0x00000000U | |
12521 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | |
12522 | // .. FSSW1_FPGA_RST = 0 | |
12523 | // .. ==> 0XF8000240[17:17] = 0x00000000U | |
12524 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | |
12525 | // .. FSSW0_FPGA_RST = 0 | |
12526 | // .. ==> 0XF8000240[16:16] = 0x00000000U | |
12527 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | |
12528 | // .. reserved_1 = 0 | |
12529 | // .. ==> 0XF8000240[15:14] = 0x00000000U | |
12530 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | |
12531 | // .. FPGA_FMSW1_RST = 0 | |
12532 | // .. ==> 0XF8000240[13:13] = 0x00000000U | |
12533 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | |
12534 | // .. FPGA_FMSW0_RST = 0 | |
12535 | // .. ==> 0XF8000240[12:12] = 0x00000000U | |
12536 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | |
12537 | // .. FPGA_DMA3_RST = 0 | |
12538 | // .. ==> 0XF8000240[11:11] = 0x00000000U | |
12539 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | |
12540 | // .. FPGA_DMA2_RST = 0 | |
12541 | // .. ==> 0XF8000240[10:10] = 0x00000000U | |
12542 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | |
12543 | // .. FPGA_DMA1_RST = 0 | |
12544 | // .. ==> 0XF8000240[9:9] = 0x00000000U | |
12545 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | |
12546 | // .. FPGA_DMA0_RST = 0 | |
12547 | // .. ==> 0XF8000240[8:8] = 0x00000000U | |
12548 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | |
12549 | // .. reserved = 0 | |
12550 | // .. ==> 0XF8000240[7:4] = 0x00000000U | |
12551 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | |
12552 | // .. FPGA3_OUT_RST = 0 | |
12553 | // .. ==> 0XF8000240[3:3] = 0x00000000U | |
12554 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | |
12555 | // .. FPGA2_OUT_RST = 0 | |
12556 | // .. ==> 0XF8000240[2:2] = 0x00000000U | |
12557 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | |
12558 | // .. FPGA1_OUT_RST = 0 | |
12559 | // .. ==> 0XF8000240[1:1] = 0x00000000U | |
12560 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | |
12561 | // .. FPGA0_OUT_RST = 0 | |
12562 | // .. ==> 0XF8000240[0:0] = 0x00000000U | |
12563 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | |
12564 | // .. | |
12565 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | |
12566 | // .. FINISH: FPGA RESETS TO 0 | |
12567 | // .. START: AFI REGISTERS | |
12568 | // .. .. START: AFI0 REGISTERS | |
12569 | // .. .. FINISH: AFI0 REGISTERS | |
12570 | // .. .. START: AFI1 REGISTERS | |
12571 | // .. .. FINISH: AFI1 REGISTERS | |
12572 | // .. .. START: AFI2 REGISTERS | |
12573 | // .. .. FINISH: AFI2 REGISTERS | |
12574 | // .. .. START: AFI3 REGISTERS | |
12575 | // .. .. FINISH: AFI3 REGISTERS | |
12576 | // .. FINISH: AFI REGISTERS | |
12577 | // .. START: LOCK IT BACK | |
12578 | // .. LOCK_KEY = 0X767B | |
12579 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | |
12580 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | |
12581 | // .. | |
12582 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | |
12583 | // .. FINISH: LOCK IT BACK | |
12584 | // FINISH: top | |
12585 | // | |
12586 | EMIT_EXIT(), | |
12587 | ||
12588 | // | |
12589 | }; | |
12590 | ||
95b237ec MY |
12591 | |
12592 | ||
12593 | #include "xil_io.h" | |
95b237ec MY |
12594 | |
12595 | unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; | |
12596 | unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; | |
12597 | unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; | |
12598 | unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; | |
12599 | unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; | |
12600 | ||
12601 | int | |
12602 | ps7_post_config() | |
12603 | { | |
12604 | // Get the PS_VERSION on run time | |
12605 | unsigned long si_ver = ps7GetSiliconVersion (); | |
12606 | int ret = -1; | |
12607 | if (si_ver == PCW_SILICON_VERSION_1) { | |
12608 | ret = ps7_config (ps7_post_config_1_0); | |
12609 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12610 | } else if (si_ver == PCW_SILICON_VERSION_2) { | |
12611 | ret = ps7_config (ps7_post_config_2_0); | |
12612 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12613 | } else { | |
12614 | ret = ps7_config (ps7_post_config_3_0); | |
12615 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12616 | } | |
12617 | return PS7_INIT_SUCCESS; | |
12618 | } | |
12619 | ||
95b237ec MY |
12620 | int |
12621 | ps7_init() | |
12622 | { | |
12623 | // Get the PS_VERSION on run time | |
12624 | unsigned long si_ver = ps7GetSiliconVersion (); | |
12625 | int ret; | |
12626 | //int pcw_ver = 0; | |
12627 | ||
12628 | if (si_ver == PCW_SILICON_VERSION_1) { | |
12629 | ps7_mio_init_data = ps7_mio_init_data_1_0; | |
12630 | ps7_pll_init_data = ps7_pll_init_data_1_0; | |
12631 | ps7_clock_init_data = ps7_clock_init_data_1_0; | |
12632 | ps7_ddr_init_data = ps7_ddr_init_data_1_0; | |
12633 | ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; | |
12634 | //pcw_ver = 1; | |
12635 | ||
12636 | } else if (si_ver == PCW_SILICON_VERSION_2) { | |
12637 | ps7_mio_init_data = ps7_mio_init_data_2_0; | |
12638 | ps7_pll_init_data = ps7_pll_init_data_2_0; | |
12639 | ps7_clock_init_data = ps7_clock_init_data_2_0; | |
12640 | ps7_ddr_init_data = ps7_ddr_init_data_2_0; | |
12641 | ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; | |
12642 | //pcw_ver = 2; | |
12643 | ||
12644 | } else { | |
12645 | ps7_mio_init_data = ps7_mio_init_data_3_0; | |
12646 | ps7_pll_init_data = ps7_pll_init_data_3_0; | |
12647 | ps7_clock_init_data = ps7_clock_init_data_3_0; | |
12648 | ps7_ddr_init_data = ps7_ddr_init_data_3_0; | |
12649 | ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; | |
12650 | //pcw_ver = 3; | |
12651 | } | |
12652 | ||
12653 | // MIO init | |
12654 | ret = ps7_config (ps7_mio_init_data); | |
12655 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12656 | ||
12657 | // PLL init | |
12658 | ret = ps7_config (ps7_pll_init_data); | |
12659 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12660 | ||
12661 | // Clock init | |
12662 | ret = ps7_config (ps7_clock_init_data); | |
12663 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12664 | ||
12665 | // DDR init | |
12666 | ret = ps7_config (ps7_ddr_init_data); | |
12667 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12668 | ||
12669 | ||
12670 | ||
12671 | // Peripherals init | |
12672 | ret = ps7_config (ps7_peripherals_init_data); | |
12673 | if (ret != PS7_INIT_SUCCESS) return ret; | |
12674 | //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); | |
12675 | return PS7_INIT_SUCCESS; | |
12676 | } | |
12677 | ||
12678 | ||
12679 | ||
12680 |